1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
21 class TargetRegisterInfo;
25 GPRRegBankID = 0, /// General Purpose Registers: W, X.
26 FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
27 CCRRegBankID = 2, /// Conditional register: NZCV.
31 extern RegisterBank GPRRegBank;
32 extern RegisterBank FPRRegBank;
33 extern RegisterBank CCRRegBank;
34 } // End AArch64 namespace.
36 /// This class provides the information for the target register banks.
37 class AArch64RegisterBankInfo final : public RegisterBankInfo {
38 /// See RegisterBankInfo::applyMapping.
39 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
41 /// Get an instruction mapping where all the operands map to
42 /// the same register bank and have similar size.
44 /// \pre MI.getNumOperands() <= 3
46 /// \return An InstructionMappings with a statically allocated
48 static InstructionMapping
49 getSameKindOfOperandsMapping(const MachineInstr &MI);
52 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
54 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
55 unsigned Size) const override;
58 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
61 getInstrAlternativeMappings(const MachineInstr &MI) const override;
63 InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
65 } // End llvm namespace.