1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
19 #define GET_REGBANK_DECLARATIONS
20 #include "AArch64GenRegisterBank.inc"
24 class TargetRegisterInfo;
26 class AArch64GenRegisterBankInfo : public RegisterBankInfo {
28 enum PartialMappingIdx {
38 PMI_FirstGPR = PMI_GPR32,
39 PMI_LastGPR = PMI_GPR64,
40 PMI_FirstFPR = PMI_FPR16,
41 PMI_LastFPR = PMI_FPR512,
42 PMI_Min = PMI_FirstFPR,
45 static RegisterBankInfo::PartialMapping PartMappings[];
46 static RegisterBankInfo::ValueMapping ValMappings[];
47 static PartialMappingIdx BankIDToCopyMapIdx[];
49 enum ValueMappingIdx {
53 DistanceBetweenRegBanks = 3,
54 FirstCrossRegCpyIdx = 25,
55 LastCrossRegCpyIdx = 39,
56 DistanceBetweenCrossRegCpy = 2,
63 static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
64 unsigned ValLength, const RegisterBank &RB);
65 static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
66 unsigned Size, unsigned Offset);
67 static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
68 PartialMappingIdx LastAlias,
69 ArrayRef<PartialMappingIdx> Order);
71 static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
73 /// Get the pointer to the ValueMapping representing the RegisterBank
74 /// at \p RBIdx with a size of \p Size.
76 /// The returned mapping works for instructions with the same kind of
77 /// operands for up to 3 operands.
79 /// \pre \p RBIdx != PartialMappingIdx::None
80 static const RegisterBankInfo::ValueMapping *
81 getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
83 /// Get the pointer to the ValueMapping of the operands of a copy
84 /// instruction from the \p SrcBankID register bank to the \p DstBankID
85 /// register bank with a size of \p Size.
86 static const RegisterBankInfo::ValueMapping *
87 getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
89 /// Get the instruction mapping for G_FPEXT.
91 /// \pre (DstSize, SrcSize) pair is one of the following:
92 /// (32, 16), (64, 16), (64, 32), (128, 64)
94 /// \return An InstructionMapping with statically allocated OperandsMapping.
95 static const RegisterBankInfo::ValueMapping *
96 getFPExtMapping(unsigned DstSize, unsigned SrcSize);
98 #define GET_TARGET_REGBANK_CLASS
99 #include "AArch64GenRegisterBank.inc"
102 /// This class provides the information for the target register banks.
103 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
104 /// See RegisterBankInfo::applyMapping.
105 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
107 /// Get an instruction mapping where all the operands map to
108 /// the same register bank and have similar size.
110 /// \pre MI.getNumOperands() <= 3
112 /// \return An InstructionMappings with a statically allocated
114 const InstructionMapping &
115 getSameKindOfOperandsMapping(const MachineInstr &MI) const;
118 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
120 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
121 unsigned Size) const override;
124 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
127 getInstrAlternativeMappings(const MachineInstr &MI) const override;
129 const InstructionMapping &
130 getInstrMapping(const MachineInstr &MI) const override;
132 } // End llvm namespace.