1 //=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 /// General Purpose Registers: W, X.
14 def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
16 /// Floating Point/Vector Registers: B, H, S, D, Q.
17 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
19 /// Conditional register: NZCV.
20 def CCRRegBank : RegisterBank<"CCR", [CCR]>;