1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64Subtarget.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
39 AArch64_MC::initLLVMToCVRegMapping(this);
43 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
44 assert(MF && "Invalid MachineFunction pointer.");
45 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
46 // GHC set of callee saved regs is empty as all those regs are
47 // used for passing STG regs around
48 return CSR_AArch64_NoRegs_SaveList;
49 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
50 return CSR_AArch64_AllRegs_SaveList;
51 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
52 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
53 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
54 CSR_AArch64_CXX_TLS_Darwin_SaveList;
55 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
56 ->supportSwiftError() &&
57 MF->getFunction().getAttributes().hasAttrSomewhere(
58 Attribute::SwiftError))
59 return CSR_AArch64_AAPCS_SwiftError_SaveList;
60 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
61 return CSR_AArch64_RT_MostRegs_SaveList;
63 return CSR_AArch64_AAPCS_SaveList;
66 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
67 const MachineFunction *MF) const {
68 assert(MF && "Invalid MachineFunction pointer.");
69 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
70 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
71 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
76 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
77 CallingConv::ID CC) const {
78 if (CC == CallingConv::GHC)
79 // This is academic because all GHC calls are (supposed to be) tail calls
80 return CSR_AArch64_NoRegs_RegMask;
81 if (CC == CallingConv::AnyReg)
82 return CSR_AArch64_AllRegs_RegMask;
83 if (CC == CallingConv::CXX_FAST_TLS)
84 return CSR_AArch64_CXX_TLS_Darwin_RegMask;
85 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
86 ->supportSwiftError() &&
87 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
88 return CSR_AArch64_AAPCS_SwiftError_RegMask;
89 if (CC == CallingConv::PreserveMost)
90 return CSR_AArch64_RT_MostRegs_RegMask;
92 return CSR_AArch64_AAPCS_RegMask;
95 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
97 return CSR_AArch64_TLS_Darwin_RegMask;
99 assert(TT.isOSBinFormatELF() && "Invalid target");
100 return CSR_AArch64_TLS_ELF_RegMask;
104 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
105 CallingConv::ID CC) const {
106 // This should return a register mask that is the same as that returned by
107 // getCallPreservedMask but that additionally preserves the register used for
108 // the first i64 argument (which must also be the register used to return a
109 // single i64 return value)
111 // In case that the calling convention does not use the same register for
112 // both, the function should return NULL (does not currently apply)
113 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
114 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
118 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
119 const AArch64FrameLowering *TFI = getFrameLowering(MF);
121 // FIXME: avoid re-calculating this every time.
122 BitVector Reserved(getNumRegs());
123 markSuperRegs(Reserved, AArch64::WSP);
124 markSuperRegs(Reserved, AArch64::WZR);
126 if (TFI->hasFP(MF) || TT.isOSDarwin())
127 markSuperRegs(Reserved, AArch64::W29);
129 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved())
130 markSuperRegs(Reserved, AArch64::W18); // Platform register
132 if (hasBasePointer(MF))
133 markSuperRegs(Reserved, AArch64::W19);
135 assert(checkAllSuperRegsMarked(Reserved));
139 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
140 unsigned Reg) const {
141 const AArch64FrameLowering *TFI = getFrameLowering(MF);
153 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
156 return TFI->hasFP(MF) || TT.isOSDarwin();
159 return hasBasePointer(MF);
165 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
166 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
169 const TargetRegisterClass *
170 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
171 unsigned Kind) const {
172 return &AArch64::GPR64spRegClass;
175 const TargetRegisterClass *
176 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
177 if (RC == &AArch64::CCRRegClass)
178 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
182 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
184 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
185 const MachineFrameInfo &MFI = MF.getFrameInfo();
187 // In the presence of variable sized objects, if the fixed stack size is
188 // large enough that referencing from the FP won't result in things being
189 // in range relatively often, we can use a base pointer to allow access
190 // from the other direction like the SP normally works.
191 // Furthermore, if both variable sized objects are present, and the
192 // stack needs to be dynamically re-aligned, the base pointer is the only
193 // reliable way to reference the locals.
194 if (MFI.hasVarSizedObjects()) {
195 if (needsStackRealignment(MF))
197 // Conservatively estimate whether the negative offset from the frame
198 // pointer will be sufficient to reach. If a function has a smallish
199 // frame, it's less likely to have lots of spills and callee saved
200 // space, so it's all more likely to be within range of the frame pointer.
201 // If it's wrong, we'll materialize the constant and still get to the
202 // object; it's just suboptimal. Negative offsets use the unscaled
203 // load/store instructions, which have a 9-bit signed immediate.
204 return MFI.getLocalFrameSize() >= 256;
211 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
212 const AArch64FrameLowering *TFI = getFrameLowering(MF);
213 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
216 bool AArch64RegisterInfo::requiresRegisterScavenging(
217 const MachineFunction &MF) const {
221 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
222 const MachineFunction &MF) const {
227 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
228 const MachineFrameInfo &MFI = MF.getFrameInfo();
229 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
230 // to the stack pointer, so only put the emergency spill slot next to the
231 // FP when there's no better way to access it (SP or base pointer).
232 return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
235 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
236 const MachineFunction &MF) const {
241 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
242 const MachineFrameInfo &MFI = MF.getFrameInfo();
243 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
245 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
248 /// needsFrameBaseReg - Returns true if the instruction's frame index
249 /// reference would be better served by a base register other than FP
250 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
251 /// references it should create new base registers for.
252 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
253 int64_t Offset) const {
254 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
255 assert(i < MI->getNumOperands() &&
256 "Instr doesn't have FrameIndex operand!");
258 // It's the load/store FI references that cause issues, as it can be difficult
259 // to materialize the offset if it won't fit in the literal field. Estimate
260 // based on the size of the local frame and some conservative assumptions
261 // about the rest of the stack frame (note, this is pre-regalloc, so
262 // we don't know everything for certain yet) whether this offset is likely
263 // to be out of range of the immediate. Return true if so.
265 // We only generate virtual base registers for loads and stores, so
266 // return false for everything else.
267 if (!MI->mayLoad() && !MI->mayStore())
270 // Without a virtual base register, if the function has variable sized
271 // objects, all fixed-size local references will be via the frame pointer,
272 // Approximate the offset and see if it's legal for the instruction.
273 // Note that the incoming offset is based on the SP value at function entry,
274 // so it'll be negative.
275 MachineFunction &MF = *MI->getParent()->getParent();
276 const AArch64FrameLowering *TFI = getFrameLowering(MF);
277 MachineFrameInfo &MFI = MF.getFrameInfo();
279 // Estimate an offset from the frame pointer.
280 // Conservatively assume all GPR callee-saved registers get pushed.
281 // FP, LR, X19-X28, D8-D15. 64-bits each.
282 int64_t FPOffset = Offset - 16 * 20;
283 // Estimate an offset from the stack pointer.
284 // The incoming offset is relating to the SP at the start of the function,
285 // but when we access the local it'll be relative to the SP after local
286 // allocation, so adjust our SP-relative offset by that allocation size.
287 Offset += MFI.getLocalFrameSize();
288 // Assume that we'll have at least some spill slots allocated.
289 // FIXME: This is a total SWAG number. We should run some statistics
290 // and pick a real one.
291 Offset += 128; // 128 bytes of spill slots
293 // If there is a frame pointer, try using it.
294 // The FP is only available if there is no dynamic realignment. We
295 // don't know for sure yet whether we'll need that, so we guess based
296 // on whether there are any local variables that would trigger it.
297 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
300 // If we can reference via the stack pointer or base pointer, try that.
301 // FIXME: This (and the code that resolves the references) can be improved
302 // to only disallow SP relative references in the live range of
303 // the VLA(s). In practice, it's unclear how much difference that
304 // would make, but it may be worth doing.
305 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
308 // The offset likely isn't legal; we want to allocate a virtual base register.
312 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
314 int64_t Offset) const {
315 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
316 assert(MI && "Unable to get the legal offset for nil instruction.");
317 int SaveOffset = Offset;
318 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
321 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
322 /// at the beginning of the basic block.
323 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
326 int64_t Offset) const {
327 MachineBasicBlock::iterator Ins = MBB->begin();
328 DebugLoc DL; // Defaults to "unknown"
329 if (Ins != MBB->end())
330 DL = Ins->getDebugLoc();
331 const MachineFunction &MF = *MBB->getParent();
332 const AArch64InstrInfo *TII =
333 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
334 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
335 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
336 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
337 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
339 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
340 .addFrameIndex(FrameIdx)
345 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
346 int64_t Offset) const {
347 int Off = Offset; // ARM doesn't need the general 64-bit offsets
350 while (!MI.getOperand(i).isFI()) {
352 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
354 const MachineFunction *MF = MI.getParent()->getParent();
355 const AArch64InstrInfo *TII =
356 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
357 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
358 assert(Done && "Unable to resolve frame index!");
362 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
363 int SPAdj, unsigned FIOperandNum,
364 RegScavenger *RS) const {
365 assert(SPAdj == 0 && "Unexpected");
367 MachineInstr &MI = *II;
368 MachineBasicBlock &MBB = *MI.getParent();
369 MachineFunction &MF = *MBB.getParent();
370 const AArch64InstrInfo *TII =
371 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
372 const AArch64FrameLowering *TFI = getFrameLowering(MF);
374 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
378 // Special handling of dbg_value, stackmap and patchpoint instructions.
379 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
380 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
381 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
383 Offset += MI.getOperand(FIOperandNum + 1).getImm();
384 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
385 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
389 // Modify MI as necessary to handle as much of 'Offset' as possible
390 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
391 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
394 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
395 "Emergency spill slot is out of reach");
397 // If we get here, the immediate doesn't fit into the instruction. We folded
398 // as much as possible above. Handle the rest, providing a register that is
400 unsigned ScratchReg =
401 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
402 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
403 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
406 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
407 MachineFunction &MF) const {
408 const AArch64FrameLowering *TFI = getFrameLowering(MF);
410 switch (RC->getID()) {
413 case AArch64::GPR32RegClassID:
414 case AArch64::GPR32spRegClassID:
415 case AArch64::GPR32allRegClassID:
416 case AArch64::GPR64spRegClassID:
417 case AArch64::GPR64allRegClassID:
418 case AArch64::GPR64RegClassID:
419 case AArch64::GPR32commonRegClassID:
420 case AArch64::GPR64commonRegClassID:
421 return 32 - 1 // XZR/SP
422 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
423 - MF.getSubtarget<AArch64Subtarget>()
424 .isX18Reserved() // X18 reserved as platform register
425 - hasBasePointer(MF); // X19
426 case AArch64::FPR8RegClassID:
427 case AArch64::FPR16RegClassID:
428 case AArch64::FPR32RegClassID:
429 case AArch64::FPR64RegClassID:
430 case AArch64::FPR128RegClassID:
433 case AArch64::DDRegClassID:
434 case AArch64::DDDRegClassID:
435 case AArch64::DDDDRegClassID:
436 case AArch64::QQRegClassID:
437 case AArch64::QQQRegClassID:
438 case AArch64::QQQQRegClassID:
441 case AArch64::FPR128_loRegClassID: