1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64Subtarget.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetOptions.h"
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42 assert(MF && "Invalid MachineFunction pointer.");
43 if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
44 // GHC set of callee saved regs is empty as all those regs are
45 // used for passing STG regs around
46 return CSR_AArch64_NoRegs_SaveList;
47 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
48 return CSR_AArch64_AllRegs_SaveList;
49 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)
50 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
51 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
52 CSR_AArch64_CXX_TLS_Darwin_SaveList;
53 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
54 ->supportSwiftError() &&
55 MF->getFunction()->getAttributes().hasAttrSomewhere(
56 Attribute::SwiftError))
57 return CSR_AArch64_AAPCS_SwiftError_SaveList;
58 if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)
59 return CSR_AArch64_RT_MostRegs_SaveList;
61 return CSR_AArch64_AAPCS_SaveList;
64 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
65 const MachineFunction *MF) const {
66 assert(MF && "Invalid MachineFunction pointer.");
67 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
68 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
69 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
74 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
75 CallingConv::ID CC) const {
76 if (CC == CallingConv::GHC)
77 // This is academic becase all GHC calls are (supposed to be) tail calls
78 return CSR_AArch64_NoRegs_RegMask;
79 if (CC == CallingConv::AnyReg)
80 return CSR_AArch64_AllRegs_RegMask;
81 if (CC == CallingConv::CXX_FAST_TLS)
82 return CSR_AArch64_CXX_TLS_Darwin_RegMask;
83 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
84 ->supportSwiftError() &&
85 MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
86 return CSR_AArch64_AAPCS_SwiftError_RegMask;
87 if (CC == CallingConv::PreserveMost)
88 return CSR_AArch64_RT_MostRegs_RegMask;
90 return CSR_AArch64_AAPCS_RegMask;
93 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
95 return CSR_AArch64_TLS_Darwin_RegMask;
97 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
98 return CSR_AArch64_TLS_ELF_RegMask;
102 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
103 CallingConv::ID CC) const {
104 // This should return a register mask that is the same as that returned by
105 // getCallPreservedMask but that additionally preserves the register used for
106 // the first i64 argument (which must also be the register used to return a
107 // single i64 return value)
109 // In case that the calling convention does not use the same register for
110 // both, the function should return NULL (does not currently apply)
111 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
112 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
116 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
117 const AArch64FrameLowering *TFI = getFrameLowering(MF);
119 // FIXME: avoid re-calculating this every time.
120 BitVector Reserved(getNumRegs());
121 markSuperRegs(Reserved, AArch64::SP);
122 markSuperRegs(Reserved, AArch64::XZR);
123 markSuperRegs(Reserved, AArch64::WSP);
124 markSuperRegs(Reserved, AArch64::WZR);
126 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
127 markSuperRegs(Reserved, AArch64::FP);
128 markSuperRegs(Reserved, AArch64::W29);
131 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
132 markSuperRegs(Reserved, AArch64::X18); // Platform register
133 markSuperRegs(Reserved, AArch64::W18);
136 if (hasBasePointer(MF)) {
137 markSuperRegs(Reserved, AArch64::X19);
138 markSuperRegs(Reserved, AArch64::W19);
141 assert(checkAllSuperRegsMarked(Reserved));
145 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
146 unsigned Reg) const {
147 const AArch64FrameLowering *TFI = getFrameLowering(MF);
159 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
162 return TFI->hasFP(MF) || TT.isOSDarwin();
165 return hasBasePointer(MF);
171 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
172 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
175 const TargetRegisterClass *
176 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
177 unsigned Kind) const {
178 return &AArch64::GPR64RegClass;
181 const TargetRegisterClass *
182 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
183 if (RC == &AArch64::CCRRegClass)
184 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
188 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
190 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
191 const MachineFrameInfo &MFI = MF.getFrameInfo();
193 // In the presence of variable sized objects, if the fixed stack size is
194 // large enough that referencing from the FP won't result in things being
195 // in range relatively often, we can use a base pointer to allow access
196 // from the other direction like the SP normally works.
197 // Furthermore, if both variable sized objects are present, and the
198 // stack needs to be dynamically re-aligned, the base pointer is the only
199 // reliable way to reference the locals.
200 if (MFI.hasVarSizedObjects()) {
201 if (needsStackRealignment(MF))
203 // Conservatively estimate whether the negative offset from the frame
204 // pointer will be sufficient to reach. If a function has a smallish
205 // frame, it's less likely to have lots of spills and callee saved
206 // space, so it's all more likely to be within range of the frame pointer.
207 // If it's wrong, we'll materialize the constant and still get to the
208 // object; it's just suboptimal. Negative offsets use the unscaled
209 // load/store instructions, which have a 9-bit signed immediate.
210 return MFI.getLocalFrameSize() >= 256;
217 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
218 const AArch64FrameLowering *TFI = getFrameLowering(MF);
219 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
222 bool AArch64RegisterInfo::requiresRegisterScavenging(
223 const MachineFunction &MF) const {
227 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
228 const MachineFunction &MF) const {
233 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
234 const MachineFrameInfo &MFI = MF.getFrameInfo();
235 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
236 // to the stack pointer, so only put the emergency spill slot next to the
237 // FP when there's no better way to access it (SP or base pointer).
238 return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
241 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
242 const MachineFunction &MF) const {
247 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
248 const MachineFrameInfo &MFI = MF.getFrameInfo();
249 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
251 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
254 /// needsFrameBaseReg - Returns true if the instruction's frame index
255 /// reference would be better served by a base register other than FP
256 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
257 /// references it should create new base registers for.
258 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
259 int64_t Offset) const {
260 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
261 assert(i < MI->getNumOperands() &&
262 "Instr doesn't have FrameIndex operand!");
264 // It's the load/store FI references that cause issues, as it can be difficult
265 // to materialize the offset if it won't fit in the literal field. Estimate
266 // based on the size of the local frame and some conservative assumptions
267 // about the rest of the stack frame (note, this is pre-regalloc, so
268 // we don't know everything for certain yet) whether this offset is likely
269 // to be out of range of the immediate. Return true if so.
271 // We only generate virtual base registers for loads and stores, so
272 // return false for everything else.
273 if (!MI->mayLoad() && !MI->mayStore())
276 // Without a virtual base register, if the function has variable sized
277 // objects, all fixed-size local references will be via the frame pointer,
278 // Approximate the offset and see if it's legal for the instruction.
279 // Note that the incoming offset is based on the SP value at function entry,
280 // so it'll be negative.
281 MachineFunction &MF = *MI->getParent()->getParent();
282 const AArch64FrameLowering *TFI = getFrameLowering(MF);
283 MachineFrameInfo &MFI = MF.getFrameInfo();
285 // Estimate an offset from the frame pointer.
286 // Conservatively assume all GPR callee-saved registers get pushed.
287 // FP, LR, X19-X28, D8-D15. 64-bits each.
288 int64_t FPOffset = Offset - 16 * 20;
289 // Estimate an offset from the stack pointer.
290 // The incoming offset is relating to the SP at the start of the function,
291 // but when we access the local it'll be relative to the SP after local
292 // allocation, so adjust our SP-relative offset by that allocation size.
293 Offset += MFI.getLocalFrameSize();
294 // Assume that we'll have at least some spill slots allocated.
295 // FIXME: This is a total SWAG number. We should run some statistics
296 // and pick a real one.
297 Offset += 128; // 128 bytes of spill slots
299 // If there is a frame pointer, try using it.
300 // The FP is only available if there is no dynamic realignment. We
301 // don't know for sure yet whether we'll need that, so we guess based
302 // on whether there are any local variables that would trigger it.
303 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
306 // If we can reference via the stack pointer or base pointer, try that.
307 // FIXME: This (and the code that resolves the references) can be improved
308 // to only disallow SP relative references in the live range of
309 // the VLA(s). In practice, it's unclear how much difference that
310 // would make, but it may be worth doing.
311 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
314 // The offset likely isn't legal; we want to allocate a virtual base register.
318 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
320 int64_t Offset) const {
321 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
322 assert(MI && "Unable to get the legal offset for nil instruction.");
323 int SaveOffset = Offset;
324 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
327 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
328 /// at the beginning of the basic block.
329 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
332 int64_t Offset) const {
333 MachineBasicBlock::iterator Ins = MBB->begin();
334 DebugLoc DL; // Defaults to "unknown"
335 if (Ins != MBB->end())
336 DL = Ins->getDebugLoc();
337 const MachineFunction &MF = *MBB->getParent();
338 const AArch64InstrInfo *TII =
339 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
340 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
341 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
342 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
343 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
345 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
346 .addFrameIndex(FrameIdx)
351 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
352 int64_t Offset) const {
353 int Off = Offset; // ARM doesn't need the general 64-bit offsets
356 while (!MI.getOperand(i).isFI()) {
358 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
360 const MachineFunction *MF = MI.getParent()->getParent();
361 const AArch64InstrInfo *TII =
362 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
363 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
364 assert(Done && "Unable to resolve frame index!");
368 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
369 int SPAdj, unsigned FIOperandNum,
370 RegScavenger *RS) const {
371 assert(SPAdj == 0 && "Unexpected");
373 MachineInstr &MI = *II;
374 MachineBasicBlock &MBB = *MI.getParent();
375 MachineFunction &MF = *MBB.getParent();
376 const AArch64InstrInfo *TII =
377 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
378 const AArch64FrameLowering *TFI = getFrameLowering(MF);
380 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
384 // Special handling of dbg_value, stackmap and patchpoint instructions.
385 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
386 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
387 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
389 Offset += MI.getOperand(FIOperandNum + 1).getImm();
390 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
391 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
395 // Modify MI as necessary to handle as much of 'Offset' as possible
396 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
397 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
400 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
401 "Emergency spill slot is out of reach");
403 // If we get here, the immediate doesn't fit into the instruction. We folded
404 // as much as possible above. Handle the rest, providing a register that is
406 unsigned ScratchReg =
407 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
408 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
409 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
412 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
413 MachineFunction &MF) const {
414 const AArch64FrameLowering *TFI = getFrameLowering(MF);
416 switch (RC->getID()) {
419 case AArch64::GPR32RegClassID:
420 case AArch64::GPR32spRegClassID:
421 case AArch64::GPR32allRegClassID:
422 case AArch64::GPR64spRegClassID:
423 case AArch64::GPR64allRegClassID:
424 case AArch64::GPR64RegClassID:
425 case AArch64::GPR32commonRegClassID:
426 case AArch64::GPR64commonRegClassID:
427 return 32 - 1 // XZR/SP
428 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
429 - MF.getSubtarget<AArch64Subtarget>()
430 .isX18Reserved() // X18 reserved as platform register
431 - hasBasePointer(MF); // X19
432 case AArch64::FPR8RegClassID:
433 case AArch64::FPR16RegClassID:
434 case AArch64::FPR32RegClassID:
435 case AArch64::FPR64RegClassID:
436 case AArch64::FPR128RegClassID:
439 case AArch64::DDRegClassID:
440 case AArch64::DDDRegClassID:
441 case AArch64::DDDDRegClassID:
442 case AArch64::QQRegClassID:
443 case AArch64::QQQRegClassID:
444 case AArch64::QQQQRegClassID:
447 case AArch64::FPR128_loRegClassID: