1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
17 #define GET_REGINFO_HEADER
18 #include "AArch64GenRegisterInfo.inc"
22 class MachineFunction;
24 class TargetRegisterClass;
27 class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
31 AArch64RegisterInfo(const Triple &TT);
33 // FIXME: This should be tablegen'd like getDwarfRegNum is
34 int getSEHRegNum(unsigned i) const {
35 return getEncodingValue(i);
38 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
39 bool isAnyArgRegReserved(const MachineFunction &MF) const;
40 void emitReservedArgRegCallError(const MachineFunction &MF) const;
42 void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
43 void UpdateCustomCallPreservedMask(MachineFunction &MF,
44 const uint32_t **Mask) const;
46 /// Code Generation virtual methods...
47 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
50 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
51 CallingConv::ID) const override;
53 unsigned getCSRFirstUseCost() const override {
54 // The cost will be compared against BlockFrequency where entry has the
55 // value of 1 << 14. A value of 5 will choose to spill or split really
56 // cold path instead of using a callee-saved register.
60 const TargetRegisterClass *
61 getSubClassWithSubReg(const TargetRegisterClass *RC,
62 unsigned Idx) const override;
64 // Calls involved in thread-local variable lookup save more registers than
65 // normal calls, so they need a different mask to represent this.
66 const uint32_t *getTLSCallPreservedMask() const;
68 // Funclets on ARM64 Windows don't preserve any registers.
69 const uint32_t *getNoPreservedMask() const override;
71 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
72 /// case that 'returned' is on an i64 first argument if the calling convention
73 /// is one that can (partially) model this attribute with a preserved mask
74 /// (i.e. it is a calling convention that uses the same register for the first
75 /// i64 argument and an i64 return value)
77 /// Should return NULL in the case that the calling convention does not have
79 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
80 CallingConv::ID) const;
82 /// Stack probing calls preserve different CSRs to the normal CC.
83 const uint32_t *getWindowsStackProbePreservedMask() const;
85 BitVector getReservedRegs(const MachineFunction &MF) const override;
86 bool isAsmClobberable(const MachineFunction &MF,
87 unsigned PhysReg) const override;
88 bool isConstantPhysReg(unsigned PhysReg) const override;
89 const TargetRegisterClass *
90 getPointerRegClass(const MachineFunction &MF,
91 unsigned Kind = 0) const override;
92 const TargetRegisterClass *
93 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
95 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
96 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
97 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
99 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
100 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
101 int64_t Offset) const override;
102 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
104 int64_t Offset) const override;
105 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
106 int64_t Offset) const override;
107 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
108 unsigned FIOperandNum,
109 RegScavenger *RS = nullptr) const override;
110 bool cannotEliminateFrame(const MachineFunction &MF) const;
112 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
113 bool hasBasePointer(const MachineFunction &MF) const;
114 unsigned getBaseRegister() const;
116 // Debug information queries.
117 unsigned getFrameRegister(const MachineFunction &MF) const override;
119 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
120 MachineFunction &MF) const override;
122 bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
127 } // end namespace llvm