contrib/llvm/lib/Target/AArch64/AArch64SchedA57.td

   1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for ARM Cortex-A57 to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // The Cortex-A57 is a traditional superscaler microprocessor with a
  17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
  18 // much wider out-of-order issue stage, this produced a need to carefully
  19 // schedule micro-ops so that all three decoded each cycle are successfully
  20 // issued as the reservation station(s) simply don't stay occupied for long.
  21 // Therefore, IssueWidth is set to the narrower of the two at three, while still
  22 // modeling the machine as out-of-order.
  23
  24 def CortexA57Model : SchedMachineModel {
  25   let IssueWidth        =   3; // 3-way decode and dispatch
  26   let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
  27   let LoadLatency       =   4; // Optimistic load latency
  28   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
  29
  30   // Enable partial & runtime unrolling. The magic number is chosen based on
  31   // experiments and benchmarking data.
  32   let LoopMicroOpBufferSize = 16;
  33   let CompleteModel = 1;
  34 }
  35
  36 //===----------------------------------------------------------------------===//
  37 // Define each kind of processor resource and number available on Cortex-A57.
  38 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
  39 // micro-ops wait for their operands and then issue out-of-order.
  40
  41 def A57UnitB : ProcResource<1>;  // Type B micro-ops
  42 def A57UnitI : ProcResource<2>;  // Type I micro-ops
  43 def A57UnitM : ProcResource<1>;  // Type M micro-ops
  44 def A57UnitL : ProcResource<1>;  // Type L micro-ops
  45 def A57UnitS : ProcResource<1>;  // Type S micro-ops
  46 def A57UnitX : ProcResource<1>;  // Type X micro-ops
  47 def A57UnitW : ProcResource<1>;  // Type W micro-ops
  48 let SchedModel = CortexA57Model in {
  49   def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>;    // Type V micro-ops
  50 }
  51
  52 let SchedModel = CortexA57Model in {
  53
  54 //===----------------------------------------------------------------------===//
  55 // Define customized scheduler read/write types specific to the Cortex-A57.
  56
  57 include "AArch64SchedA57WriteRes.td"
  58
  59 //===----------------------------------------------------------------------===//
  60 // Map the target-defined scheduler read/write resources and latency for
  61 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
  62 // defining the aliases precludes the need for mapping them using WriteRes. The
  63 // aliases are sufficient for creating a coarse, working model. As the model
  64 // evolves, InstRWs will be used to override some of these SchedAliases.
  65 //
  66 // WARNING: Using SchedAliases is convenient and works well for latency and
  67 //          resource lookup for instructions. However, this creates an entry in
  68 //          AArch64WriteLatencyTable with a WriteResourceID of 0, breaking
  69 //          any SchedReadAdvance since the lookup will fail.
  70
  71 def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
  72 def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
  73 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
  74 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
  75 def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
  76 def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
  77 def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
  78 def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
  79 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
  80 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
  81 def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
  82 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
  83 def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
  84 def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
  85 def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
  86 def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
  87 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
  88 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
  89 def : SchedAlias<WriteF,     A57Write_3cyc_1V>;
  90 def : SchedAlias<WriteFCmp,  A57Write_3cyc_1V>;
  91 def : SchedAlias<WriteFCvt,  A57Write_5cyc_1V>;
  92 def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
  93 def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
  94 def : SchedAlias<WriteFMul,  A57Write_5cyc_1V>;
  95 def : SchedAlias<WriteFDiv,  A57Write_17cyc_1W>;
  96 def : SchedAlias<WriteV,     A57Write_3cyc_1V>;
  97 def : SchedAlias<WriteVLD,   A57Write_5cyc_1L>;
  98 def : SchedAlias<WriteVST,   A57Write_1cyc_1S>;
  99
 100 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 101
 102 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 104 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 105
 106 def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
 107
 108 // Forwarding logic is only modeled for multiply and accumulate
 109 def : ReadAdvance<ReadI,       0>;
 110 def : ReadAdvance<ReadISReg,   0>;
 111 def : ReadAdvance<ReadIEReg,   0>;
 112 def : ReadAdvance<ReadIM,      0>;
 113 def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
 114 def : ReadAdvance<ReadID,      0>;
 115 def : ReadAdvance<ReadExtrHi,  0>;
 116 def : ReadAdvance<ReadAdrBase, 0>;
 117 def : ReadAdvance<ReadVLD,     0>;
 118
 119
 120 //===----------------------------------------------------------------------===//
 121 // Specialize the coarse model by associating instruction groups with the
 122 // subtarget-defined types. As the modeled is refined, this will override most
 123 // of the above ShchedAlias mappings.
 124
 125 // Miscellaneous
 126 // -----------------------------------------------------------------------------
 127
 128 def : InstRW<[WriteI], (instrs COPY)>;
 129
 130
 131 // Branch Instructions
 132 // -----------------------------------------------------------------------------
 133
 134 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
 135 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
 136
 137
 138 // Shifted Register with Shift == 0
 139 // ----------------------------------------------------------------------------
 140
 141 def A57WriteISReg : SchedWriteVariant<[
 142        SchedVar<RegShiftedPred, [WriteISReg]>,
 143        SchedVar<NoSchedPred, [WriteI]>]>;
 144 def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
 145
 146
 147 // Divide and Multiply Instructions
 148 // -----------------------------------------------------------------------------
 149
 150 // Multiply high
 151 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
 152
 153
 154 // Miscellaneous Data-Processing Instructions
 155 // -----------------------------------------------------------------------------
 156
 157 def : InstRW<[A57Write_1cyc_1I],    (instrs EXTRWrri)>;
 158 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
 159 def : InstRW<[A57Write_2cyc_1M],    (instregex "BFM")>;
 160
 161
 162 // Cryptography Extensions
 163 // -----------------------------------------------------------------------------
 164
 165 def A57ReadAES  : SchedReadAdvance<3, [A57Write_3cyc_1W]>;
 166 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>;
 167 def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>;
 168 def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
 169 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
 170 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
 171 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
 172 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
 173 def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
 174
 175
 176 // Vector Load
 177 // -----------------------------------------------------------------------------
 178
 179 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1i(8|16|32)$")>;
 180 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
 181 def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1i(64)$")>;
 182 def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1i(64)_POST$")>;
 183
 184 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(8b|4h|2s)$")>;
 185 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
 186 def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1Rv(1d)$")>;
 187 def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1Rv(1d)_POST$")>;
 188 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 189 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 190
 191 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 192 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 193 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 194 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 195 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 196 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 197 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 198 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 199 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 200 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 201 def : InstRW<[A57Write_7cyc_3L],            (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 202 def : InstRW<[A57Write_7cyc_3L, WriteAdr],  (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 203 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 204 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 205 def : InstRW<[A57Write_8cyc_4L],           (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 206 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 207
 208 def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2i(8|16)$")>;
 209 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
 210 def : InstRW<[A57Write_6cyc_2L],            (instregex "LD2i(32)$")>;
 211 def : InstRW<[A57Write_6cyc_2L, WriteAdr],  (instregex "LD2i(32)_POST$")>;
 212 def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2i(64)$")>;
 213 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2i(64)_POST$")>;
 214
 215 def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2Rv(8b|4h|2s)$")>;
 216 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2Rv(8b|4h|2s)_POST$")>;
 217 def : InstRW<[A57Write_5cyc_1L],             (instregex "LD2Rv(1d)$")>;
 218 def : InstRW<[A57Write_5cyc_1L, WriteAdr],   (instregex "LD2Rv(1d)_POST$")>;
 219 def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 220 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 221
 222 def : InstRW<[A57Write_8cyc_1L_1V],             (instregex "LD2Twov(8b|4h|2s)$")>;
 223 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 224 def : InstRW<[A57Write_9cyc_2L_2V],           (instregex "LD2Twov(16b|8h|4s)$")>;
 225 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
 226 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD2Twov(2d)$")>;
 227 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD2Twov(2d)_POST$")>;
 228
 229 def : InstRW<[A57Write_9cyc_1L_3V],           (instregex "LD3i(8|16)$")>;
 230 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
 231 def : InstRW<[A57Write_8cyc_1L_2V],            (instregex "LD3i(32)$")>;
 232 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],  (instregex "LD3i(32)_POST$")>;
 233 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD3i(64)$")>;
 234 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD3i(64)_POST$")>;
 235
 236 def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD3Rv(8b|4h|2s)$")>;
 237 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD3Rv(8b|4h|2s)_POST$")>;
 238 def : InstRW<[A57Write_6cyc_2L],              (instregex "LD3Rv(1d)$")>;
 239 def : InstRW<[A57Write_6cyc_2L, WriteAdr],    (instregex "LD3Rv(1d)_POST$")>;
 240 def : InstRW<[A57Write_9cyc_1L_3V],            (instregex "LD3Rv(16b|8h|4s)$")>;
 241 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr],  (instregex "LD3Rv(16b|8h|4s)_POST$")>;
 242 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD3Rv(2d)$")>;
 243 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
 244
 245 def : InstRW<[A57Write_9cyc_2L_2V],               (instregex "LD3Threev(8b|4h|2s)$")>;
 246 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],     (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 247 def : InstRW<[A57Write_10cyc_3L_4V],           (instregex "LD3Threev(16b|8h|4s)$")>;
 248 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
 249 def : InstRW<[A57Write_8cyc_4L],               (instregex "LD3Threev(2d)$")>;
 250 def : InstRW<[A57Write_8cyc_4L, WriteAdr],     (instregex "LD3Threev(2d)_POST$")>;
 251
 252 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(8|16)$")>;
 253 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
 254 def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD4i(32)$")>;
 255 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD4i(32)_POST$")>;
 256 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(64)$")>;
 257 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
 258
 259 def : InstRW<[A57Write_8cyc_1L_2V],              (instregex "LD4Rv(8b|4h|2s)$")>;
 260 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],    (instregex "LD4Rv(8b|4h|2s)_POST$")>;
 261 def : InstRW<[A57Write_6cyc_2L],               (instregex "LD4Rv(1d)$")>;
 262 def : InstRW<[A57Write_6cyc_2L, WriteAdr],     (instregex "LD4Rv(1d)_POST$")>;
 263 def : InstRW<[A57Write_9cyc_2L_3V],            (instregex "LD4Rv(16b|8h|4s)$")>;
 264 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr],  (instregex "LD4Rv(16b|8h|4s)_POST$")>;
 265 def : InstRW<[A57Write_9cyc_2L_4V],           (instregex "LD4Rv(2d)$")>;
 266 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
 267
 268 def : InstRW<[A57Write_9cyc_2L_2V],                (instregex "LD4Fourv(8b|4h|2s)$")>;
 269 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 270 def : InstRW<[A57Write_11cyc_4L_4V],           (instregex "LD4Fourv(16b|8h|4s)$")>;
 271 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
 272 def : InstRW<[A57Write_8cyc_4L],                (instregex "LD4Fourv(2d)$")>;
 273 def : InstRW<[A57Write_8cyc_4L, WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
 274
 275 // Vector Store
 276 // -----------------------------------------------------------------------------
 277
 278 def : InstRW<[A57Write_1cyc_1S],            (instregex "ST1i(8|16|32)$")>;
 279 def : InstRW<[A57Write_1cyc_1S, WriteAdr],  (instregex "ST1i(8|16|32)_POST$")>;
 280 def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST1i(64)$")>;
 281 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
 282
 283 def : InstRW<[A57Write_1cyc_1S],                  (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 284 def : InstRW<[A57Write_1cyc_1S, WriteAdr],        (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 285 def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 286 def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 287 def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 288 def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 289 def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 290 def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 291 def : InstRW<[A57Write_3cyc_3S],                (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 292 def : InstRW<[A57Write_3cyc_3S, WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 293 def : InstRW<[A57Write_6cyc_6S],             (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 294 def : InstRW<[A57Write_6cyc_6S, WriteAdr],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 295 def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 296 def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 297 def : InstRW<[A57Write_8cyc_8S],           (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 298 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 299
 300 def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST2i(8|16|32)$")>;
 301 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
 302 def : InstRW<[A57Write_2cyc_2S],           (instregex "ST2i(64)$")>;
 303 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
 304
 305 def : InstRW<[A57Write_3cyc_2S_1V],              (instregex "ST2Twov(8b|4h|2s)$")>;
 306 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 307 def : InstRW<[A57Write_4cyc_4S_2V],           (instregex "ST2Twov(16b|8h|4s)$")>;
 308 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
 309 def : InstRW<[A57Write_4cyc_4S],             (instregex "ST2Twov(2d)$")>;
 310 def : InstRW<[A57Write_4cyc_4S, WriteAdr],   (instregex "ST2Twov(2d)_POST$")>;
 311
 312 def : InstRW<[A57Write_3cyc_1S_1V],            (instregex "ST3i(8|16)$")>;
 313 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],  (instregex "ST3i(8|16)_POST$")>;
 314 def : InstRW<[A57Write_3cyc_3S],           (instregex "ST3i(32)$")>;
 315 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
 316 def : InstRW<[A57Write_3cyc_2S_1V],           (instregex "ST3i(64)$")>;
 317 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
 318
 319 def : InstRW<[A57Write_3cyc_3S_2V],                 (instregex "ST3Threev(8b|4h|2s)$")>;
 320 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr],       (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 321 def : InstRW<[A57Write_6cyc_6S_4V],           (instregex "ST3Threev(16b|8h|4s)$")>;
 322 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
 323 def : InstRW<[A57Write_6cyc_6S],                (instregex "ST3Threev(2d)$")>;
 324 def : InstRW<[A57Write_6cyc_6S, WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
 325
 326 def : InstRW<[A57Write_3cyc_1S_1V],             (instregex "ST4i(8|16)$")>;
 327 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],   (instregex "ST4i(8|16)_POST$")>;
 328 def : InstRW<[A57Write_4cyc_4S],           (instregex "ST4i(32)$")>;
 329 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
 330 def : InstRW<[A57Write_3cyc_2S_1V],            (instregex "ST4i(64)$")>;
 331 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],  (instregex "ST4i(64)_POST$")>;
 332
 333 def : InstRW<[A57Write_4cyc_4S_2V],                  (instregex "ST4Fourv(8b|4h|2s)$")>;
 334 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr],        (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 335 def : InstRW<[A57Write_8cyc_8S_4V],           (instregex "ST4Fourv(16b|8h|4s)$")>;
 336 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
 337 def : InstRW<[A57Write_8cyc_8S],                (instregex "ST4Fourv(2d)$")>;
 338 def : InstRW<[A57Write_8cyc_8S, WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
 339
 340 // Vector - Integer
 341 // -----------------------------------------------------------------------------
 342
 343 // Reference for forms in this group
 344 //   D form - v8i8, v4i16, v2i32
 345 //   Q form - v16i8, v8i16, v4i32
 346 //   D form - v1i8, v1i16, v1i32, v1i64
 347 //   Q form - v16i8, v8i16, v4i32, v2i64
 348 //   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
 349 //   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
 350
 351 // ASIMD absolute diff accum, D-form
 352 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
 353 // ASIMD absolute diff accum, Q-form
 354 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
 355 // ASIMD absolute diff accum long
 356 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>;
 357
 358 // ASIMD arith, reduce, 4H/4S
 359 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
 360 // ASIMD arith, reduce, 8B/8H
 361 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
 362 // ASIMD arith, reduce, 16B
 363 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
 364
 365 // ASIMD max/min, reduce, 4H/4S
 366 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
 367 // ASIMD max/min, reduce, 8B/8H
 368 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
 369 // ASIMD max/min, reduce, 16B
 370 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
 371
 372 // ASIMD multiply, D-form
 373 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
 374 // ASIMD multiply, Q-form
 375 def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
 376
 377 // ASIMD multiply accumulate, D-form
 378 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
 379 // ASIMD multiply accumulate, Q-form
 380 def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
 381
 382 // ASIMD multiply accumulate long
 383 // ASIMD multiply accumulate saturating long
 384 def A57WriteIVMA   : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
 385 def A57ReadIVMA4   : SchedReadAdvance<4, [A57WriteIVMA]>;
 386 def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>;
 387
 388 // ASIMD multiply long
 389 def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>;
 390 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
 391 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
 392
 393 // ASIMD pairwise add and accumulate
 394 // ASIMD shift accumulate
 395 def A57WriteIVA    : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
 396 def A57ReadIVA3    : SchedReadAdvance<3, [A57WriteIVA]>;
 397 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>;
 398 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
 399
 400 // ASIMD shift by immed, complex
 401 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
 402 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
 403
 404
 405 // ASIMD shift by register, basic, Q-form
 406 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
 407
 408 // ASIMD shift by register, complex, D-form
 409 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
 410
 411 // ASIMD shift by register, complex, Q-form
 412 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
 413
 414
 415 // Vector - Floating Point
 416 // -----------------------------------------------------------------------------
 417
 418 // Reference for forms in this group
 419 //   D form - v2f32
 420 //   Q form - v4f32, v2f64
 421 //   D form - 32, 64
 422 //   D form - v1i32, v1i64
 423 //   D form - v2i32
 424 //   Q form - v4i32, v2i64
 425
 426 // ASIMD FP arith, normal, D-form
 427 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
 428 // ASIMD FP arith, normal, Q-form
 429 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
 430
 431 // ASIMD FP arith, pairwise, D-form
 432 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
 433 // ASIMD FP arith, pairwise, Q-form
 434 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
 435
 436 // ASIMD FP compare, D-form
 437 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
 438 // ASIMD FP compare, Q-form
 439 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
 440
 441 // ASIMD FP convert, long and narrow
 442 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
 443 // ASIMD FP convert, other, D-form
 444 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
 445 // ASIMD FP convert, other, Q-form
 446 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
 447
 448 // ASIMD FP divide, D-form, F32
 449 def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>;
 450 // ASIMD FP divide, Q-form, F32
 451 def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>;
 452 // ASIMD FP divide, Q-form, F64
 453 def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>;
 454
 455 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
 456 // ASIMD FP square root, D-form, F32
 457 def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>;
 458 // ASIMD FP square root, Q-form, F32
 459 def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>;
 460 // ASIMD FP square root, Q-form, F64
 461 def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>;
 462
 463 // ASIMD FP max/min, normal, D-form
 464 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
 465 // ASIMD FP max/min, normal, Q-form
 466 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
 467 // ASIMD FP max/min, pairwise, D-form
 468 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
 469 // ASIMD FP max/min, pairwise, Q-form
 470 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
 471 // ASIMD FP max/min, reduce
 472 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
 473
 474 // ASIMD FP multiply, D-form, FZ
 475 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
 476 // ASIMD FP multiply, Q-form, FZ
 477 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
 478
 479 // ASIMD FP multiply accumulate, D-form, FZ
 480 // ASIMD FP multiply accumulate, Q-form, FZ
 481 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
 482 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10;  }
 483 def A57ReadFPVMA5  : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;
 484 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
 485 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
 486
 487 // ASIMD FP round, D-form
 488 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
 489 // ASIMD FP round, Q-form
 490 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
 491
 492
 493 // Vector - Miscellaneous
 494 // -----------------------------------------------------------------------------
 495
 496 // Reference for forms in this group
 497 //   D form - v8i8, v4i16, v2i32
 498 //   Q form - v16i8, v8i16, v4i32
 499 //   D form - v1i8, v1i16, v1i32, v1i64
 500 //   Q form - v16i8, v8i16, v4i32, v2i64
 501
 502 // ASIMD bitwise insert, Q-form
 503 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>;
 504
 505 // ASIMD duplicate, gen reg, D-form and Q-form
 506 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
 507 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
 508
 509 // ASIMD move, saturating
 510 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
 511
 512 // ASIMD reciprocal estimate, D-form
 513 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
 514 // ASIMD reciprocal estimate, Q-form
 515 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
 516
 517 // ASIMD reciprocal step, D-form, FZ
 518 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
 519 // ASIMD reciprocal step, Q-form, FZ
 520 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
 521
 522 // ASIMD table lookup, D-form
 523 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
 524 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
 525 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
 526 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
 527 // ASIMD table lookup, Q-form
 528 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
 529 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
 530 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
 531 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
 532
 533 // ASIMD transfer, element to gen reg
 534 def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
 535
 536 // ASIMD transfer, gen reg to element
 537 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
 538
 539 // ASIMD unzip/zip, Q-form
 540 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
 541
 542
 543 // Remainder
 544 // -----------------------------------------------------------------------------
 545
 546 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
 547
 548 def A57WriteFPMA  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
 549 def A57ReadFPMA5  : SchedReadAdvance<5, [A57WriteFPMA]>;
 550 def A57ReadFPM    : SchedReadAdvance<0>;
 551 def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 552
 553 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
 554 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
 555
 556 def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
 557 def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
 558
 559 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
 560
 561 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
 562
 563 def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
 564 def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
 565
 566 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
 567 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
 568 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
 569 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
 570 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
 571 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
 572 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
 573 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
 574 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
 575 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
 576 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
 577 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
 578 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
 579 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
 580 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
 581 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
 582 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
 583 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
 584 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
 585 def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
 586 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
 587 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
 588 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
 589 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
 590 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
 591 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
 592 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
 593 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
 594 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
 595 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
 596 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
 597 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
 598 def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
 599 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
 600 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
 601 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
 602 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
 603 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
 604 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
 605 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
 606 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
 607 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
 608 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
 609 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
 610 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
 611 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
 612 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
 613 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
 614 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
 615 def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
 616 def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
 617 def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
 618 def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
 619 def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
 620
 621 def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
 622 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
 623 def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
 624 def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
 625 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
 626 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
 627 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
 628 def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
 629 def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
 630 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
 631 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
 632 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
 633 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
 634 def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
 635 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
 636 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
 637 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
 638 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
 639 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
 640 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
 641 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
 642 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
 643 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
 644 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
 645 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
 646 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
 647 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
 648 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
 649 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
 650 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
 651 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
 652 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
 653 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
 654 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
 655 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
 656 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
 657 def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
 658 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
 659 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
 660 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
 661 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
 662 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
 663 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
 664 def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
 665
 666 } // SchedModel = CortexA57Model