contrib/llvm/lib/Target/AArch64/AArch64SchedA57.td

   1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for ARM Cortex-A57 to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def CortexA57Model : SchedMachineModel {
  16   let IssueWidth        =   8; // 3-way decode and 8-way issue
  17   let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
  18   let LoadLatency       =   4; // Optimistic load latency
  19   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
  20 }
  21
  22 //===----------------------------------------------------------------------===//
  23 // Define each kind of processor resource and number available on Cortex-A57.
  24 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
  25 // micro-ops wait for their operands and then issue out-of-order.
  26
  27 def A57UnitB : ProcResource<1> { let BufferSize = 8; }  // Type B micro-ops
  28 def A57UnitI : ProcResource<2> { let BufferSize = 8; }  // Type I micro-ops
  29 def A57UnitM : ProcResource<1> { let BufferSize = 8; }  // Type M micro-ops
  30 def A57UnitL : ProcResource<1> { let BufferSize = 8; }  // Type L micro-ops
  31 def A57UnitS : ProcResource<1> { let BufferSize = 8; }  // Type S micro-ops
  32 def A57UnitX : ProcResource<1> { let BufferSize = 8; }  // Type X micro-ops
  33 def A57UnitW : ProcResource<1> { let BufferSize = 8; }  // Type W micro-ops
  34 let SchedModel = CortexA57Model in {
  35   def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>;    // Type V micro-ops
  36 }
  37
  38
  39 let SchedModel = CortexA57Model in {
  40
  41 //===----------------------------------------------------------------------===//
  42 // Define customized scheduler read/write types specific to the Cortex-A57.
  43
  44 include "AArch64SchedA57WriteRes.td"
  45
  46 //===----------------------------------------------------------------------===//
  47 // Map the target-defined scheduler read/write resources and latency for
  48 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
  49 // defining the aliases precludes the need for mapping them using WriteRes. The
  50 // aliases are sufficient for creating a coarse, working model. As the model
  51 // evolves, InstRWs will be used to override these SchedAliases.
  52
  53 def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
  54 def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
  55 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
  56 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
  57 def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
  58 def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
  59 def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
  60 def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
  61 def : SchedAlias<WriteIM32,  A57Write_3cyc_1M>;
  62 def : SchedAlias<WriteIM64,  A57Write_5cyc_1M>;
  63 def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
  64 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
  65 def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
  66 def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
  67 def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
  68 def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
  69 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
  70 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
  71 def : SchedAlias<WriteF,     A57Write_3cyc_1V>;
  72 def : SchedAlias<WriteFCmp,  A57Write_3cyc_1V>;
  73 def : SchedAlias<WriteFCvt,  A57Write_5cyc_1V>;
  74 def : SchedAlias<WriteFCopy, A57Write_3cyc_1V>;
  75 def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
  76 def : SchedAlias<WriteFMul,  A57Write_5cyc_1V>;
  77 def : SchedAlias<WriteFDiv,  A57Write_18cyc_1X>;
  78 def : SchedAlias<WriteV,     A57Write_3cyc_1V>;
  79 def : SchedAlias<WriteVLD,   A57Write_5cyc_1L>;
  80 def : SchedAlias<WriteVST,   A57Write_1cyc_1S>;
  81
  82 def : WriteRes<WriteSys,     []> { let Latency = 1; }
  83 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
  84 def : WriteRes<WriteHint,    []> { let Latency = 1; }
  85
  86 def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
  87
  88 // Forwarding logic is not [yet] explicitly modeled beyond what is captured
  89 // in the latencies of the A57 Generic SchedWriteRes's.
  90 def : ReadAdvance<ReadI,       0>;
  91 def : ReadAdvance<ReadISReg,   0>;
  92 def : ReadAdvance<ReadIEReg,   0>;
  93 def : ReadAdvance<ReadIM,      0>;
  94 def : ReadAdvance<ReadIMA,     0>;
  95 def : ReadAdvance<ReadID,      0>;
  96 def : ReadAdvance<ReadExtrHi,  0>;
  97 def : ReadAdvance<ReadAdrBase, 0>;
  98 def : ReadAdvance<ReadVLD,     0>;
  99
 100
 101 //===----------------------------------------------------------------------===//
 102 // Specialize the coarse model by associating instruction groups with the
 103 // subtarget-defined types. As the modeled is refined, this will override most
 104 // of the above ShchedAlias mappings.
 105
 106 // Miscellaneous
 107 // -----------------------------------------------------------------------------
 108
 109 def : InstRW<[WriteI], (instrs COPY)>;
 110
 111
 112 // Branch Instructions
 113 // -----------------------------------------------------------------------------
 114
 115 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
 116 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
 117
 118
 119 // Divide and Multiply Instructions
 120 // -----------------------------------------------------------------------------
 121
 122 // Multiply high
 123 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
 124
 125
 126 // Miscellaneous Data-Processing Instructions
 127 // -----------------------------------------------------------------------------
 128
 129 def : InstRW<[A57Write_1cyc_1I],    (instrs EXTRWrri)>;
 130 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
 131 def : InstRW<[A57Write_2cyc_1M],    (instregex "BFM")>;
 132
 133
 134 // Cryptography Extensions
 135 // -----------------------------------------------------------------------------
 136
 137 def : InstRW<[A57Write_3cyc_1W], (instregex "CRC32")>;
 138
 139
 140 // Vector Load
 141 // -----------------------------------------------------------------------------
 142
 143 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1i(8|16|32)$")>;
 144 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
 145 def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1i(64)$")>;
 146 def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1i(64)_POST$")>;
 147
 148 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(8b|4h|2s)$")>;
 149 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
 150 def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1Rv(1d)$")>;
 151 def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1Rv(1d)_POST$")>;
 152 def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 153 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 154
 155 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 156 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 157 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 158 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 159 def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 160 def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 161 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 162 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 163 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 164 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 165 def : InstRW<[A57Write_7cyc_3L],            (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 166 def : InstRW<[A57Write_7cyc_3L, WriteAdr],  (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 167 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 168 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 169 def : InstRW<[A57Write_8cyc_4L],           (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 170 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 171
 172 def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2i(8|16)$")>;
 173 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
 174 def : InstRW<[A57Write_6cyc_2L],            (instregex "LD2i(32)$")>;
 175 def : InstRW<[A57Write_6cyc_2L, WriteAdr],  (instregex "LD2i(32)_POST$")>;
 176 def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2i(64)$")>;
 177 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2i(64)_POST$")>;
 178
 179 def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2Rv(8b|4h|2s)$")>;
 180 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2Rv(8b|4h|2s)_POST$")>;
 181 def : InstRW<[A57Write_5cyc_1L],             (instregex "LD2Rv(1d)$")>;
 182 def : InstRW<[A57Write_5cyc_1L, WriteAdr],   (instregex "LD2Rv(1d)_POST$")>;
 183 def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 184 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 185
 186 def : InstRW<[A57Write_8cyc_1L_1V],             (instregex "LD2Twov(8b|4h|2s)$")>;
 187 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 188 def : InstRW<[A57Write_9cyc_2L_2V],           (instregex "LD2Twov(16b|8h|4s)$")>;
 189 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
 190 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD2Twov(2d)$")>;
 191 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD2Twov(2d)_POST$")>;
 192
 193 def : InstRW<[A57Write_9cyc_1L_3V],           (instregex "LD3i(8|16)$")>;
 194 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
 195 def : InstRW<[A57Write_8cyc_1L_2V],            (instregex "LD3i(32)$")>;
 196 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],  (instregex "LD3i(32)_POST$")>;
 197 def : InstRW<[A57Write_6cyc_2L],             (instregex "LD3i(64)$")>;
 198 def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD3i(64)_POST$")>;
 199
 200 def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD3Rv(8b|4h|2s)$")>;
 201 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD3Rv(8b|4h|2s)_POST$")>;
 202 def : InstRW<[A57Write_6cyc_2L],              (instregex "LD3Rv(1d)$")>;
 203 def : InstRW<[A57Write_6cyc_2L, WriteAdr],    (instregex "LD3Rv(1d)_POST$")>;
 204 def : InstRW<[A57Write_9cyc_1L_3V],            (instregex "LD3Rv(16b|8h|4s)$")>;
 205 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr],  (instregex "LD3Rv(16b|8h|4s)_POST$")>;
 206 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD3Rv(2d)$")>;
 207 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
 208
 209 def : InstRW<[A57Write_9cyc_2L_2V],               (instregex "LD3Threev(8b|4h|2s)$")>;
 210 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],     (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 211 def : InstRW<[A57Write_10cyc_3L_4V],           (instregex "LD3Threev(16b|8h|4s)$")>;
 212 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
 213 def : InstRW<[A57Write_8cyc_4L],               (instregex "LD3Threev(2d)$")>;
 214 def : InstRW<[A57Write_8cyc_4L, WriteAdr],     (instregex "LD3Threev(2d)_POST$")>;
 215
 216 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(8|16)$")>;
 217 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
 218 def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD4i(32)$")>;
 219 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD4i(32)_POST$")>;
 220 def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(64)$")>;
 221 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
 222
 223 def : InstRW<[A57Write_8cyc_1L_2V],              (instregex "LD4Rv(8b|4h|2s)$")>;
 224 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],    (instregex "LD4Rv(8b|4h|2s)_POST$")>;
 225 def : InstRW<[A57Write_6cyc_2L],               (instregex "LD4Rv(1d)$")>;
 226 def : InstRW<[A57Write_6cyc_2L, WriteAdr],     (instregex "LD4Rv(1d)_POST$")>;
 227 def : InstRW<[A57Write_9cyc_2L_3V],            (instregex "LD4Rv(16b|8h|4s)$")>;
 228 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr],  (instregex "LD4Rv(16b|8h|4s)_POST$")>;
 229 def : InstRW<[A57Write_9cyc_2L_4V],           (instregex "LD4Rv(2d)$")>;
 230 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
 231
 232 def : InstRW<[A57Write_9cyc_2L_2V],                (instregex "LD4Fourv(8b|4h|2s)$")>;
 233 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 234 def : InstRW<[A57Write_11cyc_4L_4V],           (instregex "LD4Fourv(16b|8h|4s)$")>;
 235 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
 236 def : InstRW<[A57Write_8cyc_4L],                (instregex "LD4Fourv(2d)$")>;
 237 def : InstRW<[A57Write_8cyc_4L, WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
 238
 239 // Vector Store
 240 // -----------------------------------------------------------------------------
 241
 242 def : InstRW<[A57Write_1cyc_1S],            (instregex "ST1i(8|16|32)$")>;
 243 def : InstRW<[A57Write_1cyc_1S, WriteAdr],  (instregex "ST1i(8|16|32)_POST$")>;
 244 def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST1i(64)$")>;
 245 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
 246
 247 def : InstRW<[A57Write_1cyc_1S],                  (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 248 def : InstRW<[A57Write_1cyc_1S, WriteAdr],        (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 249 def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 250 def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 251 def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 252 def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 253 def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 254 def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 255 def : InstRW<[A57Write_3cyc_3S],                (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 256 def : InstRW<[A57Write_3cyc_3S, WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 257 def : InstRW<[A57Write_6cyc_6S],             (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 258 def : InstRW<[A57Write_6cyc_6S, WriteAdr],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 259 def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 260 def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 261 def : InstRW<[A57Write_8cyc_8S],           (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 262 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 263
 264 def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST2i(8|16|32)$")>;
 265 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
 266 def : InstRW<[A57Write_2cyc_2S],           (instregex "ST2i(64)$")>;
 267 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
 268
 269 def : InstRW<[A57Write_3cyc_2S_1V],              (instregex "ST2Twov(8b|4h|2s)$")>;
 270 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 271 def : InstRW<[A57Write_4cyc_4S_2V],           (instregex "ST2Twov(16b|8h|4s)$")>;
 272 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
 273 def : InstRW<[A57Write_4cyc_4S],             (instregex "ST2Twov(2d)$")>;
 274 def : InstRW<[A57Write_4cyc_4S, WriteAdr],   (instregex "ST2Twov(2d)_POST$")>;
 275
 276 def : InstRW<[A57Write_3cyc_1S_1V],            (instregex "ST3i(8|16)$")>;
 277 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],  (instregex "ST3i(8|16)_POST$")>;
 278 def : InstRW<[A57Write_3cyc_3S],           (instregex "ST3i(32)$")>;
 279 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
 280 def : InstRW<[A57Write_3cyc_2S_1V],           (instregex "ST3i(64)$")>;
 281 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
 282
 283 def : InstRW<[A57Write_3cyc_3S_2V],                 (instregex "ST3Threev(8b|4h|2s)$")>;
 284 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr],       (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 285 def : InstRW<[A57Write_6cyc_6S_4V],           (instregex "ST3Threev(16b|8h|4s)$")>;
 286 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
 287 def : InstRW<[A57Write_6cyc_6S],                (instregex "ST3Threev(2d)$")>;
 288 def : InstRW<[A57Write_6cyc_6S, WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
 289
 290 def : InstRW<[A57Write_3cyc_1S_1V],             (instregex "ST4i(8|16)$")>;
 291 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],   (instregex "ST4i(8|16)_POST$")>;
 292 def : InstRW<[A57Write_4cyc_4S],           (instregex "ST4i(32)$")>;
 293 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
 294 def : InstRW<[A57Write_3cyc_2S_1V],            (instregex "ST4i(64)$")>;
 295 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],  (instregex "ST4i(64)_POST$")>;
 296
 297 def : InstRW<[A57Write_4cyc_4S_2V],                  (instregex "ST4Fourv(8b|4h|2s)$")>;
 298 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr],        (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 299 def : InstRW<[A57Write_8cyc_8S_4V],           (instregex "ST4Fourv(16b|8h|4s)$")>;
 300 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
 301 def : InstRW<[A57Write_8cyc_8S],                (instregex "ST4Fourv(2d)$")>;
 302 def : InstRW<[A57Write_8cyc_8S, WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
 303
 304 } // SchedModel = CortexA57Model