contrib/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td

   1 //=- AArch64SchedExynosM1.td - Samsung Exynos M1 Sched Defs --*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for the Samsung Exynos M1 to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // The Exynos-M1 is a traditional superscalar microprocessor with a
  17 // 4-wide in-order stage for decode and dispatch and a wider issue stage.
  18 // The execution units and loads and stores are out-of-order.
  19
  20 def ExynosM1Model : SchedMachineModel {
  21   let IssueWidth            =  4; // Up to 4 uops per cycle.
  22   let MicroOpBufferSize     = 96; // ROB size.
  23   let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
  24   let LoadLatency           =  4; // Optimistic load cases.
  25   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
  26   let CompleteModel         =  1; // Use the default model otherwise.
  27
  28   list<Predicate> UnsupportedFeatures = [HasSVE];
  29 }
  30
  31 //===----------------------------------------------------------------------===//
  32 // Define each kind of processor resource and number available on the Exynos-M1,
  33 // which has 9 pipelines, each with its own queue with out-of-order dispatch.
  34
  35 let SchedModel = ExynosM1Model in {
  36
  37 def M1UnitA  : ProcResource<2>; // Simple integer
  38 def M1UnitC  : ProcResource<1>; // Simple and complex integer
  39 def M1UnitD  : ProcResource<1>; // Integer division (inside C, serialized)
  40 def M1UnitB  : ProcResource<2>; // Branch
  41 def M1UnitL  : ProcResource<1>; // Load
  42 def M1UnitS  : ProcResource<1>; // Store
  43 def M1PipeF0 : ProcResource<1>; // FP #0
  44 let Super = M1PipeF0 in {
  45   def M1UnitFMAC   : ProcResource<1>; // FP multiplication
  46   def M1UnitNAL0   : ProcResource<1>; // Simple vector
  47   def M1UnitNMISC  : ProcResource<1>; // Miscellanea
  48   def M1UnitFCVT   : ProcResource<1>; // FP conversion
  49   def M1UnitNCRYPT : ProcResource<1>; // Cryptographic
  50 }
  51 def M1PipeF1 : ProcResource<1>; // FP #1
  52 let Super = M1PipeF1 in {
  53   def M1UnitFADD : ProcResource<1>; // Simple FP
  54   def M1UnitNAL1 : ProcResource<1>; // Simple vector
  55   def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized)
  56   def M1UnitFST  : ProcResource<1>; // FP store
  57 }
  58
  59 def M1UnitALU  : ProcResGroup<[M1UnitA,
  60                                M1UnitC]>;    // All integer
  61 def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
  62                                M1UnitNAL1]>; // All simple vector
  63
  64 //===----------------------------------------------------------------------===//
  65 // Coarse scheduling model.
  66
  67 def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
  68 def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
  69 def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2;
  70                                              let ResourceCycles = [2]; }
  71 def M1WriteAB : SchedWriteRes<[M1UnitALU,
  72                                M1UnitC]>   { let Latency = 1;
  73                                              let NumMicroOps = 2; }
  74 def M1WriteAC : SchedWriteRes<[M1UnitALU,
  75                                M1UnitALU,
  76                                M1UnitC]>   { let Latency = 2;
  77                                              let NumMicroOps = 3; }
  78 def M1WriteAD : SchedWriteRes<[M1UnitALU,
  79                                M1UnitC]>   { let Latency = 2;
  80                                              let NumMicroOps = 2; }
  81 def M1WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M1WriteA1]>,
  82                                    SchedVar<ExynosLogicPred, [M1WriteA1]>,
  83                                    SchedVar<NoSchedPred,     [M1WriteAA]>]>;
  84 def M1WriteC1 : SchedWriteRes<[M1UnitC]>   { let Latency = 1; }
  85 def M1WriteC2 : SchedWriteRes<[M1UnitC]>   { let Latency = 2; }
  86
  87 def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
  88 def M1WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M1WriteAC]>,
  89                                    SchedVar<NoSchedPred,            [M1WriteAB]>]>;
  90
  91 def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
  92 def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
  93 def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6;
  94                                            let ResourceCycles = [2]; }
  95 def M1WriteLB : SchedWriteRes<[M1UnitL,
  96                                M1UnitA]> { let Latency = 4;
  97                                            let NumMicroOps = 2; }
  98 def M1WriteLC : SchedWriteRes<[M1UnitL,
  99                                M1UnitA]> { let Latency = 5;
 100                                            let NumMicroOps = 2; }
 101 def M1WriteLD : SchedWriteRes<[M1UnitL,
 102                                M1UnitA]> { let Latency = 6;
 103                                            let NumMicroOps = 2;
 104                                            let ResourceCycles = [2, 1]; }
 105 def M1WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 106                                            let NumMicroOps = 0; }
 107 def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteLC]>,
 108                                    SchedVar<NoSchedPred,   [M1WriteL5]>]>;
 109
 110 def M1WriteS1 : SchedWriteRes<[M1UnitS]>   { let Latency = 1; }
 111 def M1WriteS3 : SchedWriteRes<[M1UnitS]>   { let Latency = 3; }
 112 def M1WriteS4 : SchedWriteRes<[M1UnitS]>   { let Latency = 4; }
 113 def M1WriteSA : SchedWriteRes<[M1UnitS,
 114                                M1UnitFST,
 115                                M1UnitA]>   { let Latency = 3;
 116                                              let NumMicroOps = 2; }
 117 def M1WriteSB : SchedWriteRes<[M1UnitS,
 118                                M1UnitFST,
 119                                M1UnitS,
 120                                M1UnitFST,
 121                                M1UnitA]>   { let Latency = 3;
 122                                              let NumMicroOps = 3; }
 123 def M1WriteSC : SchedWriteRes<[M1UnitS,
 124                                M1UnitA]>   { let Latency = 2;
 125                                              let NumMicroOps = 2; }
 126 def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteSC]>,
 127                                    SchedVar<NoSchedPred,   [M1WriteS1]>]>;
 128
 129 def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
 130                                       SchedVar<NoSchedPred,   [ReadDefault]>]>;
 131
 132 // Branch instructions.
 133 def : WriteRes<WriteBr,    []>        { let Latency = 0; }
 134 def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
 135
 136 // Arithmetic and logical integer instructions.
 137 def : WriteRes<WriteI,     [M1UnitALU]> { let Latency = 1; }
 138 def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
 139 def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
 140 def : WriteRes<WriteIS,    [M1UnitALU]> { let Latency = 1; }
 141
 142 // Move instructions.
 143 def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
 144
 145 // Divide and multiply instructions.
 146 def : WriteRes<WriteID32, [M1UnitC,
 147                            M1UnitD]> { let Latency = 13;
 148                                        let ResourceCycles = [1, 13]; }
 149 def : WriteRes<WriteID64, [M1UnitC,
 150                            M1UnitD]> { let Latency = 21;
 151                                        let ResourceCycles = [1, 21]; }
 152 // TODO: Long multiplication take 5 cycles and also the ALU.
 153 def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
 154 def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4;
 155                                        let ResourceCycles = [2]; }
 156
 157 // Miscellaneous instructions.
 158 def : WriteRes<WriteExtr, [M1UnitALU,
 159                            M1UnitALU]> { let Latency = 2;
 160                                          let NumMicroOps = 2; }
 161
 162 // Addressing modes.
 163 def : WriteRes<WriteAdr, []> { let Latency = 1;
 164                                let NumMicroOps = 0; }
 165 def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
 166
 167 // Load instructions.
 168 def : WriteRes<WriteLD,    [M1UnitL]>   { let Latency = 4; }
 169 def : WriteRes<WriteLDHi,  []>          { let Latency = 4;
 170                                           let NumMicroOps = 0; }
 171 def : SchedAlias<WriteLDIdx, M1WriteLX>;
 172
 173 // Store instructions.
 174 def : WriteRes<WriteST,    [M1UnitS]> { let Latency = 1; }
 175 def : WriteRes<WriteSTP,   [M1UnitS]> { let Latency = 1; }
 176 def : WriteRes<WriteSTX,   [M1UnitS]> { let Latency = 1; }
 177 def : SchedAlias<WriteSTIdx, M1WriteSX>;
 178
 179 // FP data instructions.
 180 def : WriteRes<WriteF,    [M1UnitFADD]>  { let Latency = 3; }
 181 def : WriteRes<WriteFCmp, [M1UnitNMISC]> { let Latency = 4; }
 182 def : WriteRes<WriteFDiv, [M1UnitFVAR]>  { let Latency = 15;
 183                                            let ResourceCycles = [15]; }
 184 def : WriteRes<WriteFMul, [M1UnitFMAC]>  { let Latency = 4; }
 185
 186 // FP miscellaneous instructions.
 187 def : WriteRes<WriteFCvt,  [M1UnitFCVT]> { let Latency = 3; }
 188 def : WriteRes<WriteFImm,  [M1UnitNALU]> { let Latency = 1; }
 189 def : WriteRes<WriteFCopy, [M1UnitS]>    { let Latency = 4; }
 190
 191 // FP load instructions.
 192 def : WriteRes<WriteVLD,   [M1UnitL]> { let Latency = 5; }
 193
 194 // FP store instructions.
 195 def : WriteRes<WriteVST, [M1UnitS,
 196                           M1UnitFST]> { let Latency = 1;
 197                                         let NumMicroOps = 1; }
 198
 199 // ASIMD FP instructions.
 200 def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
 201
 202 // Other miscellaneous instructions.
 203 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 204 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 205 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 206 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 207
 208 //===----------------------------------------------------------------------===//
 209 // Fast forwarding.
 210
 211 // TODO: Add FP register forwarding rules.
 212 def : ReadAdvance<ReadI,       0>;
 213 def : ReadAdvance<ReadISReg,   0>;
 214 def : ReadAdvance<ReadIEReg,   0>;
 215 def : ReadAdvance<ReadIM,      0>;
 216 // TODO: The forwarding for WriteIM32 saves actually 2 cycles.
 217 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 218 def : ReadAdvance<ReadID,      0>;
 219 def : ReadAdvance<ReadExtrHi,  0>;
 220 def : ReadAdvance<ReadAdrBase, 0>;
 221 def : ReadAdvance<ReadVLD,     0>;
 222
 223 //===----------------------------------------------------------------------===//
 224 // Finer scheduling model.
 225
 226 def M1WriteNEONA   : SchedWriteRes<[M1UnitNALU,
 227                                     M1UnitNALU,
 228                                     M1UnitFADD]>   { let Latency = 9;
 229                                                      let NumMicroOps = 3; }
 230 def M1WriteNEONB   : SchedWriteRes<[M1UnitNALU,
 231                                     M1UnitFST]>    { let Latency = 5;
 232                                                      let NumMicroOps = 2;}
 233 def M1WriteNEONC   : SchedWriteRes<[M1UnitNALU,
 234                                     M1UnitFST]>    { let Latency = 6;
 235                                                      let NumMicroOps = 2; }
 236 def M1WriteNEOND   : SchedWriteRes<[M1UnitNALU,
 237                                     M1UnitFST,
 238                                     M1UnitL]>      { let Latency = 10;
 239                                                      let NumMicroOps = 3; }
 240 def M1WriteNEONE   : SchedWriteRes<[M1UnitFCVT,
 241                                     M1UnitFST]>    { let Latency = 8;
 242                                                      let NumMicroOps = 2; }
 243 def M1WriteNEONF   : SchedWriteRes<[M1UnitFCVT,
 244                                     M1UnitFST,
 245                                     M1UnitL]>      { let Latency = 13;
 246                                                      let NumMicroOps = 3; }
 247 def M1WriteNEONG   : SchedWriteRes<[M1UnitNMISC,
 248                                     M1UnitFST]>    { let Latency = 6;
 249                                                      let NumMicroOps = 2; }
 250 def M1WriteNEONH   : SchedWriteRes<[M1UnitNALU,
 251                                     M1UnitFST]>    { let Latency = 3;
 252                                                      let NumMicroOps = 2; }
 253 def M1WriteNEONI   : SchedWriteRes<[M1UnitFST,
 254                                     M1UnitL]>      { let Latency = 9;
 255                                                      let NumMicroOps = 2; }
 256 def M1WriteNEONJ   : SchedWriteRes<[M1UnitNMISC,
 257                                     M1UnitFMAC]>   { let Latency = 6;
 258                                                      let NumMicroOps = 2; }
 259 def M1WriteNEONK   : SchedWriteRes<[M1UnitNMISC,
 260                                     M1UnitFMAC]>   { let Latency = 7;
 261                                                      let NumMicroOps = 2; }
 262 def M1WriteNEONL   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2;
 263                                                      let ResourceCycles = [2]; }
 264 def M1WriteFADD3   : SchedWriteRes<[M1UnitFADD]>   { let Latency = 3; }
 265 def M1WriteFCVT3   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 3; }
 266 def M1WriteFCVT4   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 4; }
 267 def M1WriteFMAC4   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 4; }
 268 def M1WriteFMAC5   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 5; }
 269 // TODO
 270 def M1WriteFVAR15  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 15;
 271                                                      let ResourceCycles = [15]; }
 272 def M1WriteFVAR23  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 23;
 273                                                      let ResourceCycles = [23]; }
 274 def M1WriteNALU1   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 1; }
 275 def M1WriteNALU2   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2; }
 276 def M1WriteNAL11   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 1; }
 277 def M1WriteNAL12   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 2; }
 278 def M1WriteNAL13   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 3; }
 279 def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
 280 def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; }
 281 def M1WriteNMISC1  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 1; }
 282 def M1WriteNMISC2  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 2; }
 283 def M1WriteNMISC3  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 3; }
 284 def M1WriteNMISC4  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 4; }
 285 def M1WriteTB      : SchedWriteRes<[M1UnitC,
 286                                     M1UnitALU]>    { let Latency = 2;
 287                                                      let NumMicroOps = 2; }
 288 def M1WriteVLDA    : SchedWriteRes<[M1UnitL,
 289                                     M1UnitL]>      { let Latency = 6;
 290                                                      let NumMicroOps = 2; }
 291 def M1WriteVLDB    : SchedWriteRes<[M1UnitL,
 292                                     M1UnitL,
 293                                     M1UnitL]>      { let Latency = 7;
 294                                                      let NumMicroOps = 3; }
 295 def M1WriteVLDC    : SchedWriteRes<[M1UnitL,
 296                                     M1UnitL,
 297                                     M1UnitL,
 298                                     M1UnitL]>      { let Latency = 8;
 299                                                      let NumMicroOps = 4; }
 300 def M1WriteVLDD    : SchedWriteRes<[M1UnitL,
 301                                     M1UnitNALU]>   { let Latency = 7;
 302                                                      let NumMicroOps = 2;
 303                                                      let ResourceCycles = [2, 1]; }
 304 def M1WriteVLDE    : SchedWriteRes<[M1UnitL,
 305                                     M1UnitNALU]>   { let Latency = 6;
 306                                                      let NumMicroOps = 2; }
 307 def M1WriteVLDF    : SchedWriteRes<[M1UnitL,
 308                                     M1UnitL]>      { let Latency = 10;
 309                                                      let NumMicroOps = 2;
 310                                                      let ResourceCycles = [1, 1]; }
 311 def M1WriteVLDG    : SchedWriteRes<[M1UnitL,
 312                                     M1UnitNALU,
 313                                     M1UnitNALU]>   { let Latency = 7;
 314                                                      let NumMicroOps = 3;
 315                                                      let ResourceCycles = [2, 1, 1]; }
 316 def M1WriteVLDH    : SchedWriteRes<[M1UnitL,
 317                                     M1UnitNALU,
 318                                     M1UnitNALU]>   { let Latency = 6;
 319                                                      let NumMicroOps = 3; }
 320 def M1WriteVLDI    : SchedWriteRes<[M1UnitL,
 321                                     M1UnitL,
 322                                     M1UnitL]>      { let Latency = 12;
 323                                                      let NumMicroOps = 3;
 324                                                      let ResourceCycles = [2, 2, 2]; }
 325 def M1WriteVLDJ    : SchedWriteRes<[M1UnitL,
 326                                     M1UnitNALU,
 327                                     M1UnitNALU,
 328                                     M1UnitNALU]>   { let Latency = 9;
 329                                                      let NumMicroOps = 4;
 330                                                      let ResourceCycles = [2, 1, 1, 1]; }
 331 def M1WriteVLDK    : SchedWriteRes<[M1UnitL,
 332                                     M1UnitNALU,
 333                                     M1UnitNALU,
 334                                     M1UnitNALU,
 335                                     M1UnitNALU]>   { let Latency = 9;
 336                                                      let NumMicroOps = 5;
 337                                                      let ResourceCycles = [2, 1, 1, 1, 1]; }
 338 def M1WriteVLDL    : SchedWriteRes<[M1UnitL,
 339                                     M1UnitNALU,
 340                                     M1UnitNALU,
 341                                     M1UnitL,
 342                                     M1UnitNALU]>   { let Latency = 7;
 343                                                      let NumMicroOps = 5;
 344                                                      let ResourceCycles = [1, 1, 1, 1, 1]; }
 345 def M1WriteVLDM    : SchedWriteRes<[M1UnitL,
 346                                     M1UnitNALU,
 347                                     M1UnitNALU,
 348                                     M1UnitL,
 349                                     M1UnitNALU,
 350                                     M1UnitNALU]>   { let Latency = 7;
 351                                                      let NumMicroOps = 6;
 352                                                      let ResourceCycles = [1, 1, 1, 1, 1, 1]; }
 353 def M1WriteVLDN    : SchedWriteRes<[M1UnitL,
 354                                     M1UnitL,
 355                                     M1UnitL,
 356                                     M1UnitL]>      { let Latency = 14;
 357                                                      let NumMicroOps = 4;
 358                                                      let ResourceCycles = [2, 1, 2, 1]; }
 359 def M1WriteVSTA    : WriteSequence<[WriteVST], 2>;
 360 def M1WriteVSTB    : WriteSequence<[WriteVST], 3>;
 361 def M1WriteVSTC    : WriteSequence<[WriteVST], 4>;
 362 def M1WriteVSTD    : SchedWriteRes<[M1UnitS,
 363                                     M1UnitFST,
 364                                     M1UnitFST]>    { let Latency = 7;
 365                                                      let NumMicroOps = 2;
 366                                                      let ResourceCycles = [7, 1, 1]; }
 367 def M1WriteVSTE    : SchedWriteRes<[M1UnitS,
 368                                     M1UnitFST,
 369                                     M1UnitS,
 370                                     M1UnitFST,
 371                                     M1UnitFST]>    { let Latency = 8;
 372                                                      let NumMicroOps = 3;
 373                                                      let ResourceCycles = [7, 1, 1, 1, 1]; }
 374 def M1WriteVSTF    : SchedWriteRes<[M1UnitNALU,
 375                                     M1UnitS,
 376                                     M1UnitFST,
 377                                     M1UnitS,
 378                                     M1UnitFST,
 379                                     M1UnitFST,
 380                                     M1UnitFST]>     { let Latency = 15;
 381                                                       let NumMicroOps = 5;
 382                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1]; }
 383 def M1WriteVSTG    : SchedWriteRes<[M1UnitNALU,
 384                                     M1UnitS,
 385                                     M1UnitFST,
 386                                     M1UnitS,
 387                                     M1UnitFST,
 388                                     M1UnitS,
 389                                     M1UnitFST,
 390                                     M1UnitFST,
 391                                     M1UnitFST]>     { let Latency = 16;
 392                                                       let NumMicroOps = 6;
 393                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1]; }
 394 def M1WriteVSTH    : SchedWriteRes<[M1UnitNALU,
 395                                     M1UnitS,
 396                                     M1UnitFST,
 397                                     M1UnitFST,
 398                                     M1UnitFST]>     { let Latency = 14;
 399                                                       let NumMicroOps = 4;
 400                                                       let ResourceCycles = [1, 7, 1, 7, 1]; }
 401 def M1WriteVSTI    : SchedWriteRes<[M1UnitNALU,
 402                                     M1UnitS,
 403                                     M1UnitFST,
 404                                     M1UnitS,
 405                                     M1UnitFST,
 406                                     M1UnitS,
 407                                     M1UnitFST,
 408                                     M1UnitS,
 409                                     M1UnitFST,
 410                                     M1UnitFST,
 411                                     M1UnitFST]>     { let Latency = 17;
 412                                                       let NumMicroOps = 7;
 413                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]; }
 414
 415 // Special cases.
 416 def M1WriteAES  : SchedWriteRes<[M1UnitNCRYPT]>     { let Latency = 1; }
 417 def M1WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M1WriteNALU1]>,
 418                                      SchedVar<NoSchedPred,  [M1WriteA1]>]>;
 419
 420 // Fast forwarding.
 421 def M1ReadAES : SchedReadAdvance<1, [M1WriteAES]>;
 422
 423 // Branch instructions
 424 def : InstRW<[M1WriteB1], (instrs Bcc)>;
 425 def : InstRW<[M1WriteA1], (instrs BL)>;
 426 def : InstRW<[M1WriteBX], (instrs BLR)>;
 427 def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
 428 def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>;
 429
 430 // Arithmetic and logical integer instructions.
 431 def : InstRW<[M1WriteAX], (instregex ".+rx(64)?$")>;
 432 def : InstRW<[M1WriteAX], (instregex ".+rs$")>;
 433
 434 // Move instructions.
 435 def : InstRW<[M1WriteCOPY], (instrs COPY)>;
 436
 437 // Divide and multiply instructions.
 438
 439 // Miscellaneous instructions.
 440
 441 // Load instructions.
 442 def : InstRW<[M1WriteLB,
 443               WriteLDHi,
 444               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 445 def : InstRW<[M1WriteLC,
 446               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 447 def : InstRW<[M1WriteL5,
 448               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 449 def : InstRW<[M1WriteLC,
 450               ReadAdrBase], (instrs PRFMroW)>;
 451 def : InstRW<[M1WriteL5,
 452               ReadAdrBase], (instrs PRFMroX)>;
 453
 454 // Store instructions.
 455 def : InstRW<[M1WriteSC,
 456               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 457 def : InstRW<[WriteST,
 458               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 459
 460 // FP data instructions.
 461 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)[DS]r")>;
 462 def : InstRW<[M1WriteFADD3],  (instregex "^F(ADD|SUB)[DS]rr")>;
 463 def : InstRW<[M1WriteNEONG],  (instregex "^FCCMPE?[DS]rr")>;
 464 def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>;
 465 def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>;
 466 def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>;
 467 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>;
 468 def : InstRW<[M1WriteFMAC4],  (instregex "^FN?MUL[DS]rr")>;
 469 def : InstRW<[M1WriteFMAC5],  (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 470 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT.+r")>;
 471 def : InstRW<[M1WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 472 def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>;
 473 def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>;
 474
 475 // FP miscellaneous instructions.
 476 def : InstRW<[M1WriteFCVT3],  (instregex "^FCVT[DS][DS]r")>;
 477 def : InstRW<[M1WriteNEONF],  (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
 478 def : InstRW<[M1WriteNEONE],  (instregex "^[SU]CVTF[SU]")>;
 479 def : InstRW<[M1WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 480 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 481 def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>;
 482 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 483 def : InstRW<[M1WriteS4],     (instregex "^FMOV[WX][DS](High)?r")>;
 484 def : InstRW<[M1WriteNEONI],  (instregex "^FMOV[DS][WX](High)?r")>;
 485
 486 // FP load instructions.
 487 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 488 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 489 def : InstRW<[WriteVLD,
 490               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 491 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 492 def : InstRW<[M1WriteLD,
 493               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 494 def : InstRW<[WriteVLD,
 495               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
 496 def : InstRW<[M1WriteLD,
 497               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 498 def : InstRW<[WriteVLD,
 499               M1WriteLH],   (instregex "^LDN?P[DS]i")>;
 500 def : InstRW<[M1WriteLA,
 501               M1WriteLH],   (instregex "^LDN?PQi")>;
 502 def : InstRW<[M1WriteLC,
 503               M1WriteLH,
 504               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 505 def : InstRW<[M1WriteLD,
 506               M1WriteLH,
 507               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 508
 509 // FP store instructions.
 510 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 511 def : InstRW<[WriteVST,
 512               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 513 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 514 def : InstRW<[M1WriteSA,
 515               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
 516 def : InstRW<[WriteVST,
 517               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
 518 def : InstRW<[M1WriteSA,
 519               ReadAdrBase], (instregex "^STRQro[WX]")>;
 520 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 521 def : InstRW<[WriteVST,
 522               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 523 def : InstRW<[M1WriteSB,
 524               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 525
 526 // ASIMD instructions.
 527 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
 528 def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>;
 529 def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>;
 530 def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>;
 531 def : InstRW<[M1WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 532 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>;
 533 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>;
 534 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>;
 535 def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>;
 536 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>;
 537 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>;
 538 def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 539 def : InstRW<[M1WriteNALU1],  (instregex "^CMTSTv")>;
 540 def : InstRW<[M1WriteNALU1],  (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 541 def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>;
 542 def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>;
 543 def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>;
 544 def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>;
 545 def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>;
 546 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>;
 547 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>;
 548 def : InstRW<[M1WriteNAL13],  (instregex "^(S|SR|U|UR)SRAv")>;
 549 def : InstRW<[M1WriteNALU1],  (instregex "^SHL[dv]")>;
 550 def : InstRW<[M1WriteNALU1],  (instregex "^[SU]SH[LR][dv]")>;
 551 def : InstRW<[M1WriteNALU1],  (instregex "^S[RS]I[dv]")>;
 552 def : InstRW<[M1WriteNAL13],  (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 553 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]RSH[LR][dv]")>;
 554 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 555
 556 // ASIMD FP instructions.
 557 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)v")>;
 558 def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>;
 559 def : InstRW<[M1WriteNEONA],  (instregex "^FADDP")>;
 560 def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 561 def : InstRW<[M1WriteFCVT3],  (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>;
 562 def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>;
 563 def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>;
 564 def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>;
 565 def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>;
 566 def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>;
 567 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
 568 def : InstRW<[M1WriteNEONJ],  (instregex "^FMULX?v.i")>;
 569 def : InstRW<[M1WriteFMAC4],  (instregex "^FMULX?v.f")>;
 570 def : InstRW<[M1WriteNEONK],  (instregex "^FML[AS]v.i")>;
 571 def : InstRW<[M1WriteFMAC5],  (instregex "^FML[AS]v.f")>;
 572 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT[AIMNPXZ]v")>;
 573
 574 // ASIMD miscellaneous instructions.
 575 def : InstRW<[M1WriteNALU1],  (instregex "^RBITv")>;
 576 def : InstRW<[M1WriteNAL11],  (instregex "^(BIF|BIT|BSL)v")>;
 577 def : InstRW<[M1WriteNEONB],  (instregex "^DUPv.+gpr")>;
 578 def : InstRW<[M1WriteNALU1],  (instregex "^DUPv.+lane")>;
 579 def : InstRW<[M1WriteNALU1],  (instregex "^EXTv8")>;
 580 def : InstRW<[M1WriteNEONL],  (instregex "^EXTv16")>;
 581 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]?Q?XTU?Nv")>;
 582 def : InstRW<[M1WriteNALU1],  (instregex "^CPY")>;
 583 def : InstRW<[M1WriteNALU1],  (instregex "^INSv.+lane")>;
 584 def : InstRW<[M1WriteNALU1],  (instregex "^MOVI[Dv]")>;
 585 def : InstRW<[M1WriteNALU1],  (instregex "^FMOVv")>;
 586 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 587 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)Sv")>;
 588 def : InstRW<[M1WriteNALU1],  (instregex "^REV(16|32|64)v")>;
 589 def : InstRW<[M1WriteNAL11],  (instregex "^TB[LX]v8i8One")>;
 590 def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
 591                               (instregex "^TB[LX]v8i8Two")>;
 592 def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
 593                               (instregex "^TB[LX]v8i8Three")>;
 594 def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
 595                               (instregex "^TB[LX]v8i8Four")>;
 596 def : InstRW<[M1WriteNAL12],  (instregex "^TB[LX]v16i8One")>;
 597 def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
 598                               (instregex "^TB[LX]v16i8Two")>;
 599 def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
 600                               (instregex "^TB[LX]v16i8Three")>;
 601 def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
 602                               (instregex "^TB[LX]v16i8Four")>;
 603 def : InstRW<[M1WriteNEOND],  (instregex "^[SU]MOVv")>;
 604 def : InstRW<[M1WriteNEONC],  (instregex "^INSv.+gpr")>;
 605 def : InstRW<[M1WriteNALU1],  (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>;
 606 def : InstRW<[M1WriteNALU2],  (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>;
 607 def : InstRW<[M1WriteNALU1],  (instregex "^ZIP[12]v")>;
 608
 609 // ASIMD load instructions.
 610 def : InstRW<[M1WriteVLDD],   (instregex "LD1i(8|16|32)$")>;
 611 def : InstRW<[M1WriteVLDD,
 612               WriteAdr],      (instregex "LD1i(8|16|32)_POST$")>;
 613 def : InstRW<[M1WriteVLDE],   (instregex "LD1i(64)$")>;
 614 def : InstRW<[M1WriteVLDE,
 615               WriteAdr],      (instregex "LD1i(64)_POST$")>;
 616
 617 def : InstRW<[WriteVLD],      (instregex "LD1Rv(8b|4h|2s)$")>;
 618 def : InstRW<[WriteVLD,
 619               WriteAdr],      (instregex "LD1Rv(8b|4h|2s)_POST$")>;
 620 def : InstRW<[WriteVLD],      (instregex "LD1Rv(1d)$")>;
 621 def : InstRW<[WriteVLD,
 622               WriteAdr],      (instregex "LD1Rv(1d)_POST$")>;
 623 def : InstRW<[WriteVLD],      (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 624 def : InstRW<[WriteVLD,
 625               WriteAdr],      (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 626
 627 def : InstRW<[WriteVLD],      (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 628 def : InstRW<[WriteVLD,
 629               WriteAdr],      (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 630 def : InstRW<[WriteVLD],      (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 631 def : InstRW<[WriteVLD,
 632               WriteAdr],      (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 633 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 634 def : InstRW<[M1WriteVLDA,
 635               WriteAdr],      (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 636 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 637 def : InstRW<[M1WriteVLDA,
 638               WriteAdr],      (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 639 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 640 def : InstRW<[M1WriteVLDB,
 641               WriteAdr],      (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 642 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 643 def : InstRW<[M1WriteVLDB,
 644               WriteAdr],      (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 645 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 646 def : InstRW<[M1WriteVLDC,
 647               WriteAdr],      (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 648 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 649 def : InstRW<[M1WriteVLDC,
 650               WriteAdr],      (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 651
 652 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(8|16)$")>;
 653 def : InstRW<[M1WriteVLDG,
 654               WriteAdr],      (instregex "LD2i(8|16)_POST$")>;
 655 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(32)$")>;
 656 def : InstRW<[M1WriteVLDG,
 657               WriteAdr],      (instregex "LD2i(32)_POST$")>;
 658 def : InstRW<[M1WriteVLDH],   (instregex "LD2i(64)$")>;
 659 def : InstRW<[M1WriteVLDH,
 660               WriteAdr],      (instregex "LD2i(64)_POST$")>;
 661
 662 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(8b|4h|2s)$")>;
 663 def : InstRW<[M1WriteVLDA,
 664               WriteAdr],      (instregex "LD2Rv(8b|4h|2s)_POST$")>;
 665 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(1d)$")>;
 666 def : InstRW<[M1WriteVLDA,
 667               WriteAdr],      (instregex "LD2Rv(1d)_POST$")>;
 668 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 669 def : InstRW<[M1WriteVLDA,
 670               WriteAdr],      (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 671
 672 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(8b|4h|2s)$")>;
 673 def : InstRW<[M1WriteVLDF,
 674               WriteAdr],      (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 675 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(16b|8h|4s)$")>;
 676 def : InstRW<[M1WriteVLDF,
 677               WriteAdr],      (instregex "LD2Twov(16b|8h|4s)_POST$")>;
 678 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(2d)$")>;
 679 def : InstRW<[M1WriteVLDF,
 680               WriteAdr],      (instregex "LD2Twov(2d)_POST$")>;
 681
 682 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(8|16)$")>;
 683 def : InstRW<[M1WriteVLDJ,
 684               WriteAdr],      (instregex "LD3i(8|16)_POST$")>;
 685 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(32)$")>;
 686 def : InstRW<[M1WriteVLDJ,
 687               WriteAdr],      (instregex "LD3i(32)_POST$")>;
 688 def : InstRW<[M1WriteVLDL],   (instregex "LD3i(64)$")>;
 689 def : InstRW<[M1WriteVLDL,
 690               WriteAdr],      (instregex "LD3i(64)_POST$")>;
 691
 692 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(8b|4h|2s)$")>;
 693 def : InstRW<[M1WriteVLDB,
 694               WriteAdr],      (instregex "LD3Rv(8b|4h|2s)_POST$")>;
 695 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(1d)$")>;
 696 def : InstRW<[M1WriteVLDB,
 697               WriteAdr],      (instregex "LD3Rv(1d)_POST$")>;
 698 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(16b|8h|4s)$")>;
 699 def : InstRW<[M1WriteVLDB,
 700               WriteAdr],      (instregex "LD3Rv(16b|8h|4s)_POST$")>;
 701 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(2d)$")>;
 702 def : InstRW<[M1WriteVLDB,
 703               WriteAdr],      (instregex "LD3Rv(2d)_POST$")>;
 704
 705 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(8b|4h|2s)$")>;
 706 def : InstRW<[M1WriteVLDI,
 707               WriteAdr],      (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 708 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(16b|8h|4s)$")>;
 709 def : InstRW<[M1WriteVLDI,
 710               WriteAdr],      (instregex "LD3Threev(16b|8h|4s)_POST$")>;
 711 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(2d)$")>;
 712 def : InstRW<[M1WriteVLDI,
 713               WriteAdr],      (instregex "LD3Threev(2d)_POST$")>;
 714
 715 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(8|16)$")>;
 716 def : InstRW<[M1WriteVLDK,
 717               WriteAdr],      (instregex "LD4i(8|16)_POST$")>;
 718 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(32)$")>;
 719 def : InstRW<[M1WriteVLDK,
 720               WriteAdr],      (instregex "LD4i(32)_POST$")>;
 721 def : InstRW<[M1WriteVLDM],   (instregex "LD4i(64)$")>;
 722 def : InstRW<[M1WriteVLDM,
 723               WriteAdr],      (instregex "LD4i(64)_POST$")>;
 724
 725 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(8b|4h|2s)$")>;
 726 def : InstRW<[M1WriteVLDC,
 727               WriteAdr],      (instregex "LD4Rv(8b|4h|2s)_POST$")>;
 728 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(1d)$")>;
 729 def : InstRW<[M1WriteVLDC,
 730               WriteAdr],      (instregex "LD4Rv(1d)_POST$")>;
 731 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(16b|8h|4s)$")>;
 732 def : InstRW<[M1WriteVLDC,
 733               WriteAdr],      (instregex "LD4Rv(16b|8h|4s)_POST$")>;
 734 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(2d)$")>;
 735 def : InstRW<[M1WriteVLDC,
 736               WriteAdr],      (instregex "LD4Rv(2d)_POST$")>;
 737
 738 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(8b|4h|2s)$")>;
 739 def : InstRW<[M1WriteVLDN,
 740               WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 741 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(16b|8h|4s)$")>;
 742 def : InstRW<[M1WriteVLDN,
 743               WriteAdr],      (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
 744 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(2d)$")>;
 745 def : InstRW<[M1WriteVLDN,
 746               WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
 747
 748 // ASIMD store instructions.
 749 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(8|16|32)$")>;
 750 def : InstRW<[M1WriteVSTD,
 751               WriteAdr],      (instregex "ST1i(8|16|32)_POST$")>;
 752 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(64)$")>;
 753 def : InstRW<[M1WriteVSTD,
 754               WriteAdr],      (instregex "ST1i(64)_POST$")>;
 755
 756 def : InstRW<[WriteVST],      (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 757 def : InstRW<[WriteVST,
 758               WriteAdr],      (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 759 def : InstRW<[WriteVST],      (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 760 def : InstRW<[WriteVST,
 761               WriteAdr],      (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 762 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 763 def : InstRW<[M1WriteVSTA,
 764               WriteAdr],      (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 765 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 766 def : InstRW<[M1WriteVSTA,
 767               WriteAdr],      (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 768 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 769 def : InstRW<[M1WriteVSTB,
 770               WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 771 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 772 def : InstRW<[M1WriteVSTB,
 773               WriteAdr],      (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 774 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 775 def : InstRW<[M1WriteVSTC,
 776               WriteAdr],      (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 777 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 778 def : InstRW<[M1WriteVSTC,
 779               WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 780
 781 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(8|16|32)$")>;
 782 def : InstRW<[M1WriteVSTD,
 783               WriteAdr],      (instregex "ST2i(8|16|32)_POST$")>;
 784 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(64)$")>;
 785 def : InstRW<[M1WriteVSTD,
 786               WriteAdr],      (instregex "ST2i(64)_POST$")>;
 787
 788 def : InstRW<[M1WriteVSTD],   (instregex "ST2Twov(8b|4h|2s)$")>;
 789 def : InstRW<[M1WriteVSTD,
 790               WriteAdr],      (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 791 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(16b|8h|4s)$")>;
 792 def : InstRW<[M1WriteVSTE,
 793               WriteAdr],      (instregex "ST2Twov(16b|8h|4s)_POST$")>;
 794 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(2d)$")>;
 795 def : InstRW<[M1WriteVSTE,
 796               WriteAdr],      (instregex "ST2Twov(2d)_POST$")>;
 797
 798 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(8|16)$")>;
 799 def : InstRW<[M1WriteVSTH,
 800               WriteAdr],      (instregex "ST3i(8|16)_POST$")>;
 801 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(32)$")>;
 802 def : InstRW<[M1WriteVSTH,
 803               WriteAdr],      (instregex "ST3i(32)_POST$")>;
 804 def : InstRW<[M1WriteVSTF],   (instregex "ST3i(64)$")>;
 805 def : InstRW<[M1WriteVSTF,
 806               WriteAdr],      (instregex "ST3i(64)_POST$")>;
 807
 808 def : InstRW<[M1WriteVSTF],   (instregex "ST3Threev(8b|4h|2s)$")>;
 809 def : InstRW<[M1WriteVSTF,
 810               WriteAdr],      (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 811 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(16b|8h|4s)$")>;
 812 def : InstRW<[M1WriteVSTG,
 813               WriteAdr],      (instregex "ST3Threev(16b|8h|4s)_POST$")>;
 814 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(2d)$")>;
 815 def : InstRW<[M1WriteVSTG,
 816               WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
 817
 818 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(8|16)$")>;
 819 def : InstRW<[M1WriteVSTH,
 820               WriteAdr],      (instregex "ST4i(8|16)_POST$")>;
 821 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(32)$")>;
 822 def : InstRW<[M1WriteVSTH,
 823               WriteAdr],      (instregex "ST4i(32)_POST$")>;
 824 def : InstRW<[M1WriteVSTF],   (instregex "ST4i(64)$")>;
 825 def : InstRW<[M1WriteVSTF,
 826               WriteAdr],      (instregex "ST4i(64)_POST$")>;
 827
 828 def : InstRW<[M1WriteVSTF],   (instregex "ST4Fourv(8b|4h|2s)$")>;
 829 def : InstRW<[M1WriteVSTF,
 830               WriteAdr],      (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 831 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(16b|8h|4s)$")>;
 832 def : InstRW<[M1WriteVSTI,
 833               WriteAdr],      (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
 834 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(2d)$")>;
 835 def : InstRW<[M1WriteVSTI,
 836               WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
 837
 838 // Cryptography instructions.
 839 def : InstRW<[M1WriteAES], (instregex "^AES[DE]")>;
 840 def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AESI?MC")>;
 841
 842 def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
 843 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
 844 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;
 845 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>;
 846 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>;
 847
 848 // CRC instructions.
 849 def : InstRW<[M1WriteC2], (instregex "^CRC32")>;
 850
 851 } // SchedModel = ExynosM1Model