contrib/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

   1 //=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for the Samsung Exynos M3 to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide
  17 // in-order stage for decode and dispatch and a wider issue stage.
  18 // The execution units and loads and stores are out-of-order.
  19
  20 def ExynosM3Model : SchedMachineModel {
  21   let IssueWidth            =   6; // Up to 6 uops per cycle.
  22   let MicroOpBufferSize     = 228; // ROB size.
  23   let LoopMicroOpBufferSize =  40; // Based on the instruction queue size.
  24   let LoadLatency           =   4; // Optimistic load cases.
  25   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  26   let CompleteModel         =   1; // Use the default model otherwise.
  27
  28   list<Predicate> UnsupportedFeatures = [HasSVE];
  29 }
  30
  31 //===----------------------------------------------------------------------===//
  32 // Define each kind of processor resource and number available on the Exynos-M3,
  33 // which has 12 pipelines, each with its own queue with out-of-order dispatch.
  34
  35 let SchedModel = ExynosM3Model in {
  36
  37 def M3UnitA  : ProcResource<2>; // Simple integer
  38 def M3UnitC  : ProcResource<2>; // Simple and complex integer
  39 def M3UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  40 def M3UnitB  : ProcResource<2>; // Branch
  41 def M3UnitL  : ProcResource<2>; // Load
  42 def M3UnitS  : ProcResource<1>; // Store
  43 def M3PipeF0 : ProcResource<1>; // FP #0
  44 let Super = M3PipeF0 in {
  45   def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
  46   def M3UnitFADD0 : ProcResource<1>; // Simple FP
  47   def M3UnitFCVT0 : ProcResource<1>; // FP conversion
  48   def M3UnitFSQR  : ProcResource<2>; // FP square root (serialized)
  49   def M3UnitNALU0 : ProcResource<1>; // Simple vector
  50   def M3UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  51   def M3UnitNSHT0 : ProcResource<1>; // Vector shifting
  52   def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling
  53 }
  54 def M3PipeF1 : ProcResource<1>; // FP #1
  55 let Super = M3PipeF1 in {
  56   def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
  57   def M3UnitFADD1 : ProcResource<1>; // Simple FP
  58   def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  59   def M3UnitFCVT1 : ProcResource<1>; // FP conversion
  60   def M3UnitFST0  : ProcResource<1>; // FP store
  61   def M3UnitNALU1 : ProcResource<1>; // Simple vector
  62   def M3UnitNCRY0 : ProcResource<1>; // Cryptographic
  63   def M3UnitNMUL  : ProcResource<1>; // Vector multiplication
  64   def M3UnitNSHT1 : ProcResource<1>; // Vector shifting
  65   def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling
  66 }
  67 def M3PipeF2 : ProcResource<1>; // FP #2
  68 let Super = M3PipeF2 in {
  69   def M3UnitFMAC2 : ProcResource<1>; // FP multiplication
  70   def M3UnitFADD2 : ProcResource<1>; // Simple FP
  71   def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  72   def M3UnitFST1  : ProcResource<1>; // FP store
  73   def M3UnitNALU2 : ProcResource<1>; // Simple vector
  74   def M3UnitNCRY1 : ProcResource<1>; // Cryptographic
  75   def M3UnitNSHT2 : ProcResource<1>; // Vector shifting
  76   def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
  77 }
  78
  79
  80 def M3UnitALU  : ProcResGroup<[M3UnitA,
  81                                M3UnitC]>;
  82 def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
  83                                M3UnitFMAC1,
  84                                M3UnitFMAC2]>;
  85 def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
  86                                M3UnitFADD1,
  87                                M3UnitFADD2]>;
  88 def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
  89                                M3UnitFDIV1]>;
  90 def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
  91                                M3UnitFCVT1]>;
  92 def M3UnitFST  : ProcResGroup<[M3UnitFST0,
  93                                M3UnitFST1]>;
  94 def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
  95                                M3UnitNALU1,
  96                                M3UnitNALU2]>;
  97 def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
  98                                M3UnitNCRY1]>;
  99 def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
 100                                M3UnitNSHT1,
 101                                M3UnitNSHT2]>;
 102 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
 103                                M3UnitNSHF1,
 104                                M3UnitNSHF2]>;
 105
 106 //===----------------------------------------------------------------------===//
 107 // Coarse scheduling model.
 108
 109 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
 110                                     let NumMicroOps = 1; }
 111 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 112                                     let NumMicroOps = 0; }
 113
 114 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
 115 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
 116                                              let ResourceCycles = [2]; }
 117 def M3WriteAB : SchedWriteRes<[M3UnitALU,
 118                                M3UnitC]>   { let Latency = 1;
 119                                              let NumMicroOps = 2; }
 120 def M3WriteAC : SchedWriteRes<[M3UnitALU,
 121                                M3UnitALU,
 122                                M3UnitC]>   { let Latency = 2;
 123                                              let NumMicroOps = 3; }
 124 def M3WriteAD : SchedWriteRes<[M3UnitALU,
 125                                M3UnitC]>   { let Latency = 2;
 126                                              let NumMicroOps = 2; }
 127 def M3WriteC1 : SchedWriteRes<[M3UnitC]>   { let Latency = 1; }
 128 def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
 129 def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 130                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
 131                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 132                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 133 def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 134                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 135 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
 136                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 137 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
 138                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 139                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 140 def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
 141                                    SchedVar<NoSchedPred,              [M3WriteAA]>]>;
 142
 143 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 144 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
 145                                    SchedVar<NoSchedPred,            [M3WriteAB]>]>;
 146
 147 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
 148 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
 149 def M3WriteLA : SchedWriteRes<[M3UnitL,
 150                                M3UnitL]> { let Latency = 5;
 151                                            let NumMicroOps = 1; }
 152 def M3WriteLB : SchedWriteRes<[M3UnitA,
 153                                M3UnitL]> { let Latency = 5;
 154                                            let NumMicroOps = 2; }
 155 def M3WriteLC : SchedWriteRes<[M3UnitA,
 156                                M3UnitL,
 157                                M3UnitL]> { let Latency = 5;
 158                                            let NumMicroOps = 2; }
 159 def M3WriteLD : SchedWriteRes<[M3UnitA,
 160                                M3UnitL]> { let Latency = 4;
 161                                            let NumMicroOps = 2; }
 162 def M3WriteLE : SchedWriteRes<[M3UnitA,
 163                                M3UnitL]> { let Latency = 6;
 164                                            let NumMicroOps = 2; }
 165 def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 166                                            let NumMicroOps = 0; }
 167 def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
 168                                    SchedVar<NoSchedPred,         [M3WriteL4]>]>;
 169
 170 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 171 def M3WriteSA : SchedWriteRes<[M3UnitA,
 172                                M3UnitS,
 173                                M3UnitFST]> { let Latency = 3;
 174                                              let NumMicroOps = 2; }
 175 def M3WriteSB : SchedWriteRes<[M3UnitA,
 176                                M3UnitS]>   { let Latency = 2;
 177                                              let NumMicroOps = 2; }
 178
 179 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
 180                                       SchedVar<NoSchedPred,         [ReadDefault]>]>;
 181
 182 // Branch instructions.
 183 def : SchedAlias<WriteBr, M3WriteZ0>;
 184 def : SchedAlias<WriteBrReg, M3WriteC1>;
 185
 186 // Arithmetic and logical integer instructions.
 187 def : SchedAlias<WriteI,     M3WriteA1>;
 188 def : SchedAlias<WriteISReg, M3WriteA1>;
 189 def : SchedAlias<WriteIEReg, M3WriteA1>;
 190 def : SchedAlias<WriteIS,    M3WriteA1>;
 191
 192 // Move instructions.
 193 def : SchedAlias<WriteImm, M3WriteA1>;
 194
 195 // Divide and multiply instructions.
 196 def : WriteRes<WriteID32, [M3UnitC,
 197                            M3UnitD]>  { let Latency = 12;
 198                                         let ResourceCycles = [1, 12]; }
 199 def : WriteRes<WriteID64, [M3UnitC,
 200                            M3UnitD]>  { let Latency = 21;
 201                                         let ResourceCycles = [1, 21]; }
 202 def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
 203 def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
 204                                         let ResourceCycles = [2]; }
 205
 206 // Miscellaneous instructions.
 207 def : SchedAlias<WriteExtr, M3WriteAY>;
 208
 209 // Addressing modes.
 210 def : SchedAlias<WriteAdr,    M3WriteZ1>;
 211 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
 212
 213 // Load instructions.
 214 def : SchedAlias<WriteLD, M3WriteL4>;
 215 def : WriteRes<WriteLDHi, []> { let Latency = 4;
 216                                 let NumMicroOps = 0; }
 217 def : SchedAlias<WriteLDIdx, M3WriteLB>;
 218
 219 // Store instructions.
 220 def : SchedAlias<WriteST,    M3WriteS1>;
 221 def : SchedAlias<WriteSTP,   M3WriteS1>;
 222 def : SchedAlias<WriteSTX,   M3WriteS1>;
 223 def : SchedAlias<WriteSTIdx, M3WriteSB>;
 224
 225 // FP data instructions.
 226 def : WriteRes<WriteF,    [M3UnitFADD]>  { let Latency = 2; }
 227 def : WriteRes<WriteFCmp, [M3UnitNMSC]>  { let Latency = 2; }
 228 def : WriteRes<WriteFDiv, [M3UnitFDIV]>  { let Latency = 12;
 229                                            let ResourceCycles = [12]; }
 230 def : WriteRes<WriteFMul, [M3UnitFMAC]>  { let Latency = 4; }
 231
 232 // FP miscellaneous instructions.
 233 def : WriteRes<WriteFCvt,  [M3UnitFCVT]> { let Latency = 3; }
 234 def : WriteRes<WriteFImm,  [M3UnitNALU]> { let Latency = 1; }
 235 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
 236
 237 // FP load instructions.
 238 def : SchedAlias<WriteVLD, M3WriteL5>;
 239
 240 // FP store instructions.
 241 def : WriteRes<WriteVST, [M3UnitS,
 242                           M3UnitFST]> { let Latency = 1;
 243                                         let NumMicroOps = 1; }
 244
 245 // ASIMD FP instructions.
 246 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
 247
 248 // Other miscellaneous instructions.
 249 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 250 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 251 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 252 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 253
 254 //===----------------------------------------------------------------------===//
 255 // Generic fast forwarding.
 256
 257 // TODO: Add FP register forwarding rules.
 258
 259 def : ReadAdvance<ReadI,       0>;
 260 def : ReadAdvance<ReadISReg,   0>;
 261 def : ReadAdvance<ReadIEReg,   0>;
 262 def : ReadAdvance<ReadIM,      0>;
 263 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 264 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 265 def : ReadAdvance<ReadID,      0>;
 266 def : ReadAdvance<ReadExtrHi,  0>;
 267 def : ReadAdvance<ReadAdrBase, 0>;
 268 def : ReadAdvance<ReadVLD,     0>;
 269
 270 //===----------------------------------------------------------------------===//
 271 // Finer scheduling model.
 272
 273 def M3WriteNEONA   : SchedWriteRes<[M3UnitNSHF,
 274                                     M3UnitFADD]>  { let Latency = 3;
 275                                                     let NumMicroOps = 2; }
 276 def M3WriteNEONB   : SchedWriteRes<[M3UnitNALU,
 277                                     M3UnitFST]>   { let Latency = 10;
 278                                                     let NumMicroOps = 2; }
 279 def M3WriteNEOND   : SchedWriteRes<[M3UnitNSHF,
 280                                     M3UnitFST]>   { let Latency = 6;
 281                                                     let NumMicroOps = 2; }
 282 def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
 283                                     M3UnitS]>     { let Latency = 5;
 284                                                     let NumMicroOps = 2; }
 285 def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
 286                                     M3UnitS]>     { let Latency = 5;
 287                                                     let NumMicroOps = 2; }
 288 def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV0,
 289                                     M3UnitFDIV1]>  { let Latency = 7;
 290                                                      let NumMicroOps = 2;
 291                                                      let ResourceCycles = [8, 8]; }
 292 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV0,
 293                                     M3UnitFDIV1]>  { let Latency = 12;
 294                                                      let NumMicroOps = 2;
 295                                                      let ResourceCycles = [13, 13]; }
 296 def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
 297                                     M3UnitFSQR]>  { let Latency = 18;
 298                                                     let NumMicroOps = 2;
 299                                                     let ResourceCycles = [19, 19]; }
 300 def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
 301                                     M3UnitFSQR]>  { let Latency = 25;
 302                                                     let NumMicroOps = 2;
 303                                                     let ResourceCycles = [26, 26]; }
 304 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
 305                                     M3UnitNMSC]>  { let Latency = 5;
 306                                                     let NumMicroOps = 2; }
 307 def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
 308 def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
 309 def M3WriteFCVT3   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 3; }
 310 def M3WriteFCVT3A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
 311 def M3WriteFCVT4A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
 312 def M3WriteFCVT4   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 4; }
 313 def M3WriteFDIV10  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 7;
 314                                                     let ResourceCycles = [8]; }
 315 def M3WriteFDIV12  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 12;
 316                                                     let ResourceCycles = [13]; }
 317 def M3WriteFMAC3   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 3; }
 318 def M3WriteFMAC4   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 4; }
 319 def M3WriteFMAC5   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 5; }
 320 def M3WriteFSQR17  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 18;
 321                                                     let ResourceCycles = [19]; }
 322 def M3WriteFSQR25  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 25;
 323                                                     let ResourceCycles = [26]; }
 324 def M3WriteNALU1   : SchedWriteRes<[M3UnitNALU]>  { let Latency = 1; }
 325 def M3WriteNCRY1A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
 326 def M3WriteNCRY3A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
 327 def M3WriteNCRY5A  : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 5; }
 328 def M3WriteNMSC1   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 1; }
 329 def M3WriteNMSC2   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 2; }
 330 def M3WriteNMSC3   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 3; }
 331 def M3WriteNMUL3   : SchedWriteRes<[M3UnitNMUL]>  { let Latency = 3; }
 332 def M3WriteNSHF1   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 1; }
 333 def M3WriteNSHF3   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 3; }
 334 def M3WriteNSHT1   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 1; }
 335 def M3WriteNSHT2   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 2; }
 336 def M3WriteNSHT3   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 3; }
 337 def M3WriteVLDA    : SchedWriteRes<[M3UnitL,
 338                                     M3UnitL]>     { let Latency = 5;
 339                                                     let NumMicroOps = 2; }
 340 def M3WriteVLDB    : SchedWriteRes<[M3UnitL,
 341                                     M3UnitL,
 342                                     M3UnitL]>     { let Latency = 6;
 343                                                     let NumMicroOps = 3; }
 344 def M3WriteVLDC    : SchedWriteRes<[M3UnitL,
 345                                     M3UnitL,
 346                                     M3UnitL,
 347                                     M3UnitL]>     { let Latency = 6;
 348                                                     let NumMicroOps = 4; }
 349 def M3WriteVLDD    : SchedWriteRes<[M3UnitL,
 350                                     M3UnitNALU]>  { let Latency = 7;
 351                                                     let NumMicroOps = 2;
 352                                                     let ResourceCycles = [2, 1]; }
 353 def M3WriteVLDE    : SchedWriteRes<[M3UnitL,
 354                                     M3UnitNALU]>  { let Latency = 6;
 355                                                     let NumMicroOps = 2;
 356                                                     let ResourceCycles = [2, 1]; }
 357 def M3WriteVLDF    : SchedWriteRes<[M3UnitL,
 358                                     M3UnitL]>     { let Latency = 10;
 359                                                     let NumMicroOps = 2;
 360                                                     let ResourceCycles = [5, 5]; }
 361 def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
 362                                     M3UnitNALU,
 363                                     M3UnitNALU]>  { let Latency = 7;
 364                                                     let NumMicroOps = 3;
 365                                                     let ResourceCycles = [2, 1, 1]; }
 366 def M3WriteVLDH    : SchedWriteRes<[M3UnitL,
 367                                     M3UnitNALU,
 368                                     M3UnitNALU]>  { let Latency = 6;
 369                                                     let NumMicroOps = 3;
 370                                                     let ResourceCycles = [2, 1, 1]; }
 371 def M3WriteVLDI    : SchedWriteRes<[M3UnitL,
 372                                     M3UnitL,
 373                                     M3UnitL]>     { let Latency = 12;
 374                                                     let NumMicroOps = 3;
 375                                                     let ResourceCycles = [6, 6, 6]; }
 376 def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
 377                                     M3UnitNALU,
 378                                     M3UnitNALU,
 379                                     M3UnitNALU]>  { let Latency = 7;
 380                                                     let NumMicroOps = 4;
 381                                                     let ResourceCycles = [2, 1, 1, 1]; }
 382 def M3WriteVLDK    : SchedWriteRes<[M3UnitL,
 383                                     M3UnitNALU,
 384                                     M3UnitNALU,
 385                                     M3UnitNALU,
 386                                     M3UnitNALU]>  { let Latency = 9;
 387                                                     let NumMicroOps = 5;
 388                                                     let ResourceCycles = [4, 1, 1, 1, 1]; }
 389 def M3WriteVLDL    : SchedWriteRes<[M3UnitL,
 390                                     M3UnitNALU,
 391                                     M3UnitNALU,
 392                                     M3UnitL,
 393                                     M3UnitNALU]>  { let Latency = 6;
 394                                                     let NumMicroOps = 5;
 395                                                     let ResourceCycles = [6, 1, 1, 6, 1]; }
 396 def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
 397                                     M3UnitNALU,
 398                                     M3UnitNALU,
 399                                     M3UnitL,
 400                                     M3UnitNALU,
 401                                     M3UnitNALU]>  { let Latency = 7;
 402                                                     let NumMicroOps = 6;
 403                                                     let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
 404 def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
 405                                     M3UnitL,
 406                                     M3UnitL,
 407                                     M3UnitL]>     { let Latency = 14;
 408                                                     let NumMicroOps = 4;
 409                                                     let ResourceCycles = [6, 6, 6, 6]; }
 410 def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
 411 def M3WriteVSTB    : WriteSequence<[WriteVST], 3>;
 412 def M3WriteVSTC    : WriteSequence<[WriteVST], 4>;
 413 def M3WriteVSTD    : SchedWriteRes<[M3UnitS,
 414                                     M3UnitFST,
 415                                     M3UnitS,
 416                                     M3UnitFST]>   { let Latency = 7;
 417                                                     let NumMicroOps = 4;
 418                                                     let ResourceCycles = [1, 3, 1, 3]; }
 419 def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
 420                                     M3UnitFST,
 421                                     M3UnitS,
 422                                     M3UnitFST,
 423                                     M3UnitS,
 424                                     M3UnitFST]>   { let Latency = 8;
 425                                                     let NumMicroOps = 6;
 426                                                     let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
 427 def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
 428                                     M3UnitFST,
 429                                     M3UnitFST,
 430                                     M3UnitS,
 431                                     M3UnitFST,
 432                                     M3UnitS,
 433                                     M3UnitFST]>   { let Latency = 15;
 434                                                     let NumMicroOps = 7;
 435                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
 436 def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
 437                                     M3UnitFST,
 438                                     M3UnitFST,
 439                                     M3UnitS,
 440                                     M3UnitFST,
 441                                     M3UnitS,
 442                                     M3UnitFST,
 443                                     M3UnitS,
 444                                     M3UnitFST]>   { let Latency = 16;
 445                                                     let NumMicroOps = 9;
 446                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 447 def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
 448                                     M3UnitFST,
 449                                     M3UnitFST,
 450                                     M3UnitS,
 451                                     M3UnitFST]>   { let Latency = 14;
 452                                                     let NumMicroOps = 5;
 453                                                     let ResourceCycles = [1, 3, 3, 1, 3]; }
 454 def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
 455                                     M3UnitFST,
 456                                     M3UnitFST,
 457                                     M3UnitS,
 458                                     M3UnitFST,
 459                                     M3UnitS,
 460                                     M3UnitFST,
 461                                     M3UnitS,
 462                                     M3UnitFST]>   { let Latency = 17;
 463                                                     let NumMicroOps = 9;
 464                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 465
 466 // Special cases.
 467 def M3WriteAES     : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 1; }
 468 def M3WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
 469                                         SchedVar<NoSchedPred,  [M3WriteZ0]>]>;
 470 def M3WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
 471                                         SchedVar<NoSchedPred,       [M3WriteNALU1]>]>;
 472
 473 // Fast forwarding.
 474 def M3ReadAES      : SchedReadAdvance<1, [M3WriteAES]>;
 475 def M3ReadFMAC     : SchedReadAdvance<1, [M3WriteFMAC4,
 476                                           M3WriteFMAC5]>;
 477 def M3ReadNMUL     : SchedReadAdvance<1, [M3WriteNMUL3]>;
 478
 479 // Branch instructions
 480 def : InstRW<[M3WriteB1], (instrs Bcc)>;
 481 def : InstRW<[M3WriteA1], (instrs BL)>;
 482 def : InstRW<[M3WriteBX], (instrs BLR)>;
 483 def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
 484 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
 485
 486 // Arithmetic and logical integer instructions.
 487 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 488 def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
 489 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 490 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 491 def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
 492 def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
 493
 494 // Move instructions.
 495 def : InstRW<[M3WriteCOPY], (instrs COPY)>;
 496 def : InstRW<[M3WriteZ0],   (instrs ADR, ADRP)>;
 497 def : InstRW<[M3WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 498
 499 // Divide and multiply instructions.
 500
 501 // Miscellaneous instructions.
 502
 503 // Load instructions.
 504 def : InstRW<[M3WriteLD,
 505               WriteLDHi,
 506               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 507 def : InstRW<[M3WriteLB,
 508               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 509 def : InstRW<[M3WriteLX,
 510               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 511 def : InstRW<[M3WriteLB,
 512               ReadAdrBase], (instrs PRFMroW)>;
 513 def : InstRW<[M3WriteLX,
 514               ReadAdrBase], (instrs PRFMroX)>;
 515
 516 // Store instructions.
 517 def : InstRW<[M3WriteSB,
 518               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 519 def : InstRW<[WriteST,
 520               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 521
 522 // FP data instructions.
 523 def : InstRW<[M3WriteNSHF1],  (instregex "^FABS[DS]r")>;
 524 def : InstRW<[M3WriteFADD2],  (instregex "^F(ADD|SUB)[DS]rr")>;
 525 def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>;
 526 def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>;
 527 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN).+rr")>;
 528 def : InstRW<[M3WriteFMAC3],  (instregex "^FN?MUL[DS]rr")>;
 529 def : InstRW<[M3WriteFMAC4,
 530               M3ReadFMAC],    (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 531 def : InstRW<[M3WriteNALU1],  (instregex "^FNEG[DS]r")>;
 532 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
 533 def : InstRW<[M3WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 534 def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>;
 535 def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>;
 536
 537 // FP miscellaneous instructions.
 538 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT[DHS][DHS]r")>;
 539 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
 540 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
 541 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>;
 542 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 543 def : InstRW<[M3WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 544 def : InstRW<[M3WriteNMSC1],  (instregex "^FRECPXv1")>;
 545 def : InstRW<[M3WriteFMAC4,
 546               M3ReadFMAC],    (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 547 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS]r")>;
 548 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX]r")>;
 549 def : InstRW<[M3WriteNEONI],  (instregex "^FMOV(DX|XD)Highr")>;
 550
 551 // FP load instructions.
 552 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 553 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 554 def : InstRW<[WriteVLD,
 555               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 556 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 557 def : InstRW<[M3WriteLE,
 558               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 559 def : InstRW<[WriteVLD,
 560               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
 561 def : InstRW<[M3WriteLE,
 562               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 563 def : InstRW<[WriteVLD,
 564               M3WriteLH],   (instregex "^LDN?P[DS]i")>;
 565 def : InstRW<[M3WriteLA,
 566               M3WriteLH],   (instregex "^LDN?PQi")>;
 567 def : InstRW<[M3WriteLB,
 568               M3WriteLH,
 569               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 570 def : InstRW<[M3WriteLC,
 571               M3WriteLH,
 572               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 573
 574 // FP store instructions.
 575 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 576 def : InstRW<[WriteVST,
 577               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 578 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 579 def : InstRW<[M3WriteSA,
 580               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
 581 def : InstRW<[WriteVST,
 582               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
 583 def : InstRW<[M3WriteSA,
 584               ReadAdrBase], (instregex "^STRQro[WX]")>;
 585 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 586 def : InstRW<[WriteVST,
 587               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 588 def : InstRW<[M3WriteSA,
 589               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 590
 591 // ASIMD instructions.
 592 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>;
 593 def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>;
 594 def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>;
 595 def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
 596 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
 597 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>;
 598 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>;
 599 def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>;
 600 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>;
 601 def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>;
 602 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>;
 603 def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 604 def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>;
 605 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 606 def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
 607 def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
 608 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
 609 def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>;
 610 def : InstRW<[M3WriteNMUL3,
 611               M3ReadNMUL],   (instregex "^ML[AS]v")>;
 612 def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>;
 613 def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>;
 614 def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>;
 615 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>;
 616 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>;
 617 def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>;
 618 def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
 619 def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>;
 620 def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>;
 621 def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 622 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>;
 623 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 624
 625 // ASIMD FP instructions.
 626 def : InstRW<[M3WriteNSHF1],  (instregex "^FABSv")>;
 627 def : InstRW<[M3WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v")>;
 628 def : InstRW<[M3WriteNEONA],  (instregex "^FADDP")>;
 629 def : InstRW<[M3WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 630 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT(L|N|XN)v")>;
 631 def : InstRW<[M3WriteFCVT2],  (instregex "^FCVT[AMNPZ][SU]v")>;
 632 def : InstRW<[M3WriteFCVT2],  (instregex "^[SU]CVTFv")>;
 633 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
 634 def : InstRW<[M3WriteNEONV],  (instrs FDIVv4f32)>;
 635 def : InstRW<[M3WriteNEONW],  (instrs FDIVv2f64)>;
 636 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 637 def : InstRW<[M3WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 638 def : InstRW<[M3WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 639 def : InstRW<[M3WriteFMAC3],  (instregex "^FMULX?v.[fi]")>;
 640 def : InstRW<[M3WriteFMAC4,
 641               M3ReadFMAC],    (instregex "^FML[AS]v.f")>;
 642 def : InstRW<[M3WriteFMAC5,
 643               M3ReadFMAC],    (instregex "^FML[AS]v.i")>;
 644 def : InstRW<[M3WriteNALU1],  (instregex "^FNEGv")>;
 645 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 646 def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>;
 647 def : InstRW<[M3WriteNEONX],  (instrs FSQRTv4f32)>;
 648 def : InstRW<[M3WriteNEONY],  (instrs FSQRTv2f64)>;
 649
 650 // ASIMD miscellaneous instructions.
 651 def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
 652 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>;
 653 def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
 654 def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
 655 def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
 656 def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
 657 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
 658 def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
 659 def : InstRW<[M3WriteMOVI],  (instregex "^MOVI")>;
 660 def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
 661 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 662 def : InstRW<[M3WriteFMAC4,
 663               M3ReadFMAC],   (instregex "^F(RECP|RSQRT)Sv")>;
 664 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
 665 def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
 666 def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>;
 667 def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>;
 668 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
 669
 670 // ASIMD load instructions.
 671 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 672 def : InstRW<[M3WriteL5,
 673               M3WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST")>;
 674 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 675 def : InstRW<[M3WriteL5,
 676               M3WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST")>;
 677
 678 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 679 def : InstRW<[M3WriteVLDA,
 680               M3WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
 681 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 682 def : InstRW<[M3WriteVLDA,
 683               M3WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
 684
 685 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 686 def : InstRW<[M3WriteVLDB,
 687               M3WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
 688 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 689 def : InstRW<[M3WriteVLDB,
 690               M3WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
 691
 692 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 693 def : InstRW<[M3WriteVLDC,
 694               M3WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
 695 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 696 def : InstRW<[M3WriteVLDC,
 697               M3WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
 698
 699 def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>;
 700 def : InstRW<[M3WriteVLDD,
 701               M3WriteA1],   (instregex "LD1i(8|16|32)_POST")>;
 702 def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>;
 703 def : InstRW<[M3WriteVLDE,
 704               M3WriteA1],   (instregex "LD1i(64)_POST")>;
 705
 706 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 707 def : InstRW<[M3WriteL5,
 708               M3WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST")>;
 709 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 710 def : InstRW<[M3WriteL5,
 711               M3WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST")>;
 712
 713 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 714 def : InstRW<[M3WriteVLDF,
 715               M3WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST")>;
 716 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 717 def : InstRW<[M3WriteVLDF,
 718               M3WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
 719
 720 def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>;
 721 def : InstRW<[M3WriteVLDG,
 722               M3WriteA1],   (instregex "LD2i(8|16|32)_POST")>;
 723 def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>;
 724 def : InstRW<[M3WriteVLDH,
 725               M3WriteA1],   (instregex "LD2i(64)_POST")>;
 726
 727 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 728 def : InstRW<[M3WriteVLDA,
 729               M3WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST")>;
 730 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 731 def : InstRW<[M3WriteVLDA,
 732               M3WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST")>;
 733
 734 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 735 def : InstRW<[M3WriteVLDI,
 736               M3WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST")>;
 737 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 738 def : InstRW<[M3WriteVLDI,
 739               M3WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
 740
 741 def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 742 def : InstRW<[M3WriteVLDJ,
 743               M3WriteA1],   (instregex "LD3i(8|16|32)_POST")>;
 744 def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>;
 745 def : InstRW<[M3WriteVLDL,
 746               M3WriteA1],   (instregex "LD3i(64)_POST")>;
 747
 748 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 749 def : InstRW<[M3WriteVLDB,
 750               M3WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST")>;
 751 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 752 def : InstRW<[M3WriteVLDB,
 753               M3WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST")>;
 754
 755 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 756 def : InstRW<[M3WriteVLDN,
 757               M3WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST")>;
 758 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 759 def : InstRW<[M3WriteVLDN,
 760               M3WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
 761
 762 def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 763 def : InstRW<[M3WriteVLDK,
 764               M3WriteA1],   (instregex "LD4i(8|16|32)_POST")>;
 765 def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>;
 766 def : InstRW<[M3WriteVLDM,
 767               M3WriteA1],   (instregex "LD4i(64)_POST")>;
 768
 769 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 770 def : InstRW<[M3WriteVLDC,
 771               M3WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST")>;
 772 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 773 def : InstRW<[M3WriteVLDC,
 774               M3WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST")>;
 775
 776 // ASIMD store instructions.
 777 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 778 def : InstRW<[WriteVST,
 779               WriteAdr],    (instregex "ST1Onev(8b|4h|2s|1d)_POST")>;
 780 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 781 def : InstRW<[WriteVST,
 782               WriteAdr],    (instregex "ST1Onev(16b|8h|4s|2d)_POST")>;
 783
 784 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 785 def : InstRW<[M3WriteVSTA,
 786               WriteAdr],    (instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
 787 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 788 def : InstRW<[M3WriteVSTA,
 789               WriteAdr],    (instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
 790
 791 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 792 def : InstRW<[M3WriteVSTB,
 793               WriteAdr],    (instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
 794 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 795 def : InstRW<[M3WriteVSTB,
 796               WriteAdr],    (instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
 797
 798 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 799 def : InstRW<[M3WriteVSTC,
 800               WriteAdr],    (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
 801 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 802 def : InstRW<[M3WriteVSTC,
 803               WriteAdr],    (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
 804
 805 def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>;
 806 def : InstRW<[M3WriteVSTD,
 807               WriteAdr],    (instregex "ST1i(8|16|32|64)_POST")>;
 808
 809 def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 810 def : InstRW<[M3WriteVSTD,
 811               WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST")>;
 812 def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 813 def : InstRW<[M3WriteVSTE,
 814               WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
 815
 816 def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>;
 817 def : InstRW<[M3WriteVSTD,
 818               WriteAdr],    (instregex "ST2i(8|16|32)_POST")>;
 819 def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>;
 820 def : InstRW<[M3WriteVSTD,
 821               WriteAdr],    (instregex "ST2i(64)_POST")>;
 822
 823 def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 824 def : InstRW<[M3WriteVSTF,
 825               WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST")>;
 826 def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 827 def : InstRW<[M3WriteVSTG,
 828               WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
 829
 830 def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>;
 831 def : InstRW<[M3WriteVSTH,
 832               WriteAdr],    (instregex "ST3i(8|16|32)_POST")>;
 833 def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>;
 834 def : InstRW<[M3WriteVSTF,
 835               WriteAdr],    (instregex "ST3i(64)_POST")>;
 836
 837 def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
 838 def : InstRW<[M3WriteVSTF,
 839               WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST")>;
 840 def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 841 def : InstRW<[M3WriteVSTI,
 842               WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
 843
 844 def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>;
 845 def : InstRW<[M3WriteVSTF,
 846               WriteAdr],    (instregex "ST4i(8|16|32|64)_POST")>;
 847
 848 // Cryptography instructions.
 849 def : InstRW<[M3WriteAES],    (instregex "^AES[DE]")>;
 850 def : InstRW<[M3WriteAES,
 851               M3ReadAES],     (instregex "^AESI?MC")>;
 852
 853 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
 854
 855 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
 856 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>;
 857 def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>;
 858
 859 // CRC instructions.
 860 def : InstRW<[M3WriteC2], (instregex "^CRC32")>;
 861
 862 } // SchedModel = ExynosM3Model