1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for the Samsung Exynos M4 to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide
17 // in-order stage for decode and dispatch and a wider issue stage.
18 // The execution units and loads and stores are out-of-order.
20 def ExynosM4Model : SchedMachineModel {
21 let IssueWidth = 6; // Up to 6 uops per cycle.
22 let MicroOpBufferSize = 228; // ROB size.
23 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size.
24 let LoadLatency = 4; // Optimistic load cases.
25 let MispredictPenalty = 16; // Minimum branch misprediction penalty.
26 let CompleteModel = 1; // Use the default model otherwise.
28 list<Predicate> UnsupportedFeatures = [HasSVE];
31 //===----------------------------------------------------------------------===//
32 // Define each kind of processor resource and number available on the Exynos-M4.
34 let SchedModel = ExynosM4Model in {
36 def M4UnitA : ProcResource<2>; // Simple integer
37 def M4UnitC : ProcResource<2>; // Simple and complex integer
38 let Super = M4UnitC, BufferSize = 1 in
39 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 let Super = M4UnitC in
41 def M4UnitE : ProcResource<1>; // CRC (inside C0)
42 def M4UnitB : ProcResource<2>; // Branch
43 def M4UnitL0 : ProcResource<1>; // Load
44 def M4UnitS0 : ProcResource<1>; // Store
45 def M4PipeLS : ProcResource<1>; // Load/Store
46 let Super = M4PipeLS in {
47 def M4UnitL1 : ProcResource<1>;
48 def M4UnitS1 : ProcResource<1>;
50 def M4PipeF0 : ProcResource<1>; // FP #0
51 let Super = M4PipeF0 in {
52 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication
53 def M4UnitFADD0 : ProcResource<1>; // Simple FP
54 def M4UnitFCVT0 : ProcResource<1>; // FP conversion
55 def M4UnitNALU0 : ProcResource<1>; // Simple vector
56 def M4UnitNHAD : ProcResource<1>; // Horizontal vector
57 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea
58 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication
59 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting
60 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling
61 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic
63 def M4PipeF1 : ProcResource<1>; // FP #1
64 let Super = M4PipeF1 in {
65 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication
66 def M4UnitFADD1 : ProcResource<1>; // Simple FP
67 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized)
68 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
69 def M4UnitFST0 : ProcResource<1>; // FP store
70 def M4UnitNALU1 : ProcResource<1>; // Simple vector
71 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting
72 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling
74 def M4PipeF2 : ProcResource<1>; // FP #2
75 let Super = M4PipeF2 in {
76 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication
77 def M4UnitFADD2 : ProcResource<1>; // Simple FP
78 def M4UnitFCVT1 : ProcResource<1>; // FP conversion
79 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized)
80 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
81 def M4UnitFST1 : ProcResource<1>; // FP store
82 def M4UnitNALU2 : ProcResource<1>; // Simple vector
83 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication
84 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting
85 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic
88 def M4UnitALU : ProcResGroup<[M4UnitA,
90 def M4UnitL : ProcResGroup<[M4UnitL0,
92 def M4UnitS : ProcResGroup<[M4UnitS0,
94 def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0,
97 def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0,
99 def M4UnitFADD : ProcResGroup<[M4UnitFADD0,
102 def M4UnitFADDH : ProcResGroup<[M4UnitFADD0,
104 def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0,
106 def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>;
107 def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0,
109 def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>;
110 def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0,
112 def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>;
113 def M4UnitFST : ProcResGroup<[M4UnitFST0,
115 def M4UnitNALU : ProcResGroup<[M4UnitNALU0,
118 def M4UnitNALUH : ProcResGroup<[M4UnitNALU0,
120 def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0,
122 def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0,
125 def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0,
127 def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>;
128 def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0,
131 //===----------------------------------------------------------------------===//
132 // Resources details.
134 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
135 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
136 let NumMicroOps = 0; }
137 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
138 let NumMicroOps = 0; }
140 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
141 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
142 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
143 let ResourceCycles = [2]; }
144 def M4WriteAB : SchedWriteRes<[M4UnitALU,
145 M4UnitC]> { let Latency = 2;
146 let NumMicroOps = 2; }
147 def M4WriteAC : SchedWriteRes<[M4UnitALU,
149 M4UnitC]> { let Latency = 3;
150 let NumMicroOps = 3; }
151 def M4WriteAD : SchedWriteRes<[M4UnitALU,
152 M4UnitC]> { let Latency = 2;
153 let NumMicroOps = 2; }
154 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
155 let NumMicroOps = 2; }
156 def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>,
157 SchedVar<ExynosArithPred, [M4WriteA1]>,
158 SchedVar<ExynosLogicExPred, [M4WriteA1]>,
159 SchedVar<NoSchedPred, [M4WriteAA]>]>;
160 def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>,
161 SchedVar<NoSchedPred, [M4WriteAA]>]>;
162 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>,
163 SchedVar<ExynosLogicExPred, [M4WriteA1]>,
164 SchedVar<NoSchedPred, [M4WriteAA]>]>;
165 def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
166 SchedVar<NoSchedPred, [M4WriteAF]>]>;
168 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
169 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
170 SchedVar<NoSchedPred, [M4WriteAB]>]>;
172 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
173 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
174 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
175 let ResourceCycles = [2]; }
177 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; }
178 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; }
180 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
182 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
183 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
184 def M4WriteLA : SchedWriteRes<[M4UnitL,
185 M4UnitL]> { let Latency = 5;
186 let NumMicroOps = 1; }
187 def M4WriteLB : SchedWriteRes<[M4UnitA,
188 M4UnitL]> { let Latency = 5;
189 let NumMicroOps = 2; }
190 def M4WriteLC : SchedWriteRes<[M4UnitA,
192 M4UnitL]> { let Latency = 5;
193 let NumMicroOps = 2; }
194 def M4WriteLD : SchedWriteRes<[M4UnitA,
195 M4UnitL]> { let Latency = 4;
196 let NumMicroOps = 2; }
197 def M4WriteLE : SchedWriteRes<[M4UnitA,
198 M4UnitL]> { let Latency = 6;
199 let NumMicroOps = 2; }
200 def M4WriteLH : SchedWriteRes<[]> { let Latency = 5;
201 let NumMicroOps = 0; }
202 def M4WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M4WriteL5]>,
203 SchedVar<NoSchedPred, [M4WriteL4]>]>;
205 def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; }
206 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
207 def M4WriteSB : SchedWriteRes<[M4UnitA,
208 M4UnitS]> { let Latency = 2;
209 let NumMicroOps = 1; }
210 def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>,
211 SchedVar<NoSchedPred, [M4WriteS1]>]>;
213 def M4ReadAdrBase : SchedReadVariant<[SchedVar<
217 ExynosScaledIdxFn]>>, [ReadDefault]>,
218 SchedVar<NoSchedPred, [ReadDefault]>]>;
220 def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF,
221 M4UnitFADD]> { let Latency = 3;
222 let NumMicroOps = 2; }
223 def M4WriteNEONB : SchedWriteRes<[M4UnitNALU,
224 M4UnitS0]> { let Latency = 5;
225 let NumMicroOps = 2; }
226 def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF,
227 M4UnitFST]> { let Latency = 6;
228 let NumMicroOps = 2; }
229 def M4WriteNEONH : SchedWriteRes<[M4UnitNALU,
230 M4UnitS0]> { let Latency = 5;
231 let NumMicroOps = 2; }
232 def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF,
233 M4UnitS0]> { let Latency = 2;
234 let NumMicroOps = 2; }
235 def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC,
236 M4UnitS0]> { let Latency = 4; }
237 def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF,
239 M4UnitS0]> { let Latency = 5;
240 let NumMicroOps = 2; }
241 def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
242 def M4WriteNEONM : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
243 def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC,
244 M4UnitNMSC]> { let Latency = 5;
245 let NumMicroOps = 2; }
246 def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC,
248 M4UnitNMSC]> { let Latency = 8;
249 let NumMicroOps = 3; }
250 def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF,
251 M4UnitNMSC]> { let Latency = 4;
252 let NumMicroOps = 2; }
253 def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC,
254 M4UnitC]> { let Latency = 3;
255 let NumMicroOps = 1; }
256 def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0,
257 M4UnitS0]> { let Latency = 4;
258 let NumMicroOps = 1; }
259 def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV,
260 M4UnitFDIV]> { let Latency = 7;
261 let ResourceCycles = [6, 6]; }
262 def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH,
263 M4UnitFDIVH]> { let Latency = 7;
264 let ResourceCycles = [6, 6]; }
265 def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV,
266 M4UnitFDIV]> { let Latency = 12;
267 let ResourceCycles = [9, 9]; }
268 def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR,
269 M4UnitFSQR]> { let Latency = 8;
270 let ResourceCycles = [7, 7]; }
271 def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH,
272 M4UnitFSQRH]> { let Latency = 7;
273 let ResourceCycles = [6, 6]; }
274 def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR,
275 M4UnitFSQR]> { let Latency = 12;
276 let ResourceCycles = [9, 9]; }
277 def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
278 SchedVar<NoSchedPred, [M4WriteNEONN]>]>;
280 def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; }
281 def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
283 def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; }
284 def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
285 def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
286 def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; }
287 def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
288 def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
289 def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; }
290 def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
291 def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
293 def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7;
294 let ResourceCycles = [6]; }
295 def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
296 let ResourceCycles = [6]; }
297 def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12;
298 let ResourceCycles = [9]; }
300 def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
301 def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
302 def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; }
303 def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; }
304 def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
305 def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; }
307 def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
308 let ResourceCycles = [6]; }
309 def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8;
310 let ResourceCycles = [7]; }
311 def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12;
312 let ResourceCycles = [9]; }
314 def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; }
315 def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
317 def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; }
318 def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
319 def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
320 def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; }
322 def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; }
323 def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; }
325 def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; }
326 def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; }
327 def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; }
329 def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
331 def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; }
332 def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
333 def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; }
334 def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1;
335 let ResourceCycles = [2]; }
336 def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2;
338 let ResourceCycles = [2]; }
339 def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3;
341 let ResourceCycles = [4]; }
342 def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4;
344 let ResourceCycles = [4]; }
346 def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; }
347 def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; }
348 def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; }
349 def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
351 def M4WriteVLDA : SchedWriteRes<[M4UnitL,
352 M4UnitL]> { let Latency = 5;
353 let NumMicroOps = 2; }
354 def M4WriteVLDB : SchedWriteRes<[M4UnitL,
356 M4UnitL]> { let Latency = 6;
357 let NumMicroOps = 3; }
358 def M4WriteVLDC : SchedWriteRes<[M4UnitL,
361 M4UnitL]> { let Latency = 6;
362 let NumMicroOps = 4; }
363 def M4WriteVLDD : SchedWriteRes<[M4UnitL,
364 M4UnitNSHF]> { let Latency = 6;
366 let ResourceCycles = [2, 1]; }
367 def M4WriteVLDF : SchedWriteRes<[M4UnitL,
368 M4UnitL]> { let Latency = 10;
370 let ResourceCycles = [3, 3]; }
371 def M4WriteVLDG : SchedWriteRes<[M4UnitL,
373 M4UnitNSHF]> { let Latency = 6;
375 let ResourceCycles = [2, 1, 1]; }
376 def M4WriteVLDI : SchedWriteRes<[M4UnitL,
378 M4UnitL]> { let Latency = 12;
380 let ResourceCycles = [3, 3, 3]; }
381 def M4WriteVLDJ : SchedWriteRes<[M4UnitL,
384 M4UnitNSHF]> { let Latency = 7;
386 let ResourceCycles = [3, 1, 1, 1]; }
387 def M4WriteVLDK : SchedWriteRes<[M4UnitL,
391 M4UnitNSHF]> { let Latency = 7;
393 let ResourceCycles = [3, 1, 1, 1, 1]; }
394 def M4WriteVLDL : SchedWriteRes<[M4UnitL,
398 M4UnitNSHF]> { let Latency = 7;
400 let ResourceCycles = [3, 1, 1, 6, 1]; }
401 def M4WriteVLDM : SchedWriteRes<[M4UnitL,
406 M4UnitNSHF]> { let Latency = 7;
408 let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
409 def M4WriteVLDN : SchedWriteRes<[M4UnitL,
412 M4UnitL]> { let Latency = 14;
414 let ResourceCycles = [3, 3, 3, 3]; }
416 def M4WriteVST1 : SchedWriteRes<[M4UnitS,
417 M4UnitFST]> { let Latency = 1;
418 let NumMicroOps = 1; }
419 def M4WriteVSTA : WriteSequence<[WriteVST], 2>;
420 def M4WriteVSTB : WriteSequence<[WriteVST], 3>;
421 def M4WriteVSTC : WriteSequence<[WriteVST], 4>;
422 def M4WriteVSTD : SchedWriteRes<[M4UnitS,
423 M4UnitFST]> { let Latency = 2; }
424 def M4WriteVSTE : SchedWriteRes<[M4UnitS,
427 M4UnitFST]> { let Latency = 2;
428 let NumMicroOps = 2; }
429 def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF,
433 M4UnitFST]> { let Latency = 4;
435 let ResourceCycles = [1, 2, 1, 2, 1]; }
436 def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF,
444 M4UnitFST]> { let Latency = 5;
446 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
447 def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF,
458 M4UnitFST]> { let Latency = 8;
460 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
461 def M4WriteVSTJ : SchedWriteRes<[M4UnitA,
463 M4UnitFST]> { let Latency = 1;
464 let NumMicroOps = 2; }
465 def M4WriteVSTK : SchedWriteRes<[M4UnitA,
467 M4UnitFST]> { let Latency = 3;
468 let NumMicroOps = 2; }
469 def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF,
474 M4UnitFST]> { let Latency = 4;
476 let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
479 def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
480 SchedVar<NoSchedPred, [M4WriteZ0]>]>;
481 def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
482 SchedVar<NoSchedPred, [M4WriteNALU1]>]>;
483 def M4WriteMULL : SchedWriteVariant<[SchedVar<ExynosLongVectorUpperPred, [M4WriteNEONM]>,
484 SchedVar<NoSchedPred, [M4WriteNMUL3]>]>;
487 def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>;
488 def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4,
491 def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>;
492 def M4ReadMULLP2 : SchedReadAdvance<-2, [M4WriteNEONM]>;
494 //===----------------------------------------------------------------------===//
495 // Coarse scheduling model.
497 // Branch instructions.
498 def : SchedAlias<WriteBr, M4WriteZ0>;
499 def : SchedAlias<WriteBrReg, M4WriteC1>;
501 // Arithmetic and logical integer instructions.
502 def : SchedAlias<WriteI, M4WriteA1>;
503 def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
504 def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
505 def : SchedAlias<WriteIS, M4WriteA1>;
507 // Move instructions.
508 def : SchedAlias<WriteImm, M4WriteA1>;
510 // Divide and multiply instructions.
511 def : SchedAlias<WriteID32, M4WriteD12>;
512 def : SchedAlias<WriteID64, M4WriteD21>;
513 def : SchedAlias<WriteIM32, M4WriteC3>;
514 def : SchedAlias<WriteIM64, M4WriteCA>;
516 // Miscellaneous instructions.
517 def : SchedAlias<WriteExtr, M4WriteAY>;
520 def : SchedAlias<WriteAdr, M4WriteZ1>;
521 def : SchedAlias<ReadAdrBase, M4ReadAdrBase>;
523 // Load instructions.
524 def : SchedAlias<WriteLD, M4WriteL4>;
525 def : SchedAlias<WriteLDHi, M4WriteZ4>;
526 def : SchedAlias<WriteLDIdx, M4WriteLX>;
528 // Store instructions.
529 def : SchedAlias<WriteST, M4WriteS1>;
530 def : SchedAlias<WriteSTP, M4WriteS1>;
531 def : SchedAlias<WriteSTX, M4WriteS1>;
532 def : SchedAlias<WriteSTIdx, M4WriteSX>;
534 // FP data instructions.
535 def : SchedAlias<WriteF, M4WriteFADD2>;
536 def : SchedAlias<WriteFCmp, M4WriteNMSC2>;
537 def : SchedAlias<WriteFDiv, M4WriteFDIV12>;
538 def : SchedAlias<WriteFMul, M4WriteFMAC3>;
540 // FP miscellaneous instructions.
541 def : SchedAlias<WriteFCvt, M4WriteFCVT2>;
542 def : SchedAlias<WriteFImm, M4WriteNALU1>;
543 def : SchedAlias<WriteFCopy, M4WriteCOPY>;
545 // FP load instructions.
546 def : SchedAlias<WriteVLD, M4WriteL5>;
548 // FP store instructions.
549 def : SchedAlias<WriteVST, M4WriteVST1>;
551 // ASIMD FP instructions.
552 def : SchedAlias<WriteV, M4WriteNALU1>;
554 // Other miscellaneous instructions.
555 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
556 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
557 def : WriteRes<WriteHint, []> { let Latency = 1; }
558 def : WriteRes<WriteSys, []> { let Latency = 1; }
560 //===----------------------------------------------------------------------===//
561 // Generic fast forwarding.
563 // TODO: Add FP register forwarding rules.
565 def : ReadAdvance<ReadI, 0>;
566 def : ReadAdvance<ReadISReg, 0>;
567 def : ReadAdvance<ReadIEReg, 0>;
568 def : ReadAdvance<ReadIM, 0>;
569 // TODO: The forwarding for 32 bits actually saves 2 cycles.
570 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
571 def : ReadAdvance<ReadID, 0>;
572 def : ReadAdvance<ReadExtrHi, 0>;
573 def : ReadAdvance<ReadAdrBase, 0>;
574 def : ReadAdvance<ReadVLD, 0>;
576 //===----------------------------------------------------------------------===//
577 // Finer scheduling model.
579 // Branch instructions
580 def : InstRW<[M4WriteB1], (instrs Bcc)>;
581 def : InstRW<[M4WriteAF], (instrs BL)>;
582 def : InstRW<[M4WriteBX], (instrs BLR)>;
583 def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>;
584 def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>;
586 // Arithmetic and logical integer instructions.
587 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
588 def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>;
589 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
590 def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
591 def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>;
593 // Move instructions.
594 def : InstRW<[M4WriteCOPY], (instrs COPY)>;
595 def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>;
596 def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>;
598 // Divide and multiply instructions.
600 // Miscellaneous instructions.
602 // Load instructions.
603 def : InstRW<[M4WriteLD,
605 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
606 def : InstRW<[M4WriteL5,
607 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
608 def : InstRW<[WriteLDIdx,
609 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
610 def : InstRW<[M4WriteL5,
611 ReadAdrBase], (instrs PRFMroW)>;
612 def : InstRW<[WriteLDIdx,
613 ReadAdrBase], (instrs PRFMroX)>;
615 // Store instructions.
616 def : InstRW<[M4WriteSB,
617 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
618 def : InstRW<[WriteST,
619 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
621 // FP data instructions.
622 def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>;
623 def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>;
624 def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>;
625 def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>;
626 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>;
627 def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>;
628 def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>;
629 def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>;
630 def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
631 def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>;
632 def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>;
633 def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>;
634 def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
635 def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>;
636 def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>;
637 def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>;
638 def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>;
639 def : InstRW<[M4WriteFMAC4H,
640 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>;
641 def : InstRW<[M4WriteFMAC4,
642 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>;
643 def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>;
644 def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>;
645 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
646 def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
647 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>;
648 def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>;
649 def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>;
651 // FP miscellaneous instructions.
652 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>;
653 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>;
654 def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>;
655 def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
656 def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
657 def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>;
658 def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>;
659 def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>;
660 def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>;
661 def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>;
662 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
663 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
664 def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>;
665 def : InstRW<[M4WriteFMAC4H,
666 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S16")>;
667 def : InstRW<[M4WriteFMAC4,
668 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S(32|64)")>;
670 // FP load instructions.
671 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
672 def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>;
673 def : InstRW<[WriteVLD,
674 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
675 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
676 def : InstRW<[M4WriteLE,
677 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
678 def : InstRW<[WriteVLD,
679 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
680 def : InstRW<[M4WriteLE,
681 ReadAdrBase], (instrs LDRQroX)>;
682 def : InstRW<[WriteVLD,
683 M4WriteLH], (instregex "^LDN?P[SD]i")>;
684 def : InstRW<[M4WriteLA,
685 M4WriteLH], (instregex "^LDN?PQi")>;
686 def : InstRW<[M4WriteL5,
688 WriteAdr], (instregex "^LDP[SD]post")>;
689 def : InstRW<[M4WriteLB,
691 WriteAdr], (instrs LDPQpost)>;
692 def : InstRW<[M4WriteLB,
694 WriteAdr], (instregex "^LDP[SD]pre")>;
695 def : InstRW<[M4WriteLC,
697 WriteAdr], (instrs LDPQpre)>;
699 // FP store instructions.
700 def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>;
701 def : InstRW<[WriteVST,
702 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>;
703 def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>;
704 def : InstRW<[M4WriteVSTJ,
705 ReadAdrBase], (instregex "^STR[BHSD]roW")>;
706 def : InstRW<[M4WriteVSTK,
707 ReadAdrBase], (instrs STRQroW)>;
708 def : InstRW<[WriteVST,
709 ReadAdrBase], (instregex "^STR[BHSD]roX")>;
710 def : InstRW<[M4WriteVSTK,
711 ReadAdrBase], (instrs STRQroX)>;
712 def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>;
713 def : InstRW<[M4WriteVSTA], (instregex "^STN?PQi")>;
714 def : InstRW<[WriteVST,
715 WriteAdr], (instregex "^STP[SD](post|pre)")>;
716 def : InstRW<[M4WriteVSTJ,
717 WriteAdr], (instregex "^STPQ(post|pre)")>;
719 // ASIMD instructions.
720 def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>;
721 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>;
722 def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>;
723 def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
724 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>;
725 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>;
726 def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>;
727 def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>;
728 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>;
729 def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>;
730 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>;
731 def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>;
732 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
733 def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
734 def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>;
735 def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
736 def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
737 def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
738 def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
739 def : InstRW<[M4WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>;
740 def : InstRW<[M4WriteNMUL3,
741 M4ReadNMULM1], (instregex "^ML[AS]v")>;
742 def : InstRW<[M4WriteNMUL3], (instregex "^SQRDML[AS]H")>;
743 def : InstRW<[M4WriteMULL,
744 M4ReadMULLP2], (instregex "^(S|U|SQD)ML[AS]Lv")>;
745 def : InstRW<[M4WriteMULL,
746 M4ReadMULLP2], (instregex "^(S|U|SQD)MULLv")>;
747 def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>;
748 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>;
749 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
750 def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>;
751 def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>;
752 def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
753 def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>;
754 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
755 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
756 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
758 // ASIMD FP instructions.
759 def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>;
760 def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>;
761 def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>;
762 def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>;
763 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>;
764 def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>;
765 def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
766 def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>;
767 def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
768 def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>;
769 def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>;
770 def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>;
771 def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>;
772 def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>;
773 def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>;
774 def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>;
775 def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>;
776 def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
777 def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
778 def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>;
779 def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>;
780 def : InstRW<[M4WriteFMAC4H,
781 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>;
782 def : InstRW<[M4WriteFMAC4,
783 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>;
784 def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>;
785 def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>;
786 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
787 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>;
788 def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>;
789 def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>;
790 def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>;
791 def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>;
793 // ASIMD miscellaneous instructions.
794 def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>;
795 def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>;
796 def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>;
797 def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>;
798 def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>;
799 def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>;
800 def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>;
801 def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>;
802 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
803 def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>;
804 def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>;
805 def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>;
806 def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>;
807 def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>;
808 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
809 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
810 def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
811 def : InstRW<[M4WriteFMAC4H,
812 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f16")>;
813 def : InstRW<[M4WriteFMAC4,
814 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
815 def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>;
816 def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>;
817 def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>;
818 def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>;
819 def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>;
820 def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>;
821 def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
823 // ASIMD load instructions.
824 def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
825 def : InstRW<[WriteVLD,
826 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
827 def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
828 def : InstRW<[WriteVLD,
829 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
831 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
832 def : InstRW<[M4WriteVLDA,
833 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
834 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
835 def : InstRW<[M4WriteVLDA,
836 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
838 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
839 def : InstRW<[M4WriteVLDB,
840 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
841 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
842 def : InstRW<[M4WriteVLDB,
843 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
845 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
846 def : InstRW<[M4WriteVLDC,
847 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
848 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
849 def : InstRW<[M4WriteVLDC,
850 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
852 def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
853 def : InstRW<[M4WriteVLDD,
854 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>;
856 def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
857 def : InstRW<[WriteVLD,
858 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
859 def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
860 def : InstRW<[WriteVLD,
861 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
863 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
864 def : InstRW<[M4WriteVLDF,
865 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
866 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
867 def : InstRW<[M4WriteVLDF,
868 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
870 def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
871 def : InstRW<[M4WriteVLDG,
872 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>;
874 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
875 def : InstRW<[M4WriteVLDA,
876 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
877 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
878 def : InstRW<[M4WriteVLDA,
879 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
881 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
882 def : InstRW<[M4WriteVLDI,
883 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
884 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
885 def : InstRW<[M4WriteVLDI,
886 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
888 def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
889 def : InstRW<[M4WriteVLDJ,
890 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>;
891 def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>;
892 def : InstRW<[M4WriteVLDL,
893 M4WriteA1], (instregex "LD3i64_POST$")>;
895 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
896 def : InstRW<[M4WriteVLDB,
897 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
898 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
899 def : InstRW<[M4WriteVLDB,
900 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
902 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
903 def : InstRW<[M4WriteVLDN,
904 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
905 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
906 def : InstRW<[M4WriteVLDN,
907 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
909 def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>;
910 def : InstRW<[M4WriteVLDK,
911 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>;
912 def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>;
913 def : InstRW<[M4WriteVLDM,
914 M4WriteA1], (instregex "LD4i64_POST$")>;
916 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
917 def : InstRW<[M4WriteVLDC,
918 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
919 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
920 def : InstRW<[M4WriteVLDC,
921 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
923 // ASIMD store instructions.
924 def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
925 def : InstRW<[WriteVST,
926 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
927 def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
928 def : InstRW<[WriteVST,
929 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
931 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
932 def : InstRW<[M4WriteVSTA,
933 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
934 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
935 def : InstRW<[M4WriteVSTA,
936 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
938 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
939 def : InstRW<[M4WriteVSTB,
940 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
941 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
942 def : InstRW<[M4WriteVSTB,
943 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
945 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
946 def : InstRW<[M4WriteVSTC,
947 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
948 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
949 def : InstRW<[M4WriteVSTC,
950 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
952 def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>;
953 def : InstRW<[WriteVST,
954 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>;
956 def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
957 def : InstRW<[M4WriteVSTD,
958 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
959 def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
960 def : InstRW<[M4WriteVSTE,
961 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
963 def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
964 def : InstRW<[M4WriteVSTD,
965 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>;
967 def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
968 def : InstRW<[M4WriteVSTF,
969 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
970 def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
971 def : InstRW<[M4WriteVSTG,
972 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
974 def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>;
975 def : InstRW<[M4WriteVSTE,
976 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>;
978 def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
979 def : InstRW<[M4WriteVSTL,
980 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
981 def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
982 def : InstRW<[M4WriteVSTI,
983 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
985 def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>;
986 def : InstRW<[M4WriteVSTE,
987 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>;
989 // Cryptography instructions.
990 def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>;
991 def : InstRW<[M4WriteNCRY1,
992 M4ReadAESM1], (instregex "^AESI?MC")>;
993 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>;
994 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
995 def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
996 def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
997 def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>;
998 def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>;
999 def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>;
1001 // CRC instructions.
1002 def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>;
1004 } // SchedModel = ExynosM4Model