1 //==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Qualcomm Falkor to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Define the SchedMachineModel and provide basic properties for coarse grained
17 // instruction cost model.
19 def FalkorModel : SchedMachineModel {
20 let IssueWidth = 4; // 4-wide issue for expanded uops.
21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
22 let LoopMicroOpBufferSize = 16;
23 let LoadLatency = 3; // Optimistic load latency.
24 let MispredictPenalty = 11; // Minimum branch misprediction penalty.
25 let CompleteModel = 0;