contrib/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td

   1 //==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the uop and latency details for the machine model for the
  11 // Qualcomm Falkor subtarget.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Contains all of the Falkor specific SchedWriteRes types. The approach
  16 // below is to define a generic SchedWriteRes for every combination of
  17 // latency and microOps. The naming conventions is to use a prefix, one field
  18 // for latency, and one or more microOp count/type designators.
  19 //   Prefix: FalkorWr
  20 //   MicroOp Count/Types: #(B|X|Y|Z|LD|ST|SD|VX|VY|VSD)
  21 //   Latency: #cyc
  22 //
  23 // e.g. FalkorWr_1Z_6SD_4VX_6cyc means there are 11 micro-ops to be issued
  24 //      down one Z pipe, six SD pipes, four VX pipes and the total latency is
  25 //      six cycles.
  26 //
  27 // Contains all of the Falkor specific ReadAdvance types for forwarding logic.
  28 //
  29 // Contains all of the Falkor specific WriteVariant types for immediate zero
  30 // and LSLFast.
  31 //===----------------------------------------------------------------------===//
  32
  33 //===----------------------------------------------------------------------===//
  34 // Define 0 micro-op types
  35 def FalkorWr_none_1cyc : SchedWriteRes<[]> {
  36   let Latency = 1;
  37   let NumMicroOps = 0;
  38 }
  39 def FalkorWr_none_3cyc : SchedWriteRes<[]> {
  40   let Latency = 3;
  41   let NumMicroOps = 0;
  42 }
  43 def FalkorWr_none_4cyc : SchedWriteRes<[]> {
  44   let Latency = 4;
  45   let NumMicroOps = 0;
  46 }
  47
  48 //===----------------------------------------------------------------------===//
  49 // Define 1 micro-op types
  50
  51 def FalkorWr_1X_2cyc    : SchedWriteRes<[FalkorUnitX]>   { let Latency = 2; }
  52 def FalkorWr_IMUL32_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; }
  53 def FalkorWr_IMUL64_1X_4cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; }
  54 def FalkorWr_IMUL64_1X_5cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 5; }
  55 def FalkorWr_1Z_0cyc    : SchedWriteRes<[FalkorUnitZ]>   { let Latency = 0; }
  56 def FalkorWr_1ZB_0cyc   : SchedWriteRes<[FalkorUnitZB]>  { let Latency = 0; }
  57 def FalkorWr_1LD_3cyc   : SchedWriteRes<[FalkorUnitLD]>  { let Latency = 3; }
  58 def FalkorWr_1LD_4cyc   : SchedWriteRes<[FalkorUnitLD]>  { let Latency = 4; }
  59 def FalkorWr_1XYZ_0cyc  : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 0; }
  60 def FalkorWr_1XYZ_1cyc  : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 1; }
  61 def FalkorWr_1XYZ_2cyc  : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 2; }
  62 def FalkorWr_1XYZB_0cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 0; }
  63 def FalkorWr_1XYZB_1cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 1; }
  64 def FalkorWr_1none_0cyc : SchedWriteRes<[]>              { let Latency = 0; }
  65
  66 def FalkorWr_1VXVY_0cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 0; }
  67 def FalkorWr_1VXVY_1cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 1; }
  68 def FalkorWr_1VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 2; }
  69 def FalkorWr_1VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 3; }
  70 def FalkorWr_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; }
  71 def FalkorWr_VMUL32_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; }
  72 def FalkorWr_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; }
  73 def FalkorWr_FMUL32_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; }
  74 def FalkorWr_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; }
  75 def FalkorWr_FMUL64_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; }
  76
  77 def FalkorWr_1LD_0cyc   : SchedWriteRes<[FalkorUnitLD]>  { let Latency = 0; }
  78 def FalkorWr_1ST_0cyc   : SchedWriteRes<[FalkorUnitST]>  { let Latency = 0; }
  79 def FalkorWr_1ST_3cyc   : SchedWriteRes<[FalkorUnitST]>  { let Latency = 3; }
  80
  81 def FalkorWr_1GTOV_0cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 0; }
  82 def FalkorWr_1GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 1; }
  83 def FalkorWr_1GTOV_4cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 4; }
  84 def FalkorWr_1VTOG_1cyc : SchedWriteRes<[FalkorUnitVTOG]>{ let Latency = 1; }
  85
  86 //===----------------------------------------------------------------------===//
  87 // Define 2 micro-op types
  88
  89 def FalkorWr_2VXVY_0cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
  90   let Latency = 0;
  91   let NumMicroOps = 2;
  92 }
  93 def FalkorWr_2VXVY_1cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
  94   let Latency = 1;
  95   let NumMicroOps = 2;
  96 }
  97 def FalkorWr_2VXVY_2cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
  98   let Latency = 2;
  99   let NumMicroOps = 2;
 100 }
 101 def FalkorWr_2VXVY_3cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 102   let Latency = 3;
 103   let NumMicroOps = 2;
 104 }
 105 def FalkorWr_2VXVY_4cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 106   let Latency = 4;
 107   let NumMicroOps = 2;
 108 }
 109 def FalkorWr_VMUL32_2VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 110   let Latency = 4;
 111   let NumMicroOps = 2;
 112 }
 113 def FalkorWr_2VXVY_5cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 114   let Latency = 5;
 115   let NumMicroOps = 2;
 116 }
 117 def FalkorWr_FMUL32_2VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 118   let Latency = 5;
 119   let NumMicroOps = 2;
 120 }
 121 def FalkorWr_2VXVY_6cyc   : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 122   let Latency = 6;
 123   let NumMicroOps = 2;
 124 }
 125 def FalkorWr_FMUL64_2VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 126   let Latency = 6;
 127   let NumMicroOps = 2;
 128 }
 129
 130 def FalkorWr_1LD_1VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> {
 131   let Latency = 4;
 132   let NumMicroOps = 2;
 133 }
 134 def FalkorWr_1XYZ_1LD_4cyc  : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> {
 135   let Latency = 4;
 136   let NumMicroOps = 2;
 137 }
 138 def FalkorWr_2LD_3cyc   : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> {
 139   let Latency = 3;
 140   let NumMicroOps = 2;
 141 }
 142
 143 def FalkorWr_1VX_1VY_5cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> {
 144   let Latency = 5;
 145   let NumMicroOps = 2;
 146 }
 147
 148 def FalkorWr_1VX_1VY_2cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> {
 149   let Latency = 2;
 150   let NumMicroOps = 2;
 151 }
 152
 153 def FalkorWr_1VX_1VY_4cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> {
 154   let Latency = 4;
 155   let NumMicroOps = 2;
 156 }
 157
 158 def FalkorWr_1VX_1VY_10cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> {
 159   let Latency = 10;
 160   let NumMicroOps = 2;
 161 }
 162
 163 def FalkorWr_1GTOV_1VXVY_2cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitVXVY]> {
 164   let Latency = 2;
 165   let NumMicroOps = 2;
 166 }
 167
 168 def FalkorWr_2GTOV_1cyc    : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitGTOV]> {
 169   let Latency = 1;
 170   let NumMicroOps = 2;
 171 }
 172
 173 def FalkorWr_1XYZ_1ST_4cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST]> {
 174   let Latency = 4;
 175   let NumMicroOps = 2;
 176 }
 177 def FalkorWr_1XYZ_1LD_5cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> {
 178   let Latency = 5;
 179   let NumMicroOps = 2;
 180 }
 181
 182 def FalkorWr_2XYZ_2cyc   : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitXYZ]> {
 183   let Latency = 2;
 184   let NumMicroOps = 2;
 185 }
 186
 187 def FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> {
 188   let Latency = 0;
 189   let NumMicroOps = 2;
 190 }
 191
 192 def FalkorWr_1X_1Z_8cyc  : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
 193   let Latency = 8;
 194   let NumMicroOps = 2;
 195   let ResourceCycles = [2, 8];
 196 }
 197
 198 def FalkorWr_1X_1Z_16cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
 199   let Latency = 16;
 200   let NumMicroOps = 2;
 201   let ResourceCycles = [2, 16];
 202 }
 203
 204 def FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> {
 205   let Latency = 3;
 206   let NumMicroOps = 2;
 207 }
 208
 209 def FalkorWr_1LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD]> {
 210   let Latency = 3;
 211   let NumMicroOps = 2;
 212 }
 213
 214 def FalkorWr_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitSD, FalkorUnitST]> {
 215   let Latency = 0;
 216   let NumMicroOps = 2;
 217 }
 218
 219 def FalkorWr_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitVSD, FalkorUnitST]> {
 220   let Latency = 0;
 221   let NumMicroOps = 2;
 222 }
 223
 224 //===----------------------------------------------------------------------===//
 225 // Define 3 micro-op types
 226
 227 def FalkorWr_1ST_1SD_1LD_0cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD,
 228                                                FalkorUnitLD]> {
 229   let Latency = 0;
 230   let NumMicroOps = 3;
 231 }
 232
 233 def FalkorWr_1ST_1SD_1LD_3cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD,
 234                                                FalkorUnitLD]> {
 235   let Latency = 3;
 236   let NumMicroOps = 3;
 237 }
 238
 239 def FalkorWr_3VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 240   let Latency = 3;
 241   let NumMicroOps = 3;
 242 }
 243
 244 def FalkorWr_3VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 245   let Latency = 4;
 246   let NumMicroOps = 3;
 247 }
 248
 249 def FalkorWr_3VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 250   let Latency = 5;
 251   let NumMicroOps = 3;
 252 }
 253
 254 def FalkorWr_3VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
 255   let Latency = 6;
 256   let NumMicroOps = 3;
 257 }
 258
 259 def FalkorWr_1LD_2VXVY_4cyc  : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> {
 260   let Latency = 4;
 261   let NumMicroOps = 3;
 262 }
 263
 264 def FalkorWr_2LD_1none_3cyc  : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> {
 265   let Latency = 3;
 266   let NumMicroOps = 3;
 267 }
 268
 269 def FalkorWr_3LD_3cyc        : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 270                                               FalkorUnitLD]> {
 271   let Latency = 3;
 272   let NumMicroOps = 3;
 273 }
 274
 275 def FalkorWr_2LD_1Z_3cyc     : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 276                                              FalkorUnitZ]> {
 277   let Latency = 3;
 278   let NumMicroOps = 3;
 279 }
 280
 281 def FalkorWr_1XYZ_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitSD, FalkorUnitST]> {
 282   let Latency = 0;
 283   let NumMicroOps = 3;
 284 }
 285 def FalkorWr_1XYZ_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitVSD, FalkorUnitST]> {
 286   let Latency = 0;
 287   let NumMicroOps = 3;
 288 }
 289 //===----------------------------------------------------------------------===//
 290 // Define 4 micro-op types
 291
 292 def FalkorWr_2VX_2VY_2cyc  : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY,
 293                                             FalkorUnitVX, FalkorUnitVY]> {
 294   let Latency = 2;
 295   let NumMicroOps = 4;
 296 }
 297
 298 def FalkorWr_4VXVY_2cyc    : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
 299                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 300   let Latency = 2;
 301   let NumMicroOps = 4;
 302 }
 303 def FalkorWr_4VXVY_3cyc    : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
 304                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 305   let Latency = 3;
 306   let NumMicroOps = 4;
 307 }
 308 def FalkorWr_4VXVY_4cyc    : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
 309                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 310   let Latency = 4;
 311   let NumMicroOps = 4;
 312 }
 313 def FalkorWr_4VXVY_6cyc    : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
 314                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 315   let Latency = 6;
 316   let NumMicroOps = 4;
 317 }
 318
 319 def FalkorWr_4LD_3cyc      : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 320                                             FalkorUnitLD, FalkorUnitLD]> {
 321   let Latency = 3;
 322   let NumMicroOps = 4;
 323 }
 324
 325 def FalkorWr_1LD_3VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY,
 326                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 327   let Latency = 4;
 328   let NumMicroOps = 4;
 329 }
 330
 331 def FalkorWr_2LD_2none_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> {
 332   let Latency = 3;
 333   let NumMicroOps = 4;
 334 }
 335
 336 def FalkorWr_2LD_1ST_1SD_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitST,
 337                                               FalkorUnitSD, FalkorUnitLD]> {
 338   let Latency = 3;
 339   let NumMicroOps = 4;
 340 }
 341
 342 def FalkorWr_2VSD_2ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD,
 343                                            FalkorUnitST, FalkorUnitVSD]> {
 344   let Latency = 0;
 345   let NumMicroOps = 4;
 346 }
 347
 348 //===----------------------------------------------------------------------===//
 349 // Define 5 micro-op types
 350
 351 def FalkorWr_1LD_4VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY,
 352                                             FalkorUnitVXVY, FalkorUnitVXVY,
 353                                             FalkorUnitVXVY]> {
 354   let Latency = 4;
 355   let NumMicroOps = 5;
 356 }
 357 def FalkorWr_2LD_2VXVY_1none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 358                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 359   let Latency = 4;
 360   let NumMicroOps = 5;
 361 }
 362 def FalkorWr_5VXVY_7cyc    : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
 363                                             FalkorUnitVXVY, FalkorUnitVXVY,
 364                                             FalkorUnitVXVY]> {
 365   let Latency = 7;
 366   let NumMicroOps = 5;
 367 }
 368 def FalkorWr_1XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST,
 369                                                 FalkorUnitVSD, FalkorUnitST,
 370                                                 FalkorUnitVSD]> {
 371   let Latency = 0;
 372   let NumMicroOps = 5;
 373 }
 374 def FalkorWr_1VXVY_2ST_2VSD_0cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST,
 375                                                   FalkorUnitVSD, FalkorUnitST,
 376                                                   FalkorUnitVSD]> {
 377   let Latency = 0;
 378   let NumMicroOps = 5;
 379 }
 380 //===----------------------------------------------------------------------===//
 381 // Define 6 micro-op types
 382
 383 def FalkorWr_2LD_2VXVY_2none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 384                                             FalkorUnitVXVY, FalkorUnitVXVY]> {
 385   let Latency = 4;
 386   let NumMicroOps = 6;
 387 }
 388
 389 def FalkorWr_2XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST,
 390                                                 FalkorUnitVSD, FalkorUnitXYZ,
 391                                                 FalkorUnitST, FalkorUnitVSD]> {
 392   let Latency = 0;
 393   let NumMicroOps = 6;
 394 }
 395
 396 def FalkorWr_2VXVY_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST,
 397                                                  FalkorUnitVSD, FalkorUnitVXVY,
 398                                                  FalkorUnitST, FalkorUnitVSD]> {
 399   let Latency = 0;
 400   let NumMicroOps = 6;
 401 }
 402
 403 def FalkorWr_3VSD_3ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD,
 404                                            FalkorUnitST, FalkorUnitVSD,
 405                                            FalkorUnitST, FalkorUnitVSD]> {
 406   let Latency = 0;
 407   let NumMicroOps = 6;
 408 }
 409
 410 //===----------------------------------------------------------------------===//
 411 // Define 8 micro-op types
 412
 413 def FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
 414                                              FalkorUnitVXVY, FalkorUnitVXVY,
 415                                              FalkorUnitLD, FalkorUnitLD,
 416                                              FalkorUnitVXVY, FalkorUnitVXVY]> {
 417   let Latency = 4;
 418   let NumMicroOps = 8;
 419 }
 420
 421 def FalkorWr_4VSD_4ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD,
 422                                            FalkorUnitST, FalkorUnitVSD,
 423                                            FalkorUnitST, FalkorUnitVSD,
 424                                            FalkorUnitST, FalkorUnitVSD]> {
 425   let Latency = 0;
 426   let NumMicroOps = 8;
 427 }
 428
 429 //===----------------------------------------------------------------------===//
 430 // Define 9 micro-op types
 431
 432 def FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD,
 433                                              FalkorUnitLD, FalkorUnitVXVY,
 434                                              FalkorUnitVXVY, FalkorUnitLD,
 435                                              FalkorUnitLD, FalkorUnitXYZ,
 436                                              FalkorUnitVXVY, FalkorUnitVXVY]> {
 437   let Latency = 4;
 438   let NumMicroOps = 9;
 439 }
 440
 441 def FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD,
 442                                              FalkorUnitLD, FalkorUnitVXVY,
 443                                              FalkorUnitVXVY, FalkorUnitXYZ,
 444                                              FalkorUnitLD, FalkorUnitLD,
 445                                              FalkorUnitVXVY, FalkorUnitVXVY]> {
 446   let Latency = 4;
 447   let NumMicroOps = 9;
 448 }
 449
 450 //===----------------------------------------------------------------------===//
 451 // Define 10 micro-op types
 452
 453 def FalkorWr_2VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST,
 454                                                  FalkorUnitVSD, FalkorUnitVXVY,
 455                                                  FalkorUnitST, FalkorUnitVSD,
 456                                                  FalkorUnitST, FalkorUnitVSD,
 457                                                  FalkorUnitST, FalkorUnitVSD]> {
 458   let Latency = 0;
 459   let NumMicroOps = 10;
 460 }
 461
 462 //===----------------------------------------------------------------------===//
 463 // Define 12 micro-op types
 464
 465 def FalkorWr_4VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST,
 466                                                  FalkorUnitVSD, FalkorUnitVXVY,
 467                                                  FalkorUnitST, FalkorUnitVSD,
 468                                                  FalkorUnitVXVY, FalkorUnitST,
 469                                                  FalkorUnitVSD, FalkorUnitVXVY,
 470                                                  FalkorUnitST, FalkorUnitVSD]> {
 471   let Latency = 0;
 472   let NumMicroOps = 12;
 473 }
 474
 475 // Forwarding logic is modeled for multiply add/accumulate.
 476 // -----------------------------------------------------------------------------
 477 def FalkorReadIMA32  : SchedReadAdvance<3, [FalkorWr_IMUL32_1X_2cyc]>;
 478 def FalkorReadIMA64  : SchedReadAdvance<4, [FalkorWr_IMUL64_1X_4cyc, FalkorWr_IMUL64_1X_5cyc]>;
 479 def FalkorReadVMA    : SchedReadAdvance<3, [FalkorWr_VMUL32_1VXVY_4cyc, FalkorWr_VMUL32_2VXVY_4cyc]>;
 480 def FalkorReadFMA32  : SchedReadAdvance<1, [FalkorWr_FMUL32_1VXVY_5cyc, FalkorWr_FMUL32_2VXVY_5cyc]>;
 481 def FalkorReadFMA64  : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr_FMUL64_2VXVY_6cyc]>;
 482
 483 // SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast
 484 // -----------------------------------------------------------------------------
 485 def FalkorImmZPred    : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>;
 486 def FalkorOp1ZrReg    : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR ||
 487
 488                                          MI->getOperand(1).getReg() == AArch64::XZR}]>;
 489 def FalkorShiftExtFastPred : SchedPredicate<[{TII->isFalkorShiftExtFast(*MI)}]>;
 490
 491 def FalkorWr_FMOV  : SchedWriteVariant<[
 492                        SchedVar<FalkorOp1ZrReg,  [FalkorWr_1none_0cyc]>,
 493                        SchedVar<NoSchedPred,     [FalkorWr_1GTOV_1cyc]>]>;
 494
 495 def FalkorWr_MOVZ  : SchedWriteVariant<[
 496                        SchedVar<FalkorImmZPred, [FalkorWr_1none_0cyc]>,
 497                        SchedVar<NoSchedPred,    [FalkorWr_1XYZB_0cyc]>]>; // imm fwd
 498
 499
 500 def FalkorWr_ADDSUBsx : SchedWriteVariant<[
 501                           SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_1cyc]>,
 502                           SchedVar<NoSchedPred,            [FalkorWr_2XYZ_2cyc]>]>;
 503
 504 def FalkorWr_LDRro : SchedWriteVariant<[
 505                        SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_3cyc]>,
 506                        SchedVar<NoSchedPred,            [FalkorWr_1XYZ_1LD_4cyc]>]>;
 507
 508 def FalkorWr_LDRSro : SchedWriteVariant<[
 509                         SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_4cyc]>,
 510                         SchedVar<NoSchedPred,            [FalkorWr_1XYZ_1LD_5cyc]>]>;
 511
 512 def FalkorWr_ORRi : SchedWriteVariant<[
 513                       SchedVar<FalkorOp1ZrReg, [FalkorWr_1XYZ_0cyc]>, // imm fwd
 514                       SchedVar<NoSchedPred,    [FalkorWr_1XYZ_1cyc]>]>;
 515
 516 def FalkorWr_PRFMro : SchedWriteVariant<[
 517                         SchedVar<FalkorShiftExtFastPred, [FalkorWr_1ST_3cyc]>,
 518                         SchedVar<NoSchedPred,            [FalkorWr_1XYZ_1ST_4cyc]>]>;
 519
 520 def FalkorWr_STRVro : SchedWriteVariant<[
 521                         SchedVar<FalkorShiftExtFastPred, [FalkorWr_1VSD_1ST_0cyc]>,
 522                         SchedVar<NoSchedPred,            [FalkorWr_1XYZ_1VSD_1ST_0cyc]>]>;
 523
 524 def FalkorWr_STRQro : SchedWriteVariant<[
 525                         SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_2ST_2VSD_0cyc]>,
 526                         SchedVar<NoSchedPred,            [FalkorWr_2XYZ_2ST_2VSD_0cyc]>]>;
 527
 528 def FalkorWr_STRro : SchedWriteVariant<[
 529                        SchedVar<FalkorShiftExtFastPred, [FalkorWr_1SD_1ST_0cyc]>,
 530                        SchedVar<NoSchedPred,            [FalkorWr_1XYZ_1SD_1ST_0cyc]>]>;
 531
 532 //===----------------------------------------------------------------------===//
 533 // Specialize the coarse model by associating instruction groups with the
 534 // subtarget-defined types. As the modeled is refined, this will override most
 535 // of the earlier mappings.
 536
 537 // Miscellaneous
 538 // -----------------------------------------------------------------------------
 539
 540 // FIXME: This could be better modeled by looking at the regclasses of the operands.
 541 def : InstRW<[FalkorWr_1XYZ_1cyc], (instrs COPY)>;
 542
 543 // SIMD Floating-point Instructions
 544 // -----------------------------------------------------------------------------
 545 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(FABS|FNEG)v2f32$")>;
 546
 547 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>;
 548 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^FAC(GE|GT)(32|64)$")>;
 549 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
 550 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
 551 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
 552
 553 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^F(MAX|MIN)(NM)?Vv4i32v$")>;
 554 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(FABD|FADD|FSUB)v2f32$")>;
 555 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^FADDP(v2i32p|v2i64p|v2f32)$")>;
 556
 557 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
 558 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instrs FCVTXNv1i64)>;
 559 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instregex "^FCVTZ(S|U)v2i32(_shift)?$")>;
 560
 561 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc],
 562                                       (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
 563 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc],
 564                                       (instrs FMULX32)>;
 565
 566 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc],
 567                                       (instregex "^(FMUL|FMULX)v1i64_indexed$")>;
 568 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc],
 569                                       (instrs FMULX64)>;
 570
 571 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
 572
 573 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f64|v4f32|v2i64p)$")>;
 574 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>;
 575 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instrs FCVTLv4i16, FCVTLv2i32)>;
 576 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
 577
 578 def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instregex "^(FDIV|FSQRT)v2f32$")>;
 579
 580 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
 581
 582 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^FCVT(N|M|P|Z|A)(S|U)(v2f64|v4f32)$")>;
 583 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instrs FCVTLv8i16, FCVTLv4i32)>;
 584 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^FCVTZ(S|U)(v2i64|v4i32)(_shift)?$")>;
 585
 586 def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc],
 587                                       (instregex "^(FMUL|FMULX)(v2f64|v4f32|v4i32_indexed)$")>;
 588
 589 def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc],
 590                                       (instregex "^(FMUL|FMULX)v2i64_indexed$")>;
 591
 592 def : InstRW<[FalkorWr_3VXVY_4cyc],   (instrs FCVTNv4i16, FCVTNv2i32, FCVTXNv2f32)>;
 593 def : InstRW<[FalkorWr_3VXVY_5cyc],   (instrs FCVTNv8i16, FCVTNv4i32, FCVTXNv4f32)>;
 594
 595 def : InstRW<[FalkorWr_2VX_2VY_2cyc], (instregex "^(FDIV|FSQRT)(v2f64|v4f32)$")>;
 596
 597 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA],
 598                                       (instregex "^ML(A|S)(v8i8|v4i16|v2i32)(_indexed)?$")>;
 599 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA],
 600                                       (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>;
 601
 602 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, FalkorReadFMA32],
 603                                       (instregex "^FML(A|S)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
 604 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, FalkorReadFMA64],
 605                                       (instregex "^FML(A|S)v1i64_indexed$")>;
 606 def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc, FalkorReadFMA32],
 607                                       (instregex "^FML(A|S)(v4f32|v4i32_indexed)$")>;
 608 def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc, FalkorReadFMA64],
 609                                       (instregex "^FML(A|S)(v2f64|v2i64_indexed)$")>;
 610
 611 // SIMD Integer Instructions
 612 // -----------------------------------------------------------------------------
 613 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
 614 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instrs ADDPv2i64p)>;
 615 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
 616 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(BIC|ORR)(v2i32|v4i16)$")>;
 617 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
 618 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
 619
 620 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.*)?$")>;
 621 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(S|U)SHLv1i64$")>;
 622 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(S|U)SHR(v2i32|v4i16|v8i8)_shift$")>;
 623 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(S|U)SHRd$")>;
 624 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$")>;
 625 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
 626 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
 627 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>;
 628 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instrs PMULv8i8)>;
 629 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^SHL(v2i32|v4i16|v8i8)_shift$")>;
 630 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^SHLd$")>;
 631
 632 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^SQNEG(v2i32|v4i16|v8i8)$")>;
 633 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)$")>;
 634 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)(ABD|ADALP)(v8i8|v4i16|v2i32)(_v.*)?$")>;
 635 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)ADDLVv4i16v$")>;
 636 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>;
 637 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>;
 638 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>;
 639 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(s|h|b)$")>;
 640 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>;
 641 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)RHADD(v2i32|v4i16|v8i8)$")>;
 642 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)RSHR(v2i32|v4i16|v8i8)_shift$")>;
 643 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)RSHRd$")>;
 644 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^R?SHRN(v2i32|v4i16|v8i8)_shift$")>;
 645 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>;
 646 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(S|U)?(MAX|MIN)V(v4i16v|v4i32v)$")>;
 647 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instrs ADDVv4i16v)>;
 648 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)$")>;
 649 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>;
 650 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
 651
 652 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instregex "^(S|U)ADDLVv8i8v$")>;
 653 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instregex "^(S|U)?(MAX|MIN)V(v8i8v|v8i16v)$")>;
 654 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instrs ADDVv8i8v)>;
 655 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc],
 656                                       (instregex "^MUL(v2i32|v4i16|v8i8)(_indexed)?$")>;
 657 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc],
 658                                       (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
 659 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc],
 660                                       (instregex "^SQDMULL(i16|i32)$")>;
 661 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA],
 662                                       (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
 663
 664 def : InstRW<[FalkorWr_1VXVY_5cyc],   (instregex "^(S|U)?(MAX|MIN)Vv16i8v$")>;
 665
 666 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instrs ADDVv4i32v)>;
 667
 668 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instrs ADDVv8i16v)>;
 669 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^(ADD|SUB)HNv.*$")>;
 670 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^(S|U)ABA(v2i32|v4i16|v8i8)$")>;
 671
 672 def : InstRW<[FalkorWr_2VXVY_5cyc],   (instrs ADDVv16i8v)>;
 673
 674 def : InstRW<[FalkorWr_2VXVY_6cyc],   (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>;
 675 def : InstRW<[FalkorWr_2VXVY_6cyc],   (instregex "^R(ADD|SUB)HNv.*$")>;
 676
 677 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
 678 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs ADDPv2i64)>; // sz==11
 679 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
 680 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
 681 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
 682
 683 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(S|U)ADDLv.*$")>;
 684 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i16)(_v.*)?$")>;
 685 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;
 686 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>;
 687 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(S|U)SUBLv.*$")>;
 688 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^((S|U)?(MAX|MIN)P?|ABS)(v16i8|v2i64|v4i32|v8i16)$")>;
 689 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^ADDP(v4i32|v8i16|v16i8)$")>; // sz!=11
 690 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^CM(EQ|GE|HS|GT|HI)(v16i8|v2i64|v4i32|v8i16)$")>;
 691 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^CM(EQ|LE|GE|GT|LT)(v16i8|v2i64|v4i32|v8i16)rz$")>;
 692 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(CMTST|PMUL)(v16i8|v2i64|v4i32|v8i16)$")>;
 693 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^PMULL(v8i8|v16i8)$")>;
 694 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^SHL(v16i8|v8i16|v4i32|v2i64)_shift$")>;
 695 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;
 696
 697 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift$")>;
 698 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)ABD(v16i8|v8i16|v4i32|v2i64)$")>;
 699 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)ABDLv.*$")>;
 700 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)(ADALP|QADD)(v16i8|v8i16|v4i32|v2i64)(_v.*)?$")>;
 701 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)QSHLU?(v2i64|v4i32|v8i16|v16i8)_shift$")>;
 702 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)(QSHL|RSHL|QRSHL|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)$")>;
 703 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(S|U)RSHR(v2i64|v4i32|v8i16|v16i8)_shift$")>;
 704 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^R?SHRN(v2i64|v4i32|v8i16|v16i8)_shift$")>;
 705 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)$")>;
 706 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^PMULL(v1i64|v2i64)$")>;
 707 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift$")>;
 708 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instregex "^SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)$")>;
 709
 710 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc],
 711                                       (instregex "^(MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
 712 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc],
 713                                       (instregex "^SQDMULLv.*$")>;
 714 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA],
 715                                       (instregex "^SQRDML(A|S)H(v16i8|v8i16|v4i32)(_indexed)?$")>;
 716
 717 def : InstRW<[FalkorWr_3VXVY_3cyc],   (instregex "^(S|U)ADDLVv4i32v$")>;
 718
 719 def : InstRW<[FalkorWr_3VXVY_5cyc],   (instregex "^(S|U)ADDLVv8i16v$")>;
 720
 721 def : InstRW<[FalkorWr_3VXVY_6cyc],   (instregex "^(S|U)ADDLVv16i8v$")>;
 722
 723 def : InstRW<[FalkorWr_4VXVY_2cyc],   (instregex "^(S|U)(ADD|SUB)Wv.*$")>;
 724
 725 def : InstRW<[FalkorWr_4VXVY_3cyc],   (instregex "^(S|U)ABALv.*$")>;
 726
 727 def : InstRW<[FalkorWr_4VXVY_4cyc],   (instregex "^(S|U)ABA(v16i8|v8i16|v4i32)$")>;
 728
 729 def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA],
 730                                       (instregex "^SQD(MLAL|MLSL)(i16|i32|v1i32_indexed|v1i64_indexed)$")>;
 731 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA],
 732                                       (instregex "^SQD(MLAL|MLSL)v[248].*$")>;
 733
 734 // SIMD Load Instructions
 735 // -----------------------------------------------------------------------------
 736 def : InstRW<[FalkorWr_1LD_3cyc],                           (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))$")>;
 737 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc],       (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>;
 738 def : InstRW<[FalkorWr_1LD_3cyc],                           (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 739 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc],       (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 740 def : InstRW<[FalkorWr_1LD_3cyc],                           (instrs LD2i64)>;
 741 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc],       (instrs LD2i64_POST)>;
 742
 743 def : InstRW<[FalkorWr_1LD_1VXVY_4cyc],                     (instregex "^LD1i(8|16|32)$")>;
 744 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_1VXVY_4cyc], (instregex "^LD1i(8|16|32)_POST$")>;
 745
 746 def : InstRW<[FalkorWr_1LD_1none_3cyc],                     (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
 747 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_1none_3cyc], (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
 748 def : InstRW<[FalkorWr_1LD_1none_3cyc],                     (instregex "^LD2Twov(8b|4h|2s|1d)$")>;
 749 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_1none_3cyc], (instregex "^LD2Twov(8b|4h|2s|1d)_POST$")>;
 750 def : InstRW<[FalkorWr_1LD_1none_3cyc],                     (instregex "^LD2Rv(8b|4h|2s|1d)$")>;
 751 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_1none_3cyc], (instregex "^LD2Rv(8b|4h|2s|1d)_POST$")>;
 752
 753 def : InstRW<[FalkorWr_2LD_3cyc],                           (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
 754 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc],       (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
 755 def : InstRW<[FalkorWr_2LD_3cyc],                           (instregex "^LD2Twov(16b|8h|4s|2d)$")>;
 756 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc],       (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>;
 757 def : InstRW<[FalkorWr_2LD_3cyc],                           (instregex "^LD2Rv(16b|8h|4s|2d)$")>;
 758 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc],       (instregex "^LD2Rv(16b|8h|4s|2d)_POST$")>;
 759 def : InstRW<[FalkorWr_2LD_3cyc],                           (instrs LD3i64)>;
 760 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc],       (instrs LD3i64_POST)>;
 761 def : InstRW<[FalkorWr_2LD_3cyc],                           (instrs LD4i64)>;
 762 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc],       (instrs LD4i64_POST)>;
 763
 764 def : InstRW<[FalkorWr_1LD_2VXVY_4cyc],                     (instregex "^LD2i(8|16|32)$")>;
 765 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_2VXVY_4cyc], (instregex "^LD2i(8|16|32)_POST$")>;
 766
 767 def : InstRW<[FalkorWr_2LD_1none_3cyc],                     (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
 768 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_1none_3cyc], (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
 769 def : InstRW<[FalkorWr_2LD_1none_3cyc],                     (instregex "^LD3Rv(8b|4h|2s|1d)$")>;
 770 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_1none_3cyc], (instregex "^LD3Rv(8b|4h|2s|1d)_POST$")>;
 771
 772 def : InstRW<[FalkorWr_3LD_3cyc],                           (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
 773 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_3LD_3cyc],       (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
 774 def : InstRW<[FalkorWr_3LD_3cyc],                           (instrs LD3Threev2d)>;
 775 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_3LD_3cyc],       (instrs LD3Threev2d_POST)>;
 776 def : InstRW<[FalkorWr_3LD_3cyc],                           (instregex "^LD3Rv(16b|8h|4s|2d)$")>;
 777 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_3LD_3cyc],       (instregex "^LD3Rv(16b|8h|4s|2d)_POST$")>;
 778
 779 def : InstRW<[FalkorWr_1LD_3VXVY_4cyc],                     (instregex "^LD3i(8|16|32)$")>;
 780 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3VXVY_4cyc], (instregex "^LD3i(8|16|32)_POST$")>;
 781
 782 def : InstRW<[FalkorWr_2LD_2none_3cyc],                     (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
 783 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2none_3cyc], (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
 784 def : InstRW<[FalkorWr_2LD_2none_3cyc],                     (instregex "^LD4Rv(8b|4h|2s|1d)$")>;
 785 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2none_3cyc], (instregex "^LD4Rv(8b|4h|2s|1d)_POST$")>;
 786
 787 def : InstRW<[FalkorWr_4LD_3cyc],                           (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
 788 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_4LD_3cyc],       (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
 789 def : InstRW<[FalkorWr_4LD_3cyc],                           (instrs LD4Fourv2d)>;
 790 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_4LD_3cyc],       (instrs LD4Fourv2d_POST)>;
 791 def : InstRW<[FalkorWr_4LD_3cyc],                           (instregex "^LD4Rv(16b|8h|4s|2d)$")>;
 792 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_4LD_3cyc],       (instregex "^LD4Rv(16b|8h|4s|2d)_POST$")>;
 793
 794 def : InstRW<[FalkorWr_1LD_4VXVY_4cyc],                     (instregex "^LD4i(8|16|32)$")>;
 795 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_4VXVY_4cyc], (instregex "^LD4i(8|16|32)_POST$")>;
 796
 797 def : InstRW<[FalkorWr_2LD_2VXVY_1none_4cyc],               (instregex "^LD3Threev(8b|4h|2s|1d)$")>;
 798 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2VXVY_1none_4cyc],
 799                                                             (instregex "^LD3Threev(8b|4h|2s|1d)_POST$")>;
 800
 801 def : InstRW<[FalkorWr_2LD_2VXVY_2none_4cyc],               (instregex "^LD4Fourv(8b|4h|2s|1d)$")>;
 802 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2VXVY_2none_4cyc],
 803                                                             (instregex "^LD4Fourv(8b|4h|2s|1d)_POST$")>;
 804
 805 def : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc],           (instregex "^LD3Threev(16b|8h|4s)$")>;
 806
 807 def : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc],           (instregex "^LD4Fourv(16b|8h|4s)$")>;
 808
 809 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc],
 810                                                             (instregex "^LD3Threev(16b|8h|4s)_POST$")>;
 811
 812 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc],
 813                                                             (instregex "^LD4Fourv(16b|8h|4s)_POST$")>;
 814
 815 // Arithmetic and Logical Instructions
 816 // -----------------------------------------------------------------------------
 817 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>;
 818 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^ADC(S)?(W|X)r$")>;
 819 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^ADD(S)?(W|X)r(r|i)$")>;
 820 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
 821 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^AND(S)?(W|X)r(i|r|s)$")>;
 822 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^BIC(S)?(W|X)r(r|s)$")>;
 823 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^EON(W|X)r(r|s)$")>;
 824 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^EOR(W|X)r(i|r|s)$")>;
 825 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^ORN(W|X)r(r|s)$")>;
 826 def : InstRW<[FalkorWr_ORRi],         (instregex "^ORR(W|X)ri$")>;
 827 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^ORR(W|X)r(r|s)$")>;
 828 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^SBC(S)?(W|X)r$")>;
 829 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^SUB(S)?(W|X)r(r|i)$")>;
 830 def : InstRW<[FalkorWr_ADDSUBsx],     (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>;
 831 def : InstRW<[FalkorWr_ADDSUBsx],     (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>;
 832
 833 // SIMD Miscellaneous Instructions
 834 // -----------------------------------------------------------------------------
 835 def : InstRW<[FalkorWr_1GTOV_1cyc],   (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>;
 836 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>;
 837 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^CPY(i8|i16|i32|i64)$")>;
 838 def : InstRW<[FalkorWr_1GTOV_1cyc],   (instregex "^INSv(i8|i16)(gpr|lane)$")>;
 839 def : InstRW<[FalkorWr_1VTOG_1cyc],   (instregex "^(S|U)MOVv.*$")>;
 840 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(BIF|BIT|BSL)v8i8$")>;
 841 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instrs EXTv8i8)>;
 842 def : InstRW<[FalkorWr_1VXVY_0cyc],   (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)$")>; // imm fwd
 843 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instrs TBLv8i8One)>;
 844 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instrs NOTv8i8)>;
 845 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^REV(16|32|64)v.*$")>;
 846 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|v4i16|v4i32|v8i8|v8i16|v16i8)$")>;
 847
 848 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
 849
 850 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "(S|U)QXTU?Nv.*$")>;
 851 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64, FRECPEv2f32, FRSQRTEv2f32)>;
 852 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instrs FRECPXv1i32, FRECPXv1i64)>;
 853 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instrs URECPEv2i32, URSQRTEv2i32)>;
 854
 855 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc],
 856                                       (instrs FRECPS32, FRSQRTS32, FRECPSv2f32, FRSQRTSv2f32)>;
 857
 858 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc],
 859                                       (instrs FRECPS64, FRSQRTS64)>;
 860
 861 def : InstRW<[FalkorWr_1GTOV_1VXVY_2cyc],
 862                                       (instregex "^INSv(i32|i64)(gpr|lane)$")>;
 863 def : InstRW<[FalkorWr_2GTOV_1cyc],   (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>;
 864 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "^(BIF|BIT|BSL)v16i8$")>;
 865 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs EXTv16i8)>;
 866 def : InstRW<[FalkorWr_2VXVY_0cyc],   (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)$")>; // imm fwd
 867 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs NOTv16i8)>;
 868 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs TBLv16i8One)>;
 869
 870 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
 871 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>;
 872 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instrs URECPEv4i32, URSQRTEv4i32)>;
 873
 874 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instrs TBLv8i8Two)>;
 875 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^TBX(v8|v16)i8One$")>;
 876
 877 def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc],
 878                                       (instrs FRECPSv4f32, FRSQRTSv4f32)>;
 879
 880 def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc],
 881                                       (instrs FRECPSv2f64, FRSQRTSv2f64)>;
 882
 883 def : InstRW<[FalkorWr_3VXVY_5cyc],   (instregex "^TBL(v8i8Three|v16i8Two)$")>;
 884 def : InstRW<[FalkorWr_3VXVY_5cyc],   (instregex "^TBX(v8i8Two|v16i8Two)$")>;
 885
 886 def : InstRW<[FalkorWr_4VXVY_6cyc],   (instregex "^TBL(v8i8Four|v16i8Three)$")>;
 887 def : InstRW<[FalkorWr_4VXVY_6cyc],   (instregex "^TBX(v8i8Three|v16i8Three)$")>;
 888
 889 def : InstRW<[FalkorWr_5VXVY_7cyc],   (instrs TBLv16i8Four)>;
 890 def : InstRW<[FalkorWr_5VXVY_7cyc],   (instregex "^TBX(v8i8Four|v16i8Four)$")>;
 891
 892 // SIMD Store Instructions
 893 // -----------------------------------------------------------------------------
 894
 895 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instregex "^STR(Q|D|S|H|B)ui$")>;
 896 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1VSD_1ST_0cyc],
 897                                        (instregex "^STR(Q|D|S|H|B)(post|pre)$")>;
 898 def : InstRW<[FalkorWr_STRVro],        (instregex "^STR(D|S|H|B)ro(W|X)$")>;
 899 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instregex "^STPQi$")>;
 900 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2VSD_2ST_0cyc],
 901                                        (instregex "^STPQ(post|pre)$")>;
 902 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instregex "^STP(D|S)(i)$")>;
 903 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1VSD_1ST_0cyc],
 904                                        (instregex "^STP(D|S)(post|pre)$")>;
 905 def : InstRW<[FalkorWr_STRQro],        (instregex "^STRQro(W|X)$")>;
 906 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instregex "^STUR(Q|D|S|B|H)i$")>;
 907 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instrs STNPDi, STNPSi)>;
 908 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instrs STNPQi)>;
 909
 910 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>;
 911 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1VSD_1ST_0cyc],
 912                                        (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>;
 913 def : InstRW<[FalkorWr_1VSD_1ST_0cyc], (instregex "^ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))$")>;
 914 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc],
 915                                        (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
 916 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc],
 917                                        (instregex "^ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))_POST$")>;
 918
 919 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
 920 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instregex "^ST2Two(v16b|v8h|v4s|v2d)$")>;
 921 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instregex "^ST3(i8|i16|i32|i64)$")>;
 922 def : InstRW<[FalkorWr_2VSD_2ST_0cyc], (instregex "^ST4(i8|i16|i32|i64)$")>;
 923 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 924 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc],
 925                                        (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
 926 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 927 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc],
 928                                        (instregex "^ST2Two(v16b|v8h|v4s|v2d)_POST$")>;
 929 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 930 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc],
 931                                        (instregex "^ST3(i8|i16|i32|i64)_POST$")>;
 932 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 933 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc],
 934                                        (instregex "^ST4(i8|i16|i32|i64)_POST$")>;
 935
 936 def : InstRW<[FalkorWr_1VXVY_2ST_2VSD_0cyc],
 937                                        (instregex "^ST3Three(v8b|v4h|v2s|v1d)$")>;
 938 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 939 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VXVY_2ST_2VSD_0cyc],
 940                                        (instregex "^ST3Three(v8b|v4h|v2s|v1d)_POST$")>;
 941
 942 def : InstRW<[FalkorWr_3VSD_3ST_0cyc], (instregex "^ST1Three(v16b|v8h|v4s|v2d)$")>;
 943 def : InstRW<[FalkorWr_3VSD_3ST_0cyc], (instrs ST3Threev2d)>;
 944 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 945 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc],
 946                                        (instregex "^ST1Three(v16b|v8h|v4s|v2d)_POST$")>;
 947 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 948 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc],
 949                                        (instrs ST3Threev2d_POST)>;
 950
 951 def : InstRW<[FalkorWr_2VXVY_2ST_2VSD_0cyc],
 952                                        (instregex "^ST4Four(v8b|v4h|v2s|v1d)$")>;
 953 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 954 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_2ST_2VSD_0cyc],
 955                                        (instregex "^ST4Four(v8b|v4h|v2s|v1d)_POST$")>;
 956
 957 def : InstRW<[FalkorWr_4VSD_4ST_0cyc], (instregex "^ST1Four(v16b|v8h|v4s|v2d)$")>;
 958 def : InstRW<[FalkorWr_4VSD_4ST_0cyc], (instrs ST4Fourv2d)>;
 959 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 960 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc],
 961                                        (instregex "^ST1Four(v16b|v8h|v4s|v2d)_POST$")>;
 962 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 963 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc],
 964                                        (instrs ST4Fourv2d_POST)>;
 965
 966 def : InstRW<[FalkorWr_2VXVY_4ST_4VSD_0cyc],
 967                                        (instregex "^ST3Three(v16b|v8h|v4s)$")>;
 968 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 969 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_4ST_4VSD_0cyc],
 970                                        (instregex "^ST3Three(v16b|v8h|v4s)_POST$")>;
 971
 972 def : InstRW<[FalkorWr_4VXVY_4ST_4VSD_0cyc],
 973                                        (instregex "^ST4Four(v16b|v8h|v4s)$")>;
 974 // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case).
 975 def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VXVY_4ST_4VSD_0cyc],
 976                                        (instregex "^ST4Four(v16b|v8h|v4s)_POST$")>;
 977
 978 // Branch Instructions
 979 // -----------------------------------------------------------------------------
 980 def : InstRW<[FalkorWr_1none_0cyc],   (instrs B, TCRETURNdi)>;
 981 def : InstRW<[FalkorWr_1Z_0cyc],      (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ)(W|X))$")>;
 982 def : InstRW<[FalkorWr_1Z_0cyc],      (instrs RET_ReallyLR, TCRETURNri)>;
 983 def : InstRW<[FalkorWr_1ZB_0cyc],     (instrs Bcc)>;
 984 def : InstRW<[FalkorWr_1XYZB_0cyc],   (instrs BL)>;
 985 def : InstRW<[FalkorWr_1Z_1XY_0cyc],  (instrs BLR)>;
 986
 987 // Cryptography Extensions
 988 // -----------------------------------------------------------------------------
 989 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instrs SHA1Hrr)>;
 990 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instrs AESIMCrr, AESMCrr)>;
 991 def : InstRW<[FalkorWr_2VXVY_3cyc],   (instrs AESDrr, AESErr)>;
 992 def : InstRW<[FalkorWr_2VXVY_2cyc],   (instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>;
 993 def : InstRW<[FalkorWr_1VX_1VY_4cyc], (instregex "^SHA1(C|M|P)rrr$")>;
 994 def : InstRW<[FalkorWr_1VX_1VY_5cyc], (instrs SHA256H2rrr, SHA256Hrrr)>;
 995 def : InstRW<[FalkorWr_4VXVY_3cyc],   (instrs SHA256SU1rrr)>;
 996
 997 // FP Load Instructions
 998 // -----------------------------------------------------------------------------
 999 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>;
1000 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc],
1001                                       (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>;
1002 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDUR(Q|D|S|H|B)i$")>;
1003 def : InstRW<[FalkorWr_LDRro],        (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
1004 def : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc],
1005                                       (instrs LDNPQi)>;
1006 def : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc],
1007                                       (instrs LDPQi)>;
1008 def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc],
1009                                       (instregex "LDNP(D|S)i$")>;
1010 def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc],
1011                                       (instregex "LDP(D|S)i$")>;
1012 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc],
1013                                       (instregex "LDP(D|S)(pre|post)$")>;
1014 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_2LD_3cyc, FalkorWr_none_3cyc],
1015                                       (instregex "^LDPQ(pre|post)$")>;
1016
1017 // FP Data Processing Instructions
1018 // -----------------------------------------------------------------------------
1019 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^FCCMP(E)?(S|D)rr$")>;
1020 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^FCMP(E)?(S|D)r(r|i)$")>;
1021 def : InstRW<[FalkorWr_1VTOG_1cyc],   (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
1022 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^(FABS|FNEG)(S|D)r$")>;
1023 def : InstRW<[FalkorWr_1VXVY_1cyc],   (instregex "^FCSEL(S|D)rrr$")>;
1024
1025 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^F(MAX|MIN)(NM)?(S|D)rr$")>;
1026 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^F(MAX|MIN)(NM)?Pv2i(32|64)p$")>;
1027 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instrs FCVTSHr, FCVTDHr)>;
1028 def : InstRW<[FalkorWr_1VXVY_2cyc],   (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
1029
1030 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^FABD(32|64)$")>;
1031 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instregex "^(FADD|FSUB)(S|D)rr$")>;
1032 def : InstRW<[FalkorWr_1VXVY_3cyc],   (instrs FCVTHSr, FCVTHDr)>;
1033
1034 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instrs FCVTSDr, FCVTDSr)>;
1035
1036 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc],
1037                                       (instregex "^F(N)?MULSrr$")>;
1038
1039 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc],
1040                                       (instregex "^F(N)?MULDrr$")>;
1041
1042 def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instregex "^FDIV(S|D)rr$")>;
1043 def : InstRW<[FalkorWr_1VX_1VY_2cyc], (instregex "^FSQRT(S|D)r$")>;
1044
1045 def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, ReadDefault, ReadDefault, FalkorReadFMA32],
1046                                       (instregex "^F(N)?M(ADD|SUB)Srrr$")>;
1047 def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, ReadDefault, ReadDefault, FalkorReadFMA64],
1048                                       (instregex "^F(N)?M(ADD|SUB)Drrr$")>;
1049
1050 // FP Miscellaneous Instructions
1051 // -----------------------------------------------------------------------------
1052 def : InstRW<[FalkorWr_FMOV],         (instregex "^FMOV(WS|XD|XDHigh)r$")>;
1053 def : InstRW<[FalkorWr_1GTOV_0cyc],   (instregex "^FMOV(S|D)i$")>; // imm fwd
1054 def : InstRW<[FalkorWr_1VTOG_1cyc],   (instregex "^FCVTZ(S|U)S(W|X)(D|S)ri$")>;
1055 def : InstRW<[FalkorWr_1VTOG_1cyc],   (instregex "^FCVTZ(S|U)(d|s)$")>;
1056 def : InstRW<[FalkorWr_1VTOG_1cyc],   (instregex "^FMOV(SW|DX|DXHigh)r$")>;
1057 def : InstRW<[FalkorWr_1VXVY_0cyc],   (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd
1058 // FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov wzr/xzr
1059 def : InstRW<[FalkorWr_2VXVY_0cyc],   (instrs FMOVD0, FMOVS0)>; // imm fwd
1060
1061 def : InstRW<[FalkorWr_1GTOV_4cyc],   (instregex "^(S|U)CVTF(S|U)(W|X)(D|S)ri$")>;
1062 def : InstRW<[FalkorWr_1VXVY_4cyc],   (instregex "^(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
1063
1064 def : InstRW<[FalkorWr_2VXVY_4cyc],   (instregex "^(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>;
1065
1066 // Load Instructions
1067 // -----------------------------------------------------------------------------
1068 def : InstRW<[FalkorWr_1ST_0cyc],     (instrs PRFMui, PRFMl)>;
1069 def : InstRW<[FalkorWr_1ST_0cyc],     (instrs PRFUMi)>;
1070 def : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc],
1071                                       (instregex "^LDNP(W|X)i$")>;
1072 def : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc],
1073                                       (instregex "^LDP(W|X)i$")>;
1074 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc, FalkorWr_none_3cyc],
1075                                       (instregex "^LDP(W|X)(post|pre)$")>;
1076 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDR(BB|HH|W|X)ui$")>;
1077 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_3cyc],
1078                                       (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
1079 def : InstRW<[FalkorWr_LDRro],        (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>;
1080 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDR(W|X)l$")>;
1081 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDTR(B|H|W|X)i$")>;
1082 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^LDUR(BB|HH|W|X)i$")>;
1083 def : InstRW<[FalkorWr_PRFMro],       (instregex "^PRFMro(W|X)$")>;
1084 def : InstRW<[FalkorWr_1LD_4cyc, FalkorWr_none_4cyc],
1085                                       (instrs LDPSWi)>;
1086 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_4cyc, FalkorWr_none_4cyc],
1087                                       (instregex "^LDPSW(post|pre)$")>;
1088 def : InstRW<[FalkorWr_1LD_4cyc],     (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1089 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1LD_4cyc],
1090                                       (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1091 def : InstRW<[FalkorWr_LDRSro],       (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1092 def : InstRW<[FalkorWr_1LD_4cyc],     (instrs LDRSWl)>;
1093 def : InstRW<[FalkorWr_1LD_4cyc],     (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1094 def : InstRW<[FalkorWr_1LD_4cyc],     (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
1095
1096 // Miscellaneous Data-Processing Instructions
1097 // -----------------------------------------------------------------------------
1098 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^(S|U)?BFM(W|X)ri$")>;
1099 def : InstRW<[FalkorWr_1X_2cyc],      (instregex "^CRC32.*$")>;
1100 def : InstRW<[FalkorWr_1XYZ_2cyc],    (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
1101 def : InstRW<[FalkorWr_2XYZ_2cyc],    (instregex "^EXTR(W|X)rri$")>;
1102
1103 // Divide and Multiply Instructions
1104 // -----------------------------------------------------------------------------
1105 def : InstRW<[FalkorWr_IMUL64_1X_4cyc, ReadDefault, ReadDefault, FalkorReadIMA64],
1106                                         (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;
1107 def : InstRW<[FalkorWr_IMUL32_1X_2cyc, ReadDefault, ReadDefault, FalkorReadIMA32],
1108                                         (instregex "^M(ADD|SUB)Wrrr$")>;
1109
1110 def : InstRW<[FalkorWr_IMUL64_1X_5cyc], (instregex "^(S|U)MULHrr$")>;
1111 def : InstRW<[FalkorWr_IMUL64_1X_5cyc, ReadDefault, ReadDefault, FalkorReadIMA64],
1112                                         (instregex "^M(ADD|SUB)Xrrr$")>;
1113
1114 def : InstRW<[FalkorWr_1X_1Z_8cyc],     (instregex "^(S|U)DIVWr$")>;
1115 def : InstRW<[FalkorWr_1X_1Z_16cyc],    (instregex "^(S|U)DIVXr$")>;
1116
1117 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc],
1118                                         (instregex "^(S|U)MULLv.*$")>;
1119 def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA],
1120                                         (instregex "^(S|U)(MLAL|MLSL)v.*$")>;
1121
1122 // Move and Shift Instructions
1123 // -----------------------------------------------------------------------------
1124 def : InstRW<[FalkorWr_1XYZ_1cyc],    (instregex "^(LSLV|LSRV|ASRV|RORV)(W|X)r$")>;
1125 def : InstRW<[FalkorWr_1XYZ_0cyc],    (instregex "^MOVK(W|X)i$")>; // imm fwd
1126 def : InstRW<[FalkorWr_1XYZB_0cyc],   (instregex "^ADRP?$")>; // imm fwd
1127 def : InstRW<[FalkorWr_1XYZB_0cyc],   (instregex "^MOVN(W|X)i$")>; // imm fwd
1128 def : InstRW<[FalkorWr_MOVZ],         (instregex "^MOVZ(W|X)i$")>;
1129 def : InstRW<[FalkorWr_1XYZ_0cyc],    (instrs MOVi32imm, MOVi64imm)>; // imm fwd (approximation)
1130 def : InstRW<[WriteSequence<[FalkorWr_1XYZ_1cyc, FalkorWr_1XYZ_1cyc]>],
1131                                       (instrs MOVaddr, MOVaddrBA, MOVaddrCP, MOVaddrEXT, MOVaddrJT, MOVaddrTLS)>;
1132 def : InstRW<[WriteSequence<[FalkorWr_1LD_3cyc, FalkorWr_1XYZ_1cyc]>],
1133                                       (instrs LOADgot)>;
1134
1135 // Other Instructions
1136 // -----------------------------------------------------------------------------
1137 def : InstRW<[FalkorWr_1LD_0cyc],     (instrs CLREX, DMB, DSB)>;
1138 def : InstRW<[FalkorWr_1none_0cyc],   (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, SVC)>;
1139 def : InstRW<[FalkorWr_1ST_0cyc],     (instrs SYSxt, SYSLxt)>;
1140 def : InstRW<[FalkorWr_1Z_0cyc],      (instrs MSRpstateImm1, MSRpstateImm4)>;
1141
1142 def : InstRW<[FalkorWr_1LD_3cyc],     (instregex "^(LDAR(B|H|W|X)|LDAXP(W|X)|LDAXR(B|H|W|X)|LDXP(W|X)|LDXR(B|H|W|X))$")>;
1143 def : InstRW<[FalkorWr_1LD_3cyc],     (instrs MRS, MOVbaseTLS)>;
1144
1145 def : InstRW<[FalkorWr_1LD_1Z_3cyc],  (instrs DRPS)>;
1146
1147 def : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs MSR)>;
1148 def : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs STNPWi, STNPXi)>;
1149 def : InstRW<[FalkorWr_2LD_1Z_3cyc],  (instrs ERET)>;
1150
1151 def : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDC.*$")>;
1152 def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STLR(B|H|W|X)$")>;
1153 def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXP(W|X)$")>;
1154 def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXR(B|H|W|X)$")>;
1155
1156 def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc], (instregex "^STLXP(W|X)$")>;
1157 def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc], (instregex "^STLXR(B|H|W|X)$")>;
1158
1159 // Store Instructions
1160 // -----------------------------------------------------------------------------
1161 def : InstRW<[FalkorWr_1SD_1ST_0cyc],     (instregex "^STP(W|X)i$")>;
1162 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1SD_1ST_0cyc],
1163                                           (instregex "^STP(W|X)(post|pre)$")>;
1164 def : InstRW<[FalkorWr_1SD_1ST_0cyc],     (instregex "^STR(BB|HH|W|X)ui$")>;
1165 def : InstRW<[FalkorWr_none_1cyc, FalkorWr_1SD_1ST_0cyc],
1166                                           (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
1167 def : InstRW<[FalkorWr_STRro],            (instregex "^STR(BB|HH|W|X)ro(W|X)$")>;
1168 def : InstRW<[FalkorWr_1SD_1ST_0cyc],     (instregex "^STTR(B|H|W|X)i$")>;
1169 def : InstRW<[FalkorWr_1SD_1ST_0cyc],     (instregex "^STUR(BB|HH|W|X)i$")>;
1170