1 //=- AArch64SchedKryoDetails.td - QC Kryo Scheduling Defs ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the uop and latency details for the machine model for the
11 // Qualcomm Kryo subtarget.
13 //===----------------------------------------------------------------------===//
15 def KryoWrite_3cyc_X_noRSV_138ln :
16 SchedWriteRes<[KryoUnitX]> {
17 let Latency = 3; let NumMicroOps = 2;
19 def : InstRW<[KryoWrite_3cyc_X_noRSV_138ln],
20 (instregex "(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)")>;
22 def KryoWrite_3cyc_X_X_139ln :
23 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
24 let Latency = 3; let NumMicroOps = 2;
26 def : InstRW<[KryoWrite_3cyc_X_X_139ln],
27 (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;
29 def KryoWrite_4cyc_XY_XY_noRSV_172ln :
30 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
31 let Latency = 4; let NumMicroOps = 3;
33 def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_172ln],
34 (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;
35 def KryoWrite_4cyc_XY_XY_XY_XY_178ln :
36 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {
37 let Latency = 4; let NumMicroOps = 4;
39 def : InstRW<[KryoWrite_4cyc_XY_XY_XY_XY_178ln],
40 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
41 def KryoWrite_3cyc_XY_XY_XY_XY_177ln :
42 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {
43 let Latency = 3; let NumMicroOps = 4;
45 def : InstRW<[KryoWrite_3cyc_XY_XY_XY_XY_177ln],
46 (instregex "(S|U)ABALv.*")>;
47 def KryoWrite_3cyc_XY_XY_166ln :
48 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
49 let Latency = 3; let NumMicroOps = 2;
51 def : InstRW<[KryoWrite_3cyc_XY_XY_166ln],
52 (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;
53 def KryoWrite_3cyc_XY_noRSV_159ln :
54 SchedWriteRes<[KryoUnitXY]> {
55 let Latency = 3; let NumMicroOps = 2;
57 def : InstRW<[KryoWrite_3cyc_XY_noRSV_159ln],
58 (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;
59 def KryoWrite_3cyc_XY_XY_165ln :
60 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
61 let Latency = 3; let NumMicroOps = 2;
63 def : InstRW<[KryoWrite_3cyc_XY_XY_165ln],
64 (instregex "(S|U)ABDLv.*")>;
65 def KryoWrite_3cyc_X_noRSV_154ln :
66 SchedWriteRes<[KryoUnitX]> {
67 let Latency = 3; let NumMicroOps = 2;
69 def : InstRW<[KryoWrite_3cyc_X_noRSV_154ln],
70 (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;
71 def KryoWrite_3cyc_X_X_155ln :
72 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
73 let Latency = 3; let NumMicroOps = 2;
75 def : InstRW<[KryoWrite_3cyc_X_X_155ln],
76 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
77 def KryoWrite_2cyc_XY_XY_151ln :
78 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
79 let Latency = 2; let NumMicroOps = 2;
81 def : InstRW<[KryoWrite_2cyc_XY_XY_151ln],
82 (instregex "(S|U)(ADD|SUB)Lv.*")>;
83 def KryoWrite_2cyc_XY_noRSV_148ln :
84 SchedWriteRes<[KryoUnitXY]> {
85 let Latency = 2; let NumMicroOps = 2;
87 def : InstRW<[KryoWrite_2cyc_XY_noRSV_148ln],
88 (instregex "((S|U)ADDLP|ABS)(v2i32|v4i16|v8i8)(_v.*)?")>;
89 def KryoWrite_2cyc_XY_XY_150ln :
90 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
91 let Latency = 2; let NumMicroOps = 2;
93 def : InstRW<[KryoWrite_2cyc_XY_XY_150ln],
94 (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;
95 def KryoWrite_3cyc_XY_XY_XY_noRSV_179ln :
96 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> {
97 let Latency = 3; let NumMicroOps = 4;
99 def : InstRW<[KryoWrite_3cyc_XY_XY_XY_noRSV_179ln],
100 (instrs SADDLVv4i32v, UADDLVv4i32v)>;
101 def KryoWrite_5cyc_XY_XY_XY_noRSV_180ln :
102 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> {
103 let Latency = 5; let NumMicroOps = 4;
105 def : InstRW<[KryoWrite_5cyc_XY_XY_XY_noRSV_180ln],
106 (instrs SADDLVv8i16v, UADDLVv8i16v)>;
107 def KryoWrite_6cyc_XY_XY_X_noRSV_181ln :
108 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX]> {
109 let Latency = 6; let NumMicroOps = 4;
111 def : InstRW<[KryoWrite_6cyc_XY_XY_X_noRSV_181ln],
112 (instrs SADDLVv16i8v, UADDLVv16i8v)>;
113 def KryoWrite_3cyc_XY_noRSV_158ln :
114 SchedWriteRes<[KryoUnitXY]> {
115 let Latency = 3; let NumMicroOps = 2;
117 def : InstRW<[KryoWrite_3cyc_XY_noRSV_158ln],
118 (instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>;
119 def KryoWrite_4cyc_X_noRSV_169ln :
120 SchedWriteRes<[KryoUnitX]> {
121 let Latency = 4; let NumMicroOps = 2;
123 def : InstRW<[KryoWrite_4cyc_X_noRSV_169ln],
124 (instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>;
125 def KryoWrite_2cyc_XY_XY_XY_XY_176ln :
126 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {
127 let Latency = 2; let NumMicroOps = 4;
129 def : InstRW<[KryoWrite_2cyc_XY_XY_XY_XY_176ln],
130 (instregex "(S|U)(ADDW|SUBW)v.*")>;
131 def KryoWrite_4cyc_X_noRSV_40ln :
132 SchedWriteRes<[KryoUnitX]> {
133 let Latency = 4; let NumMicroOps = 2;
135 def : InstRW<[KryoWrite_4cyc_X_noRSV_40ln],
136 (instregex "(S|U)CVTFS(W|X)(D|S)ri")>;
137 def KryoWrite_4cyc_X_noRSV_97ln :
138 SchedWriteRes<[KryoUnitX]> {
139 let Latency = 4; let NumMicroOps = 2;
141 def : InstRW<[KryoWrite_4cyc_X_noRSV_97ln],
142 (instregex "(S|U)CVTFU(W|X)(D|S)ri")>;
143 def KryoWrite_4cyc_X_noRSV_110ln :
144 SchedWriteRes<[KryoUnitX]> {
145 let Latency = 4; let NumMicroOps = 2;
147 def : InstRW<[KryoWrite_4cyc_X_noRSV_110ln],
148 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
149 def KryoWrite_4cyc_X_X_114ln :
150 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
151 let Latency = 4; let NumMicroOps = 2;
153 def : InstRW<[KryoWrite_4cyc_X_X_114ln],
154 (instregex "(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>;
155 def KryoWrite_1cyc_XA_Y_98ln :
156 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
157 let Latency = 1; let NumMicroOps = 2;
159 def : InstRW<[KryoWrite_1cyc_XA_Y_98ln],
160 (instregex "(S|U)DIV(_Int)?(W|X)r")>;
161 def KryoWrite_2cyc_XY_XY_152ln :
162 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
163 let Latency = 2; let NumMicroOps = 2;
165 def : InstRW<[KryoWrite_2cyc_XY_XY_152ln],
166 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
167 def KryoWrite_2cyc_XY_noRSV_149ln :
168 SchedWriteRes<[KryoUnitXY]> {
169 let Latency = 2; let NumMicroOps = 2;
171 def : InstRW<[KryoWrite_2cyc_XY_noRSV_149ln],
172 (instregex "((S|U)H(ADD|SUB)|ADDP)(v8i8|v4i16|v2i32)")>;
173 def KryoWrite_4cyc_X_70ln :
174 SchedWriteRes<[KryoUnitX]> {
175 let Latency = 4; let NumMicroOps = 1;
177 def : InstRW<[KryoWrite_4cyc_X_70ln],
178 (instregex "(S|U)(MADDL|MSUBL)rrr")>;
179 def KryoWrite_4cyc_X_X_191ln :
180 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
181 let Latency = 4; let NumMicroOps = 2;
183 def : InstRW<[KryoWrite_4cyc_X_X_191ln],
184 (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;
185 def KryoWrite_1cyc_XY_195ln :
186 SchedWriteRes<[KryoUnitXY]> {
187 let Latency = 1; let NumMicroOps = 1;
189 def : InstRW<[KryoWrite_1cyc_XY_195ln],
190 (instregex "(S|U)MOVv.*")>;
191 def KryoWrite_5cyc_X_71ln :
192 SchedWriteRes<[KryoUnitX]> {
193 let Latency = 5; let NumMicroOps = 1;
195 def : InstRW<[KryoWrite_5cyc_X_71ln],
196 (instrs SMULHrr, UMULHrr)>;
197 def KryoWrite_3cyc_XY_noRSV_186ln :
198 SchedWriteRes<[KryoUnitXY]> {
199 let Latency = 3; let NumMicroOps = 2;
201 def : InstRW<[KryoWrite_3cyc_XY_noRSV_186ln],
202 (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;
203 def KryoWrite_3cyc_XY_XY_187ln :
204 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
205 let Latency = 3; let NumMicroOps = 2;
207 def : InstRW<[KryoWrite_3cyc_XY_XY_187ln],
208 (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;
209 def KryoWrite_3cyc_XY_noRSV_69ln :
210 SchedWriteRes<[KryoUnitXY]> {
211 let Latency = 3; let NumMicroOps = 2;
213 def : InstRW<[KryoWrite_3cyc_XY_noRSV_69ln],
214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
215 def KryoWrite_3cyc_XY_noRSV_248ln :
216 SchedWriteRes<[KryoUnitXY]> {
217 let Latency = 3; let NumMicroOps = 2;
219 def : InstRW<[KryoWrite_3cyc_XY_noRSV_248ln],
220 (instregex "(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>;
221 def KryoWrite_3cyc_XY_XY_250ln :
222 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
223 let Latency = 3; let NumMicroOps = 2;
225 def : InstRW<[KryoWrite_3cyc_XY_XY_250ln],
226 (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
227 def KryoWrite_3cyc_XY_noRSV_246ln :
228 SchedWriteRes<[KryoUnitXY]> {
229 let Latency = 3; let NumMicroOps = 2;
231 def : InstRW<[KryoWrite_3cyc_XY_noRSV_246ln],
232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
233 def KryoWrite_3cyc_XY_XY_251ln :
234 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
235 let Latency = 3; let NumMicroOps = 2;
237 def : InstRW<[KryoWrite_3cyc_XY_XY_251ln],
238 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;
239 def KryoWrite_6cyc_XY_X_238ln :
240 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
241 let Latency = 6; let NumMicroOps = 2;
243 def : InstRW<[KryoWrite_6cyc_XY_X_238ln],
244 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v16i8|v8i16|v4i32)_shift$")>;
245 def KryoWrite_3cyc_XY_noRSV_249ln :
246 SchedWriteRes<[KryoUnitXY]> {
247 let Latency = 3; let NumMicroOps = 2;
249 def : InstRW<[KryoWrite_3cyc_XY_noRSV_249ln],
250 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(s|h|b)?")>;
251 def KryoWrite_6cyc_XY_X_noRSV_252ln :
252 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
253 let Latency = 6; let NumMicroOps = 3;
255 def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_252ln],
256 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v8i8|v4i16|v2i32)_shift?")>;
257 def KryoWrite_3cyc_XY_noRSV_161ln :
258 SchedWriteRes<[KryoUnitXY]> {
259 let Latency = 3; let NumMicroOps = 2;
261 def : InstRW<[KryoWrite_3cyc_XY_noRSV_161ln],
262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
263 def KryoWrite_3cyc_XY_noRSV_163ln :
264 SchedWriteRes<[KryoUnitXY]> {
265 let Latency = 3; let NumMicroOps = 2;
267 def : InstRW<[KryoWrite_3cyc_XY_noRSV_163ln],
268 (instregex "(S|U)QXTU?N(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)")>;
269 def KryoWrite_3cyc_XY_noRSV_162ln :
270 SchedWriteRes<[KryoUnitXY]> {
271 let Latency = 3; let NumMicroOps = 2;
273 def : InstRW<[KryoWrite_3cyc_XY_noRSV_162ln],
274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
275 def KryoWrite_3cyc_XY_noRSV_247ln :
276 SchedWriteRes<[KryoUnitXY]> {
277 let Latency = 3; let NumMicroOps = 2;
279 def : InstRW<[KryoWrite_3cyc_XY_noRSV_247ln],
280 (instregex "(S|U)RSHR(d|(v8i8|v4i16|v2i32)_shift)$")>;
281 def KryoWrite_2cyc_XY_noRSV_239ln :
282 SchedWriteRes<[KryoUnitXY]> {
283 let Latency = 2; let NumMicroOps = 2;
285 def : InstRW<[KryoWrite_2cyc_XY_noRSV_239ln],
286 (instregex "(S|U)SHL(d|v8i8|v4i16|v2i32|v1i64)$")>;
287 def KryoWrite_2cyc_XY_XY_243ln :
288 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
289 let Latency = 2; let NumMicroOps = 2;
291 def : InstRW<[KryoWrite_2cyc_XY_XY_243ln],
292 (instregex "(S|U)SHL(v16i8|v8i16|v4i32|v2i64)$")>;
293 def KryoWrite_2cyc_XY_XY_241ln :
294 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
295 let Latency = 2; let NumMicroOps = 2;
297 def : InstRW<[KryoWrite_2cyc_XY_XY_241ln],
298 (instregex "(S|U)?SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;
299 def KryoWrite_2cyc_XY_noRSV_240ln :
300 SchedWriteRes<[KryoUnitXY]> {
301 let Latency = 2; let NumMicroOps = 2;
303 def : InstRW<[KryoWrite_2cyc_XY_noRSV_240ln],
304 (instregex "((S|U)SHR|SHL)(d|(v8i8|v4i16|v2i32)_shift)$")>;
305 def KryoWrite_2cyc_XY_XY_242ln :
306 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
307 let Latency = 2; let NumMicroOps = 2;
309 def : InstRW<[KryoWrite_2cyc_XY_XY_242ln],
310 (instregex "((S|U)SHR|SHL)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
311 def KryoWrite_2cyc_XY_XY_183ln :
312 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
313 let Latency = 2; let NumMicroOps = 2;
315 def : InstRW<[KryoWrite_2cyc_XY_XY_183ln],
316 (instregex "(S|U)(MAX|MIN)P?(v16i8|v8i16|v4i32)")>;
317 def KryoWrite_2cyc_XY_noRSV_182ln :
318 SchedWriteRes<[KryoUnitXY]> {
319 let Latency = 2; let NumMicroOps = 2;
321 def : InstRW<[KryoWrite_2cyc_XY_noRSV_182ln],
322 (instregex "(S|U)(MAX|MIN)P?(v8i8|v4i16|v2i32)")>;
323 def KryoWrite_3cyc_XY_noRSV_184ln :
324 SchedWriteRes<[KryoUnitXY]> {
325 let Latency = 3; let NumMicroOps = 2;
327 def : InstRW<[KryoWrite_3cyc_XY_noRSV_184ln],
328 (instregex "(S|U)(MAX|MIN)V(v4i16v|v8i8v|v4i32)")>;
329 def KryoWrite_4cyc_X_noRSV_185ln :
330 SchedWriteRes<[KryoUnitX]> {
331 let Latency = 4; let NumMicroOps = 2;
333 def : InstRW<[KryoWrite_4cyc_X_noRSV_185ln],
334 (instregex "(S|U)(MAX|MIN)V(v16i8v|v8i16v)")>;
335 def KryoWrite_2cyc_XY_noRSV_67ln :
336 SchedWriteRes<[KryoUnitXY]> {
337 let Latency = 2; let NumMicroOps = 2;
339 def : InstRW<[KryoWrite_2cyc_XY_noRSV_67ln],
341 def KryoWrite_1cyc_XY_63ln :
342 SchedWriteRes<[KryoUnitXY]> {
343 let Latency = 1; let NumMicroOps = 1;
345 def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI],
346 (instregex "ADC.*")>;
347 def KryoWrite_1cyc_XY_63_1ln :
348 SchedWriteRes<[KryoUnitXY]> {
349 let Latency = 1; let NumMicroOps = 1;
351 def : InstRW<[KryoWrite_1cyc_XY_63_1ln],
352 (instregex "ADR.*")>;
353 def KryoWrite_1cyc_XY_62ln :
354 SchedWriteRes<[KryoUnitXY]> {
355 let Latency = 1; let NumMicroOps = 1;
357 def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI],
358 (instregex "ADDS?(W|X)ri")>;
359 def KryoWrite_2cyc_XY_XY_64ln :
360 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
361 let Latency = 2; let NumMicroOps = 2;
363 def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI],
364 (instregex "ADDS?(W|X)r(r|s|x)(64)?")>;
365 def KryoWrite_1cyc_XY_noRSV_65ln :
366 SchedWriteRes<[KryoUnitXY]> {
367 let Latency = 1; let NumMicroOps = 2;
369 def : InstRW<[KryoWrite_1cyc_XY_noRSV_65ln],
371 def KryoWrite_1cyc_XY_noRSV_144ln :
372 SchedWriteRes<[KryoUnitXY]> {
373 let Latency = 1; let NumMicroOps = 2;
375 def : InstRW<[KryoWrite_1cyc_XY_noRSV_144ln],
376 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
377 def KryoWrite_1cyc_XY_XY_146ln :
378 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
379 let Latency = 1; let NumMicroOps = 2;
381 def : InstRW<[KryoWrite_1cyc_XY_XY_146ln],
382 (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>;
383 def KryoWrite_4cyc_XY_X_noRSV_171ln :
384 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
385 let Latency = 4; let NumMicroOps = 3;
387 def : InstRW<[KryoWrite_4cyc_XY_X_noRSV_171ln],
388 (instregex "(ADD|SUB)HNv.*")>;
389 def KryoWrite_1cyc_XY_noRSV_66ln :
390 SchedWriteRes<[KryoUnitXY]> {
391 let Latency = 1; let NumMicroOps = 2;
393 def : InstRW<[KryoWrite_1cyc_XY_noRSV_66ln],
394 (instrs ADDPv2i64p)>;
395 def KryoWrite_2cyc_XY_XY_153ln :
396 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
397 let Latency = 2; let NumMicroOps = 2;
399 def : InstRW<[KryoWrite_2cyc_XY_XY_153ln],
400 (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>;
401 def KryoWrite_3cyc_XY_XY_noRSV_170ln :
402 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
403 let Latency = 3; let NumMicroOps = 3;
405 def : InstRW<[KryoWrite_3cyc_XY_XY_noRSV_170ln],
406 (instrs ADDVv4i32v)>;
407 def KryoWrite_4cyc_XY_XY_noRSV_173ln :
408 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
409 let Latency = 4; let NumMicroOps = 3;
411 def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_173ln],
412 (instrs ADDVv8i16v)>;
413 def KryoWrite_5cyc_XY_X_noRSV_174ln :
414 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
415 let Latency = 5; let NumMicroOps = 3;
417 def : InstRW<[KryoWrite_5cyc_XY_X_noRSV_174ln],
418 (instrs ADDVv16i8v)>;
419 def KryoWrite_3cyc_XY_XY_X_X_27ln :
420 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> {
421 let Latency = 3; let NumMicroOps = 4;
423 def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_27ln],
424 (instrs AESDrr, AESErr)>;
425 def KryoWrite_2cyc_X_X_22ln :
426 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
427 let Latency = 2; let NumMicroOps = 2;
429 def : InstRW<[KryoWrite_2cyc_X_X_22ln],
430 (instrs AESIMCrr, AESMCrr)>;
431 def KryoWrite_1cyc_XY_noRSV_76ln :
432 SchedWriteRes<[KryoUnitXY]> {
433 let Latency = 1; let NumMicroOps = 2;
435 def : InstRW<[KryoWrite_1cyc_XY_noRSV_76ln],
436 (instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")>;
437 def KryoWrite_1cyc_XY_XY_79ln :
438 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
439 let Latency = 1; let NumMicroOps = 2;
441 def : InstRW<[KryoWrite_1cyc_XY_XY_79ln],
442 (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
443 def KryoWrite_1cyc_X_72ln :
444 SchedWriteRes<[KryoUnitX]> {
445 let Latency = 1; let NumMicroOps = 1;
447 def : InstRW<[KryoWrite_1cyc_X_72ln],
448 (instregex "(S|U)?BFM.*")>;
449 def KryoWrite_1cyc_XY_noRSV_77ln :
450 SchedWriteRes<[KryoUnitXY]> {
451 let Latency = 1; let NumMicroOps = 2;
453 def : InstRW<[KryoWrite_1cyc_XY_noRSV_77ln],
454 (instregex "(BIC|ORR)S?Wri")>;
455 def KryoWrite_1cyc_XY_XY_78ln :
456 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
457 let Latency = 1; let NumMicroOps = 2;
459 def : InstRW<[KryoWrite_1cyc_XY_XY_78ln],
460 (instregex "(BIC|ORR)S?Xri")>;
461 def KryoWrite_1cyc_X_noRSV_74ln :
462 SchedWriteRes<[KryoUnitX]> {
463 let Latency = 1; let NumMicroOps = 2;
465 def : InstRW<[KryoWrite_1cyc_X_noRSV_74ln],
466 (instrs BIFv8i8, BITv8i8, BSLv8i8)>;
467 def KryoWrite_1cyc_X_X_75ln :
468 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
469 let Latency = 1; let NumMicroOps = 2;
471 def : InstRW<[KryoWrite_1cyc_X_X_75ln],
472 (instrs BIFv16i8, BITv16i8, BSLv16i8)>;
473 def KryoWrite_0cyc_noRSV_11ln :
475 let Latency = 0; let NumMicroOps = 1;
477 def : InstRW<[KryoWrite_0cyc_noRSV_11ln],
478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
479 def KryoWrite_0cyc_XY_16ln :
480 SchedWriteRes<[KryoUnitXY]> {
481 let Latency = 0; let NumMicroOps = 1;
483 def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI],
484 (instregex "(CCMN|CCMP)(W|X)i")>;
485 def KryoWrite_0cyc_XY_16_1ln :
486 SchedWriteRes<[KryoUnitXY]> {
487 let Latency = 0; let NumMicroOps = 1;
489 def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI],
490 (instregex "(CCMN|CCMP)(W|X)r")>;
491 def KryoWrite_2cyc_XY_3ln :
492 SchedWriteRes<[KryoUnitXY]> {
493 let Latency = 2; let NumMicroOps = 1;
495 def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI],
496 (instregex "(CLS|CLZ)(W|X)r")>;
497 def KryoWrite_2cyc_XY_noRSV_7ln :
498 SchedWriteRes<[KryoUnitXY]> {
499 let Latency = 2; let NumMicroOps = 2;
501 def : InstRW<[KryoWrite_2cyc_XY_noRSV_7ln],
502 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
503 def KryoWrite_2cyc_XY_XY_8ln :
504 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
505 let Latency = 2; let NumMicroOps = 2;
507 def : InstRW<[KryoWrite_2cyc_XY_XY_8ln],
508 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
509 def KryoWrite_2cyc_XY_noRSV_80ln :
510 SchedWriteRes<[KryoUnitXY]> {
511 let Latency = 2; let NumMicroOps = 2;
513 def : InstRW<[KryoWrite_2cyc_XY_noRSV_80ln],
514 (instregex "CM(EQ|GE|HS|GT|HI|TST)(v8i8|v4i16|v2i32|v1i64)$")>;
515 def KryoWrite_2cyc_XY_XY_83ln :
516 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
517 let Latency = 2; let NumMicroOps = 2;
519 def : InstRW<[KryoWrite_2cyc_XY_XY_83ln],
520 (instregex "CM(EQ|GE|HS|GT|HI|TST)(v16i8|v8i16|v4i32|v2i64)$")>;
521 def KryoWrite_2cyc_XY_noRSV_81ln :
522 SchedWriteRes<[KryoUnitXY]> {
523 let Latency = 2; let NumMicroOps = 2;
525 def : InstRW<[KryoWrite_2cyc_XY_noRSV_81ln],
526 (instregex "CM(EQ|LE|GE|GT|LT)(v8i8|v4i16|v2i32|v1i64)rz$")>;
527 def KryoWrite_2cyc_XY_XY_82ln :
528 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
529 let Latency = 2; let NumMicroOps = 2;
531 def : InstRW<[KryoWrite_2cyc_XY_XY_82ln],
532 (instregex "CM(EQ|LE|GE|GT|LT)(v16i8|v8i16|v4i32|v2i64)rz$")>;
533 def KryoWrite_3cyc_XY_4ln :
534 SchedWriteRes<[KryoUnitXY]> {
535 let Latency = 3; let NumMicroOps = 1;
537 def : InstRW<[KryoWrite_3cyc_XY_4ln, ReadI, ReadISReg],
538 (instregex "CRC32.*")>;
539 def KryoWrite_1cyc_XY_20ln :
540 SchedWriteRes<[KryoUnitXY]> {
541 let Latency = 1; let NumMicroOps = 1;
543 def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI],
544 (instregex "CSEL(W|X)r")>;
545 def KryoWrite_1cyc_X_17ln :
546 SchedWriteRes<[KryoUnitX]> {
547 let Latency = 1; let NumMicroOps = 1;
549 def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI],
550 (instregex "(CSINC|CSNEG)(W|X)r")>;
551 def KryoWrite_1cyc_XY_18ln :
552 SchedWriteRes<[KryoUnitXY]> {
553 let Latency = 1; let NumMicroOps = 1;
555 def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI],
556 (instregex "(CSINV)(W|X)r")>;
557 def KryoWrite_3cyc_LS_X_13ln :
558 SchedWriteRes<[KryoUnitLS, KryoUnitX]> {
559 let Latency = 3; let NumMicroOps = 2;
561 def : InstRW<[KryoWrite_3cyc_LS_X_13ln],
563 def KryoWrite_0cyc_LS_10ln :
564 SchedWriteRes<[KryoUnitLS]> {
565 let Latency = 0; let NumMicroOps = 1;
567 def : InstRW<[KryoWrite_0cyc_LS_10ln],
568 (instrs DSB, DMB, CLREX)>;
569 def KryoWrite_1cyc_X_noRSV_196ln :
570 SchedWriteRes<[KryoUnitX]> {
571 let Latency = 1; let NumMicroOps = 2;
573 def : InstRW<[KryoWrite_1cyc_X_noRSV_196ln],
574 (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>;
575 def KryoWrite_1cyc_X_X_197ln :
576 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
577 let Latency = 1; let NumMicroOps = 2;
579 def : InstRW<[KryoWrite_1cyc_X_X_197ln],
580 (instregex "DUP(v16i8|v8i16|v4i32|v2i64)(gpr|lane)")>;
581 def KryoWrite_3cyc_LS_LS_X_15ln :
582 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX]> {
583 let Latency = 3; let NumMicroOps = 3;
585 def : InstRW<[KryoWrite_3cyc_LS_LS_X_15ln],
587 def KryoWrite_1cyc_X_noRSV_207ln :
588 SchedWriteRes<[KryoUnitX]> {
589 let Latency = 1; let NumMicroOps = 2;
591 def : InstRW<[KryoWrite_1cyc_X_noRSV_207ln],
593 def KryoWrite_1cyc_X_X_212ln :
594 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
595 let Latency = 1; let NumMicroOps = 2;
597 def : InstRW<[KryoWrite_1cyc_X_X_212ln],
599 def KryoWrite_2cyc_XY_X_136ln :
600 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
601 let Latency = 2; let NumMicroOps = 2;
603 def : InstRW<[KryoWrite_2cyc_XY_X_136ln],
604 (instrs EXTRWrri, EXTRXrri)>;
605 def KryoWrite_2cyc_XY_noRSV_35ln :
606 SchedWriteRes<[KryoUnitXY]> {
607 let Latency = 2; let NumMicroOps = 2;
609 def : InstRW<[KryoWrite_2cyc_XY_noRSV_35ln],
610 (instregex "F(MAX|MIN)(NM)?P?(D|S)rr")>;
611 def KryoWrite_2cyc_XY_XY_106ln :
612 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
613 let Latency = 2; let NumMicroOps = 2;
615 def : InstRW<[KryoWrite_2cyc_XY_XY_106ln],
616 (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2i64p|v2f64|v4f32)")>;
617 def KryoWrite_2cyc_XY_noRSV_104ln :
618 SchedWriteRes<[KryoUnitXY]> {
619 let Latency = 2; let NumMicroOps = 2;
621 def : InstRW<[KryoWrite_2cyc_XY_noRSV_104ln],
622 (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f32|v2i32p)")>;
623 def KryoWrite_3cyc_XY_noRSV_107ln :
624 SchedWriteRes<[KryoUnitXY]> {
625 let Latency = 3; let NumMicroOps = 2;
627 def : InstRW<[KryoWrite_3cyc_XY_noRSV_107ln],
628 (instregex "F(MAX|MIN)(NM)?Vv4i32v")>;
629 def KryoWrite_3cyc_XY_noRSV_101ln :
630 SchedWriteRes<[KryoUnitXY]> {
631 let Latency = 3; let NumMicroOps = 2;
633 def : InstRW<[KryoWrite_3cyc_XY_noRSV_101ln],
634 (instregex "FABD(32|64|v2f32)")>;
635 def KryoWrite_3cyc_XY_XY_103ln :
636 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
637 let Latency = 3; let NumMicroOps = 2;
639 def : InstRW<[KryoWrite_3cyc_XY_XY_103ln],
640 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
641 def KryoWrite_1cyc_XY_noRSV_48ln :
642 SchedWriteRes<[KryoUnitXY]> {
643 let Latency = 1; let NumMicroOps = 2;
645 def : InstRW<[KryoWrite_1cyc_XY_noRSV_48ln],
646 (instregex "F(ABS|NEG)(D|S)r")>;
647 def KryoWrite_1cyc_XY_noRSV_124ln :
648 SchedWriteRes<[KryoUnitXY]> {
649 let Latency = 1; let NumMicroOps = 2;
651 def : InstRW<[KryoWrite_1cyc_XY_noRSV_124ln],
652 (instregex "F(ABS|NEG)v2f32")>;
653 def KryoWrite_1cyc_XY_XY_125ln :
654 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
655 let Latency = 1; let NumMicroOps = 2;
657 def : InstRW<[KryoWrite_1cyc_XY_XY_125ln],
658 (instregex "F(ABS|NEG)(v2f64|v4f32)")>;
659 def KryoWrite_2cyc_XY_noRSV_33ln :
660 SchedWriteRes<[KryoUnitXY]> {
661 let Latency = 2; let NumMicroOps = 2;
663 def : InstRW<[KryoWrite_2cyc_XY_noRSV_33ln],
664 (instregex "(FAC(GE|GT)|FCM(EQ|GE|GT))(32|64)")>;
665 def KryoWrite_3cyc_XY_noRSV_30ln :
666 SchedWriteRes<[KryoUnitXY]> {
667 let Latency = 3; let NumMicroOps = 2;
669 def : InstRW<[KryoWrite_3cyc_XY_noRSV_30ln],
670 (instregex "(FADD|FSUB)(D|S)rr")>;
671 def KryoWrite_3cyc_XY_noRSV_100ln :
672 SchedWriteRes<[KryoUnitXY]> {
673 let Latency = 3; let NumMicroOps = 2;
675 def : InstRW<[KryoWrite_3cyc_XY_noRSV_100ln],
676 (instregex "(FADD|FSUB|FADDP)v2f32")>;
677 def KryoWrite_3cyc_XY_noRSV_29ln :
678 SchedWriteRes<[KryoUnitXY]> {
679 let Latency = 3; let NumMicroOps = 2;
681 def : InstRW<[KryoWrite_3cyc_XY_noRSV_29ln],
682 (instregex "FADDP(v2i32p|v2i64p)")>;
683 def KryoWrite_0cyc_XY_31ln :
684 SchedWriteRes<[KryoUnitXY]> {
685 let Latency = 0; let NumMicroOps = 1;
687 def : InstRW<[KryoWrite_0cyc_XY_31ln],
688 (instregex "FCCMPE?(D|S)rr")>;
689 def KryoWrite_2cyc_XY_noRSV_34ln :
690 SchedWriteRes<[KryoUnitXY]> {
691 let Latency = 2; let NumMicroOps = 2;
693 def : InstRW<[KryoWrite_2cyc_XY_noRSV_34ln],
694 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
695 def KryoWrite_2cyc_XY_XY_36ln :
696 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
697 let Latency = 2; let NumMicroOps = 2;
699 def : InstRW<[KryoWrite_2cyc_XY_XY_36ln],
700 (instregex "FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz")>;
701 def KryoWrite_2cyc_XY_noRSV_105ln :
702 SchedWriteRes<[KryoUnitXY]> {
703 let Latency = 2; let NumMicroOps = 2;
705 def : InstRW<[KryoWrite_2cyc_XY_noRSV_105ln],
706 (instregex "FCM(EQ|LE|GE|GT|LT)v2i32rz")>;
707 def KryoWrite_0cyc_XY_32ln :
708 SchedWriteRes<[KryoUnitXY]> {
709 let Latency = 0; let NumMicroOps = 1;
711 def : InstRW<[KryoWrite_0cyc_XY_32ln],
712 (instregex "FCMPE?(D|S)r(r|i)")>;
713 def KryoWrite_1cyc_XY_noRSV_49ln :
714 SchedWriteRes<[KryoUnitXY]> {
715 let Latency = 1; let NumMicroOps = 2;
717 def : InstRW<[KryoWrite_1cyc_XY_noRSV_49ln],
718 (instrs FCSELDrrr, FCSELSrrr)>;
719 def KryoWrite_4cyc_X_noRSV_41ln :
720 SchedWriteRes<[KryoUnitX]> {
721 let Latency = 4; let NumMicroOps = 2;
723 def : InstRW<[KryoWrite_4cyc_X_noRSV_41ln],
724 (instrs FCVTDHr, FCVTDSr, FCVTHDr, FCVTHSr, FCVTSDr, FCVTSHr)>;
725 def KryoWrite_4cyc_X_38ln :
726 SchedWriteRes<[KryoUnitX]> {
727 let Latency = 4; let NumMicroOps = 1;
729 def : InstRW<[KryoWrite_4cyc_X_38ln],
730 (instregex "FCVT(((A|N|M|P)(S|U)(S|U)|Z(S|U)_Int(S|U))(W|X)(D|S)ri?|Z(S|U)(d|s))$")>;
731 def KryoWrite_4cyc_X_noRSV_113ln :
732 SchedWriteRes<[KryoUnitX]> {
733 let Latency = 4; let NumMicroOps = 2;
735 def : InstRW<[KryoWrite_4cyc_X_noRSV_113ln],
736 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
737 def KryoWrite_4cyc_X_X_117ln :
738 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
739 let Latency = 4; let NumMicroOps = 2;
741 def : InstRW<[KryoWrite_4cyc_X_X_117ln],
742 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v4f32|v2f64)$")>;
743 def KryoWrite_5cyc_X_X_XY_noRSV_119ln :
744 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitXY]> {
745 let Latency = 5; let NumMicroOps = 4;
747 def : InstRW<[KryoWrite_5cyc_X_X_XY_noRSV_119ln],
748 (instregex "FCVTX?N(v2f32|v4f32|v2i32|v4i16|v4i32|v8i16)$")>;
749 def KryoWrite_4cyc_X_X_116ln :
750 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
751 let Latency = 4; let NumMicroOps = 2;
753 def : InstRW<[KryoWrite_4cyc_X_X_116ln],
754 (instregex "FCVTL(v2i32|v4i16|v4i32|v8i16)$")>;
755 def KryoWrite_4cyc_X_noRSV_112ln :
756 SchedWriteRes<[KryoUnitX]> {
757 let Latency = 4; let NumMicroOps = 2;
759 def : InstRW<[KryoWrite_4cyc_X_noRSV_112ln],
760 (instrs FCVTXNv1i64)>;
761 def KryoWrite_4cyc_X_37ln :
762 SchedWriteRes<[KryoUnitX]> {
763 let Latency = 4; let NumMicroOps = 1;
765 def : InstRW<[KryoWrite_4cyc_X_37ln],
766 (instregex "FCVTZ(S|U)(S|U)(W|X)(D|S)ri?$")>;
767 def KryoWrite_4cyc_X_noRSV_111ln :
768 SchedWriteRes<[KryoUnitX]> {
769 let Latency = 4; let NumMicroOps = 2;
771 def : InstRW<[KryoWrite_4cyc_X_noRSV_111ln],
772 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
773 def KryoWrite_4cyc_X_X_115ln :
774 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
775 let Latency = 4; let NumMicroOps = 2;
777 def : InstRW<[KryoWrite_4cyc_X_X_115ln],
778 (instregex "FCVTZ(S|U)(v2f64|v4f32|(v2i64|v4i32)(_shift)?)$")>;
779 def KryoWrite_10cyc_XA_Y_noRSV_43ln :
780 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
781 let Latency = 10; let NumMicroOps = 3;
783 def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_43ln],
785 def KryoWrite_14cyc_XA_Y_noRSV_43ln :
786 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
787 let Latency = 14; let NumMicroOps = 3;
789 def : InstRW<[KryoWrite_14cyc_XA_Y_noRSV_43ln],
791 def KryoWrite_10cyc_XA_Y_noRSV_121ln :
792 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
793 let Latency = 10; let NumMicroOps = 3;
795 def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_121ln],
797 def KryoWrite_14cyc_XA_Y_XA_Y_123ln :
798 SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {
799 let Latency = 14; let NumMicroOps = 4;
801 def : InstRW<[KryoWrite_14cyc_XA_Y_XA_Y_123ln],
802 (instrs FDIVv2f64, FDIVv4f32)>;
803 def KryoWrite_5cyc_X_noRSV_55ln :
804 SchedWriteRes<[KryoUnitX]> {
805 let Latency = 5; let NumMicroOps = 2;
807 def : InstRW<[KryoWrite_5cyc_X_noRSV_55ln],
808 (instregex "FN?M(ADD|SUB)Srrr")>;
809 def KryoWrite_6cyc_X_noRSV_57ln :
810 SchedWriteRes<[KryoUnitX]> {
811 let Latency = 6; let NumMicroOps = 2;
813 def : InstRW<[KryoWrite_6cyc_X_noRSV_57ln],
814 (instregex "FN?M(ADD|SUB)Drrr")>;
815 def KryoWrite_5cyc_X_noRSV_51ln :
816 SchedWriteRes<[KryoUnitX]> {
817 let Latency = 5; let NumMicroOps = 2;
819 def : InstRW<[KryoWrite_5cyc_X_noRSV_51ln],
820 (instrs FMLAv2f32, FMLSv2f32, FMLAv1i32_indexed, FMLSv1i32_indexed)>;
821 def KryoWrite_5cyc_X_X_56ln :
822 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
823 let Latency = 5; let NumMicroOps = 2;
825 def : InstRW<[KryoWrite_5cyc_X_X_56ln],
826 (instrs FMLAv4f32, FMLSv4f32)>;
827 def KryoWrite_6cyc_X_X_61ln :
828 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
829 let Latency = 6; let NumMicroOps = 2;
831 def : InstRW<[KryoWrite_6cyc_X_X_61ln],
832 (instrs FMLAv2f64, FMLSv2f64)>;
833 def KryoWrite_5cyc_X_noRSV_128ln :
834 SchedWriteRes<[KryoUnitX]> {
835 let Latency = 5; let NumMicroOps = 2;
837 def : InstRW<[KryoWrite_5cyc_X_noRSV_128ln],
838 (instrs FMLAv2i32_indexed, FMLSv2i32_indexed)>;
839 def KryoWrite_5cyc_X_X_131ln :
840 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
841 let Latency = 5; let NumMicroOps = 2;
843 def : InstRW<[KryoWrite_5cyc_X_X_131ln],
844 (instrs FMLAv4i32_indexed, FMLSv4i32_indexed)>;
845 def KryoWrite_6cyc_X_X_134ln :
846 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
847 let Latency = 6; let NumMicroOps = 2;
849 def : InstRW<[KryoWrite_6cyc_X_X_134ln],
850 (instrs FMLAv2i64_indexed, FMLSv2i64_indexed)>;
851 def KryoWrite_6cyc_X_noRSV_60ln :
852 SchedWriteRes<[KryoUnitX]> {
853 let Latency = 6; let NumMicroOps = 2;
855 def : InstRW<[KryoWrite_6cyc_X_noRSV_60ln],
856 (instrs FMLAv1i64_indexed, FMLSv1i64_indexed, FMULv1i64_indexed, FMULXv1i64_indexed)>;
857 def KryoWrite_1cyc_XY_45ln :
858 SchedWriteRes<[KryoUnitXY]> {
859 let Latency = 1; let NumMicroOps = 1;
861 def : InstRW<[KryoWrite_1cyc_XY_45ln],
862 (instregex "FMOV(XDHigh|DXHigh|DX)r")>;
863 def KryoWrite_1cyc_XY_noRSV_47ln :
864 SchedWriteRes<[KryoUnitXY]> {
865 let Latency = 1; let NumMicroOps = 2;
867 def : InstRW<[KryoWrite_1cyc_XY_noRSV_47ln],
868 (instregex "FMOV(Di|Dr|Si|Sr|SWr|WSr|XDr|v.*_ns)")>;
869 def KryoWrite_5cyc_X_noRSV_53ln :
870 SchedWriteRes<[KryoUnitX]> {
871 let Latency = 5; let NumMicroOps = 2;
873 def : InstRW<[KryoWrite_5cyc_X_noRSV_53ln],
874 (instrs FMULv1i32_indexed, FMULXv1i32_indexed)>;
875 def KryoWrite_5cyc_X_noRSV_127ln :
876 SchedWriteRes<[KryoUnitX]> {
877 let Latency = 5; let NumMicroOps = 2;
879 def : InstRW<[KryoWrite_5cyc_X_noRSV_127ln],
880 (instrs FMULv2f32, FMULXv2f32, FMULv2i32_indexed, FMULXv2i32_indexed)>;
881 def KryoWrite_5cyc_X_X_130ln :
882 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
883 let Latency = 5; let NumMicroOps = 2;
885 def : InstRW<[KryoWrite_5cyc_X_X_130ln],
886 (instrs FMULv4f32, FMULXv4f32, FMULv4i32_indexed, FMULXv4i32_indexed)>;
887 def KryoWrite_6cyc_X_X_133ln :
888 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
889 let Latency = 6; let NumMicroOps = 2;
891 def : InstRW<[KryoWrite_6cyc_X_X_133ln],
892 (instrs FMULv2f64, FMULXv2f64, FMULv2i64_indexed, FMULXv2i64_indexed)>;
893 def KryoWrite_5cyc_X_noRSV_54ln :
894 SchedWriteRes<[KryoUnitX]> {
895 let Latency = 5; let NumMicroOps = 2;
897 def : InstRW<[KryoWrite_5cyc_X_noRSV_54ln],
898 (instrs FMULSrr, FNMULSrr, FMULX32)>;
899 def KryoWrite_6cyc_X_noRSV_59ln :
900 SchedWriteRes<[KryoUnitX]> {
901 let Latency = 6; let NumMicroOps = 2;
903 def : InstRW<[KryoWrite_6cyc_X_noRSV_59ln],
904 (instrs FMULDrr, FNMULDrr, FMULX64)>;
905 def KryoWrite_3cyc_XY_noRSV_28ln :
906 SchedWriteRes<[KryoUnitXY]> {
907 let Latency = 3; let NumMicroOps = 2;
909 def : InstRW<[KryoWrite_3cyc_XY_noRSV_28ln],
910 (instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64 )>;
911 def KryoWrite_3cyc_XY_noRSV_99ln :
912 SchedWriteRes<[KryoUnitXY]> {
913 let Latency = 3; let NumMicroOps = 2;
915 def : InstRW<[KryoWrite_3cyc_XY_noRSV_99ln],
916 (instrs FRECPEv2f32, FRSQRTEv2f32)>;
917 def KryoWrite_3cyc_XY_XY_102ln :
918 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
919 let Latency = 3; let NumMicroOps = 2;
921 def : InstRW<[KryoWrite_3cyc_XY_XY_102ln],
922 (instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>;
923 def KryoWrite_5cyc_X_noRSV_52ln :
924 SchedWriteRes<[KryoUnitX]> {
925 let Latency = 5; let NumMicroOps = 2;
927 def : InstRW<[KryoWrite_5cyc_X_noRSV_52ln],
928 (instrs FRECPS32, FRSQRTS32)>;
929 def KryoWrite_6cyc_X_noRSV_58ln :
930 SchedWriteRes<[KryoUnitX]> {
931 let Latency = 6; let NumMicroOps = 2;
933 def : InstRW<[KryoWrite_6cyc_X_noRSV_58ln],
934 (instrs FRECPS64, FRSQRTS64)>;
935 def KryoWrite_5cyc_X_noRSV_126ln :
936 SchedWriteRes<[KryoUnitX]> {
937 let Latency = 5; let NumMicroOps = 2;
939 def : InstRW<[KryoWrite_5cyc_X_noRSV_126ln],
940 (instrs FRECPSv2f32, FRSQRTSv2f32)>;
941 def KryoWrite_5cyc_X_X_129ln :
942 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
943 let Latency = 5; let NumMicroOps = 2;
945 def : InstRW<[KryoWrite_5cyc_X_X_129ln],
946 (instrs FRECPSv4f32, FRSQRTSv4f32)>;
947 def KryoWrite_6cyc_X_X_132ln :
948 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
949 let Latency = 6; let NumMicroOps = 2;
951 def : InstRW<[KryoWrite_6cyc_X_X_132ln],
952 (instrs FRECPSv2f64, FRSQRTSv2f64)>;
953 def KryoWrite_3cyc_XY_noRSV_50ln :
954 SchedWriteRes<[KryoUnitXY]> {
955 let Latency = 3; let NumMicroOps = 2;
957 def : InstRW<[KryoWrite_3cyc_XY_noRSV_50ln],
958 (instrs FRECPXv1i32, FRECPXv1i64)>;
959 def KryoWrite_2cyc_XY_noRSV_39ln :
960 SchedWriteRes<[KryoUnitXY]> {
961 let Latency = 2; let NumMicroOps = 2;
963 def : InstRW<[KryoWrite_2cyc_XY_noRSV_39ln],
964 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
965 def KryoWrite_2cyc_XY_noRSV_108ln :
966 SchedWriteRes<[KryoUnitXY]> {
967 let Latency = 2; let NumMicroOps = 2;
969 def : InstRW<[KryoWrite_2cyc_XY_noRSV_108ln],
970 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
971 def KryoWrite_2cyc_XY_XY_109ln :
972 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
973 let Latency = 2; let NumMicroOps = 2;
975 def : InstRW<[KryoWrite_2cyc_XY_XY_109ln],
976 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
977 def KryoWrite_12cyc_XA_Y_noRSV_42ln :
978 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
979 let Latency = 12; let NumMicroOps = 3;
981 def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_42ln],
983 def KryoWrite_21cyc_XA_Y_noRSV_42ln :
984 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
985 let Latency = 21; let NumMicroOps = 3;
987 def : InstRW<[KryoWrite_21cyc_XA_Y_noRSV_42ln],
989 def KryoWrite_12cyc_XA_Y_noRSV_120ln :
990 SchedWriteRes<[KryoUnitXA, KryoUnitY]> {
991 let Latency = 12; let NumMicroOps = 3;
993 def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_120ln],
994 (instrs FSQRTv2f32)>;
995 def KryoWrite_21cyc_XA_Y_XA_Y_122ln :
996 SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {
997 let Latency = 21; let NumMicroOps = 4;
999 def : InstRW<[KryoWrite_21cyc_XA_Y_XA_Y_122ln],
1000 (instrs FSQRTv4f32)>;
1001 def KryoWrite_36cyc_XA_Y_XA_Y_122ln :
1002 SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {
1003 let Latency = 36; let NumMicroOps = 4;
1005 def : InstRW<[KryoWrite_36cyc_XA_Y_XA_Y_122ln],
1006 (instrs FSQRTv2f64)>;
1007 def KryoWrite_1cyc_X_201ln :
1008 SchedWriteRes<[KryoUnitX]> {
1009 let Latency = 1; let NumMicroOps = 1;
1011 def : InstRW<[KryoWrite_1cyc_X_201ln],
1012 (instregex "INSv.*")>;
1013 def KryoWrite_3cyc_LS_255ln :
1014 SchedWriteRes<[KryoUnitLS]> {
1015 let Latency = 3; let NumMicroOps = 1;
1017 def : InstRW<[KryoWrite_3cyc_LS_255ln],
1018 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;
1019 def KryoWrite_4cyc_LS_X_270ln :
1020 SchedWriteRes<[KryoUnitLS, KryoUnitX]> {
1021 let Latency = 4; let NumMicroOps = 2;
1023 def : InstRW<[KryoWrite_4cyc_LS_X_270ln],
1024 (instregex "LD1(i8|i16|i32)$")>;
1025 def KryoWrite_3cyc_LS_noRSV_285ln :
1026 SchedWriteRes<[KryoUnitLS]> {
1027 let Latency = 3; let NumMicroOps = 2;
1029 def : InstRW<[KryoWrite_3cyc_LS_noRSV_285ln],
1030 (instregex "LD1One(v8b|v4h|v2s|v1d)$")>;
1031 def KryoWrite_3cyc_LS_XY_289ln :
1032 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1033 let Latency = 3; let NumMicroOps = 2;
1035 def : InstRW<[KryoWrite_3cyc_LS_XY_289ln, WriteAdr],
1036 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;
1037 def KryoWrite_4cyc_LS_XY_X_298ln :
1038 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX]> {
1039 let Latency = 4; let NumMicroOps = 3;
1041 def : InstRW<[KryoWrite_4cyc_LS_XY_X_298ln, WriteAdr],
1042 (instregex "LD1(i8|i16|i32)_POST$")>;
1043 def KryoWrite_3cyc_LS_LS_LS_308ln :
1044 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1045 let Latency = 3; let NumMicroOps = 3;
1047 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_308ln],
1048 (instregex "LD1Three(v16b|v8h|v4s|v2d)$")>;
1049 def KryoWrite_3cyc_LS_XY_noRSV_317ln :
1050 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1051 let Latency = 3; let NumMicroOps = 3;
1053 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_317ln, WriteAdr],
1054 (instregex "LD1One(v8b|v4h|v2s|v1d)_POST$")>;
1055 def KryoWrite_3cyc_LS_LS_LS_LS_328ln :
1056 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1057 let Latency = 3; let NumMicroOps = 4;
1059 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_328ln, WriteAdr],
1060 (instregex "LD1Four(v16b|v8h|v4s|v2d)_POST$")>;
1061 def KryoWrite_3cyc_LS_XY_LS_LS_332ln :
1062 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {
1063 let Latency = 3; let NumMicroOps = 4;
1065 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_332ln, WriteAdr],
1066 (instregex "LD1Three(v16b|v8h|v4s|v2d)_POST$")>;
1067 def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln :
1068 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1069 let Latency = 3; let NumMicroOps = 5;
1071 def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln],
1072 (instregex "LD1Three(v8b|v4h|v2s|v1d)$")>;
1073 def KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln :
1074 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1075 let Latency = 3; let NumMicroOps = 5;
1077 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln],
1078 (instregex "LD1Four(v16b|v8h|v4s|v2d)$")>;
1079 def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln :
1080 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1081 let Latency = 3; let NumMicroOps = 6;
1083 def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln],
1084 (instregex "LD1Four(v8b|v4h|v2s|v1d)$")>;
1085 def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln :
1086 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1087 let Latency = 3; let NumMicroOps = 6;
1089 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln, WriteAdr],
1090 (instregex "LD1Three(v8b|v4h|v2s|v1d)_POST$")>;
1091 def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln :
1092 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1093 let Latency = 3; let NumMicroOps = 7;
1095 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln, WriteAdr],
1096 (instregex "LD1Four(v8b|v4h|v2s|v1d)_POST$")>;
1097 def KryoWrite_3cyc_LS_LS_281ln :
1098 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1099 let Latency = 3; let NumMicroOps = 2;
1101 def : InstRW<[KryoWrite_3cyc_LS_LS_281ln],
1102 (instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)$")>;
1103 def KryoWrite_3cyc_LS_noRSV_noRSV_311ln :
1104 SchedWriteRes<[KryoUnitLS]> {
1105 let Latency = 3; let NumMicroOps = 3;
1107 def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_311ln],
1108 (instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)$")>;
1109 def KryoWrite_3cyc_LS_XY_LS_313ln :
1110 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1111 let Latency = 3; let NumMicroOps = 3;
1113 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_313ln, WriteAdr],
1114 (instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)_POST$")>;
1115 def KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln :
1116 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1117 let Latency = 3; let NumMicroOps = 4;
1119 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln, WriteAdr],
1120 (instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)_POST$")>;
1121 def KryoWrite_3cyc_LS_256ln :
1122 SchedWriteRes<[KryoUnitLS]> {
1123 let Latency = 3; let NumMicroOps = 1;
1125 def : InstRW<[KryoWrite_3cyc_LS_256ln],
1126 (instregex "LD1R(v16b|v8h|v4s|v2d)$")>;
1127 def KryoWrite_3cyc_LS_noRSV_286ln :
1128 SchedWriteRes<[KryoUnitLS]> {
1129 let Latency = 3; let NumMicroOps = 2;
1131 def : InstRW<[KryoWrite_3cyc_LS_noRSV_286ln],
1132 (instregex "LD1R(v8b|v4h|v2s|v1d)$")>;
1133 def KryoWrite_3cyc_LS_XY_290ln :
1134 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1135 let Latency = 3; let NumMicroOps = 2;
1137 def : InstRW<[KryoWrite_3cyc_LS_XY_290ln, WriteAdr],
1138 (instregex "LD1R(v16b|v8h|v4s|v2d)_POST$")>;
1139 def KryoWrite_3cyc_LS_XY_noRSV_318ln :
1140 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1141 let Latency = 3; let NumMicroOps = 3;
1143 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_318ln, WriteAdr],
1144 (instregex "LD1R(v8b|v4h|v2s|v1d)_POST$")>;
1145 def KryoWrite_3cyc_LS_257ln :
1146 SchedWriteRes<[KryoUnitLS]> {
1147 let Latency = 3; let NumMicroOps = 1;
1149 def : InstRW<[KryoWrite_3cyc_LS_257ln],
1150 (instregex "LD2i64$")>;
1151 def KryoWrite_3cyc_LS_XY_291ln :
1152 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1153 let Latency = 3; let NumMicroOps = 2;
1155 def : InstRW<[KryoWrite_3cyc_LS_XY_291ln, WriteAdr],
1156 (instregex "LD2i64_POST$")>;
1157 def KryoWrite_4cyc_LS_X_X_296ln :
1158 SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX]> {
1159 let Latency = 4; let NumMicroOps = 3;
1161 def : InstRW<[KryoWrite_4cyc_LS_X_X_296ln],
1162 (instregex "LD2(i8|i16|i32)$")>;
1163 def KryoWrite_4cyc_LS_XY_X_X_321ln :
1164 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX]> {
1165 let Latency = 4; let NumMicroOps = 4;
1167 def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_321ln, WriteAdr],
1168 (instregex "LD2(i8|i16|i32)_POST$")>;
1169 def KryoWrite_3cyc_LS_LS_282ln :
1170 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1171 let Latency = 3; let NumMicroOps = 2;
1173 def : InstRW<[KryoWrite_3cyc_LS_LS_282ln],
1174 (instregex "LD2R(v16b|v8h|v4s|v2d)$")>;
1175 def KryoWrite_3cyc_LS_noRSV_noRSV_312ln :
1176 SchedWriteRes<[KryoUnitLS]> {
1177 let Latency = 3; let NumMicroOps = 3;
1179 def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_312ln],
1180 (instregex "LD2R(v8b|v4h|v2s|v1d)$")>;
1181 def KryoWrite_3cyc_LS_XY_LS_314ln :
1182 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1183 let Latency = 3; let NumMicroOps = 3;
1185 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_314ln, WriteAdr],
1186 (instregex "LD2R(v16b|v8h|v4s|v2d)_POST$")>;
1187 def KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln :
1188 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1189 let Latency = 3; let NumMicroOps = 4;
1191 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln, WriteAdr],
1192 (instregex "LD2R(v8b|v4h|v2s|v1d)_POST$")>;
1193 def KryoWrite_3cyc_LS_LS_283ln :
1194 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1195 let Latency = 3; let NumMicroOps = 2;
1197 def : InstRW<[KryoWrite_3cyc_LS_LS_283ln],
1198 (instregex "LD3i64$")>;
1199 def KryoWrite_3cyc_LS_LS_LS_309ln :
1200 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1201 let Latency = 3; let NumMicroOps = 3;
1203 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_309ln],
1204 (instregex "LD3Threev2d$")>;
1205 def KryoWrite_3cyc_LS_XY_LS_315ln :
1206 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1207 let Latency = 3; let NumMicroOps = 3;
1209 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_315ln, WriteAdr],
1210 (instregex "LD3i64_POST$")>;
1211 def KryoWrite_4cyc_LS_X_X_X_320ln :
1212 SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {
1213 let Latency = 4; let NumMicroOps = 4;
1215 def : InstRW<[KryoWrite_4cyc_LS_X_X_X_320ln],
1216 (instregex "LD3(i8|i16|i32)$")>;
1217 def KryoWrite_3cyc_LS_XY_LS_LS_331ln :
1218 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {
1219 let Latency = 3; let NumMicroOps = 4;
1221 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_331ln, WriteAdr],
1222 (instregex "LD3Threev2d_POST$")>;
1223 def KryoWrite_4cyc_LS_XY_X_X_X_338ln :
1224 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX]> {
1225 let Latency = 4; let NumMicroOps = 5;
1227 def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_338ln, WriteAdr],
1228 (instregex "LD3(i8|i16|i32)_POST$")>;
1229 def KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln :
1230 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {
1231 let Latency = 4; let NumMicroOps = 8;
1233 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln],
1234 (instregex "LD3Three(v8b|v4h|v2s)$")>;
1235 def KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln :
1236 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,
1238 let Latency = 4; let NumMicroOps = 9;
1240 def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln, WriteAdr],
1241 (instregex "LD3Three(v8b|v4h|v2s)_POST$")>;
1242 def KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln :
1243 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,
1244 KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {
1245 let Latency = 4; let NumMicroOps = 10;
1247 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln],
1248 (instregex "LD3Three(v16b|v8h|v4s)$")>;
1249 def KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln :
1250 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,
1251 KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,
1253 let Latency = 4; let NumMicroOps = 11;
1255 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln, WriteAdr],
1256 (instregex "LD3Three(v16b|v8h|v4s)_POST$")>;
1257 def KryoWrite_3cyc_LS_LS_LS_310ln :
1258 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1259 let Latency = 3; let NumMicroOps = 3;
1261 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_310ln],
1262 (instregex "LD3R(v16b|v8h|v4s|v2d)$")>;
1263 def KryoWrite_3cyc_LS_XY_LS_LS_333ln :
1264 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {
1265 let Latency = 3; let NumMicroOps = 4;
1267 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_333ln, WriteAdr],
1268 (instregex "LD3R(v16b|v8h|v4s|v2d)_POST$")>;
1269 def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln :
1270 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1271 let Latency = 3; let NumMicroOps = 5;
1273 def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln],
1274 (instregex "LD3R(v8b|v4h|v2s|v1d)$")>;
1275 def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln :
1276 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1277 let Latency = 3; let NumMicroOps = 6;
1279 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln, WriteAdr],
1280 (instregex "LD3R(v8b|v4h|v2s|v1d)_POST$")>;
1281 def KryoWrite_3cyc_LS_LS_284ln :
1282 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1283 let Latency = 3; let NumMicroOps = 2;
1285 def : InstRW<[KryoWrite_3cyc_LS_LS_284ln],
1286 (instregex "LD4i64$")>;
1287 def KryoWrite_3cyc_LS_XY_LS_316ln :
1288 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1289 let Latency = 3; let NumMicroOps = 3;
1291 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_316ln, WriteAdr],
1292 (instregex "LD4i64_POST$")>;
1293 def KryoWrite_3cyc_LS_LS_LS_LS_329ln :
1294 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1295 let Latency = 3; let NumMicroOps = 4;
1297 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_329ln],
1298 (instregex "LD4Four(v2d)$")>;
1299 def KryoWrite_4cyc_LS_X_X_X_X_337ln :
1300 SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {
1301 let Latency = 4; let NumMicroOps = 5;
1303 def : InstRW<[KryoWrite_4cyc_LS_X_X_X_X_337ln],
1304 (instregex "LD4(i8|i16|i32)$")>;
1305 def KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln :
1306 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1307 let Latency = 3; let NumMicroOps = 5;
1309 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln, WriteAdr],
1310 (instregex "LD4Four(v2d)_POST$")>;
1311 def KryoWrite_4cyc_LS_XY_X_X_X_X_355ln :
1312 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX,
1314 let Latency = 4; let NumMicroOps = 6;
1316 def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_X_355ln, WriteAdr],
1317 (instregex "LD4(i8|i16|i32)_POST$")>;
1318 def KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln :
1319 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,
1321 let Latency = 4; let NumMicroOps = 10;
1323 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln],
1324 (instregex "LD4Four(v8b|v4h|v2s)$")>;
1325 def KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln :
1326 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,
1327 KryoUnitX, KryoUnitX]> {
1328 let Latency = 4; let NumMicroOps = 11;
1330 def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln, WriteAdr],
1331 (instregex "LD4Four(v8b|v4h|v2s)_POST$")>;
1332 def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln :
1333 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,
1334 KryoUnitX, KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX,
1335 KryoUnitX, KryoUnitX]> {
1336 let Latency = 4; let NumMicroOps = 12;
1338 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln],
1339 (instregex "LD4Four(v16b|v8h|v4s)$")>;
1340 def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln :
1341 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,
1342 KryoUnitX, KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX,
1343 KryoUnitX, KryoUnitX, KryoUnitX]> {
1344 let Latency = 4; let NumMicroOps = 13;
1346 def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln, WriteAdr],
1347 (instregex "LD4Four(v16b|v8h|v4s)_POST$")>;
1348 def KryoWrite_3cyc_LS_LS_LS_LS_330ln :
1349 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1350 let Latency = 3; let NumMicroOps = 4;
1352 def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_330ln],
1353 (instregex "LD4R(v16b|v8h|v4s|v2d)$")>;
1354 def KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln :
1355 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {
1356 let Latency = 3; let NumMicroOps = 5;
1358 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln, WriteAdr],
1359 (instregex "LD4R(v16b|v8h|v4s|v2d)_POST$")>;
1360 def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln :
1361 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1362 let Latency = 3; let NumMicroOps = 6;
1364 def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln],
1365 (instregex "LD4R(v8b|v4h|v2s|v1d)$")>;
1366 def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln :
1367 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1368 let Latency = 3; let NumMicroOps = 7;
1370 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln, WriteAdr],
1371 (instregex "LD4R(v8b|v4h|v2s|v1d)_POST$")>;
1372 def KryoWrite_3cyc_LS_LS_400ln :
1373 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1374 let Latency = 3; let NumMicroOps = 2;
1376 def : InstRW<[KryoWrite_3cyc_LS_LS_400ln],
1377 (instregex "LDAX?R(B|H|W|X)")>;
1378 def : InstRW<[KryoWrite_3cyc_LS_LS_400ln, WriteLDHi],
1379 (instregex "LDAXP(W|X)")>;
1380 def KryoWrite_3cyc_LS_LS_401ln :
1381 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1382 let Latency = 3; let NumMicroOps = 2;
1384 def : InstRW<[KryoWrite_3cyc_LS_LS_401ln, WriteLDHi],
1386 def KryoWrite_3cyc_LS_noRSV_noRSV_408ln :
1387 SchedWriteRes<[KryoUnitLS]> {
1388 let Latency = 3; let NumMicroOps = 3;
1390 def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_408ln, WriteLDHi],
1391 (instrs LDNPDi, LDNPSi)>;
1392 def KryoWrite_3cyc_LS_394ln :
1393 SchedWriteRes<[KryoUnitLS]> {
1394 let Latency = 3; let NumMicroOps = 1;
1396 def : InstRW<[KryoWrite_3cyc_LS_394ln, WriteLDHi],
1397 (instrs LDNPWi, LDNPXi)>;
1398 def KryoWrite_3cyc_LS_LS_402ln :
1399 SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {
1400 let Latency = 3; let NumMicroOps = 2;
1402 def : InstRW<[KryoWrite_3cyc_LS_LS_402ln, WriteLDHi],
1404 def KryoWrite_3cyc_LS_noRSV_noRSV_409ln :
1405 SchedWriteRes<[KryoUnitLS]> {
1406 let Latency = 3; let NumMicroOps = 3;
1408 def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_409ln, WriteLDHi],
1409 (instrs LDPDi, LDPSi)>;
1410 def KryoWrite_3cyc_LS_XY_LS_410ln :
1411 SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {
1412 let Latency = 3; let NumMicroOps = 3;
1414 def : InstRW<[KryoWrite_3cyc_LS_XY_LS_410ln, WriteLDHi, WriteAdr],
1415 (instregex "LDPQ(post|pre)")>;
1416 def KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln :
1417 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1418 let Latency = 3; let NumMicroOps = 4;
1420 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln, WriteLDHi, WriteAdr],
1421 (instregex "LDP(D|S)(post|pre)")>;
1422 def KryoWrite_3cyc_LS_393ln :
1423 SchedWriteRes<[KryoUnitLS]> {
1424 let Latency = 3; let NumMicroOps = 1;
1426 def : InstRW<[KryoWrite_3cyc_LS_393ln, WriteLDHi],
1427 (instrs LDPWi, LDPXi)>;
1428 def KryoWrite_3cyc_LS_XY_403ln :
1429 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1430 let Latency = 3; let NumMicroOps = 2;
1432 def : InstRW<[KryoWrite_3cyc_LS_XY_403ln, WriteLDHi, WriteAdr],
1433 (instregex "LDP(W|X)(post|pre)")>;
1434 def KryoWrite_4cyc_LS_395ln :
1435 SchedWriteRes<[KryoUnitLS]> {
1436 let Latency = 4; let NumMicroOps = 1;
1438 def : InstRW<[KryoWrite_4cyc_LS_395ln, WriteLDHi],
1440 def KryoWrite_4cyc_LS_XY_405ln :
1441 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1442 let Latency = 4; let NumMicroOps = 2;
1444 def : InstRW<[KryoWrite_4cyc_LS_XY_405ln, WriteLDHi, WriteAdr],
1445 (instrs LDPSWpost, LDPSWpre)>;
1446 def KryoWrite_3cyc_LS_264ln :
1447 SchedWriteRes<[KryoUnitLS]> {
1448 let Latency = 3; let NumMicroOps = 1;
1450 def : InstRW<[KryoWrite_3cyc_LS_264ln],
1451 (instrs LDRQui, LDRQl)>;
1452 def KryoWrite_4cyc_X_LS_271ln :
1453 SchedWriteRes<[KryoUnitX, KryoUnitLS]> {
1454 let Latency = 4; let NumMicroOps = 2;
1456 def : InstRW<[KryoWrite_4cyc_X_LS_271ln],
1457 (instrs LDRQroW, LDRQroX)>;
1458 def KryoWrite_3cyc_LS_noRSV_287ln :
1459 SchedWriteRes<[KryoUnitLS]> {
1460 let Latency = 3; let NumMicroOps = 2;
1462 def : InstRW<[KryoWrite_3cyc_LS_noRSV_287ln],
1463 (instregex "LDR((D|S)l|(D|S|H|B)ui)")>;
1464 def KryoWrite_3cyc_LS_XY_293ln :
1465 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1466 let Latency = 3; let NumMicroOps = 2;
1468 def : InstRW<[KryoWrite_3cyc_LS_XY_293ln, WriteAdr],
1469 (instrs LDRQpost, LDRQpre)>;
1470 def KryoWrite_4cyc_X_LS_noRSV_297ln :
1471 SchedWriteRes<[KryoUnitX, KryoUnitLS]> {
1472 let Latency = 4; let NumMicroOps = 3;
1474 def : InstRW<[KryoWrite_4cyc_X_LS_noRSV_297ln],
1475 (instregex "LDR(D|S|H|B)ro(W|X)")>;
1476 def KryoWrite_3cyc_LS_XY_noRSV_319ln :
1477 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1478 let Latency = 3; let NumMicroOps = 3;
1480 def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_319ln, WriteAdr],
1481 (instregex "LDR(D|S|H|B)(post|pre)")>;
1482 def KryoWrite_3cyc_LS_261ln :
1483 SchedWriteRes<[KryoUnitLS]> {
1484 let Latency = 3; let NumMicroOps = 1;
1486 def : InstRW<[KryoWrite_3cyc_LS_261ln],
1487 (instregex "LDR(BB|HH|W|X)ui")>;
1488 def KryoWrite_3cyc_LS_XY_292ln :
1489 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1490 let Latency = 3; let NumMicroOps = 2;
1492 def : InstRW<[KryoWrite_3cyc_LS_XY_292ln, WriteAdr],
1493 (instregex "LDR(BB|HH|W|X)(post|pre)")>;
1494 def KryoWrite_4cyc_X_LS_272ln :
1495 SchedWriteRes<[KryoUnitX, KryoUnitLS]> {
1496 let Latency = 4; let NumMicroOps = 2;
1498 def : InstRW<[KryoWrite_4cyc_X_LS_272ln],
1499 (instregex "(LDR(BB|HH|W|X)ro(W|X)|PRFMro(W|X))")>;
1500 def KryoWrite_3cyc_LS_262ln :
1501 SchedWriteRes<[KryoUnitLS]> {
1502 let Latency = 3; let NumMicroOps = 1;
1504 def : InstRW<[KryoWrite_3cyc_LS_262ln],
1505 (instrs LDRWl, LDRXl)>;
1506 def KryoWrite_4cyc_LS_268ln :
1507 SchedWriteRes<[KryoUnitLS]> {
1508 let Latency = 4; let NumMicroOps = 1;
1510 def : InstRW<[KryoWrite_4cyc_LS_268ln],
1511 (instregex "LDRS(BW|BX|HW|HX|W)ui")>;
1512 def KryoWrite_5cyc_X_LS_273ln :
1513 SchedWriteRes<[KryoUnitX, KryoUnitLS]> {
1514 let Latency = 5; let NumMicroOps = 2;
1516 def : InstRW<[KryoWrite_5cyc_X_LS_273ln],
1517 (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;
1518 def KryoWrite_4cyc_LS_XY_294ln :
1519 SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {
1520 let Latency = 4; let NumMicroOps = 2;
1522 def : InstRW<[KryoWrite_4cyc_LS_XY_294ln, WriteAdr],
1523 (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;
1524 def KryoWrite_4cyc_LS_269ln :
1525 SchedWriteRes<[KryoUnitLS]> {
1526 let Latency = 4; let NumMicroOps = 1;
1528 def : InstRW<[KryoWrite_4cyc_LS_269ln],
1530 def KryoWrite_3cyc_LS_260ln :
1531 SchedWriteRes<[KryoUnitLS]> {
1532 let Latency = 3; let NumMicroOps = 1;
1534 def : InstRW<[KryoWrite_3cyc_LS_260ln],
1535 (instregex "LDTR(B|H|W|X)i")>;
1536 def KryoWrite_4cyc_LS_267ln :
1537 SchedWriteRes<[KryoUnitLS]> {
1538 let Latency = 4; let NumMicroOps = 1;
1540 def : InstRW<[KryoWrite_4cyc_LS_267ln],
1541 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
1542 def KryoWrite_3cyc_LS_263ln :
1543 SchedWriteRes<[KryoUnitLS]> {
1544 let Latency = 3; let NumMicroOps = 1;
1546 def : InstRW<[KryoWrite_3cyc_LS_263ln],
1548 def KryoWrite_3cyc_LS_noRSV_288ln :
1549 SchedWriteRes<[KryoUnitLS]> {
1550 let Latency = 3; let NumMicroOps = 2;
1552 def : InstRW<[KryoWrite_3cyc_LS_noRSV_288ln],
1553 (instregex "LDUR(D|S|H|B)i")>;
1554 def KryoWrite_3cyc_LS_259ln :
1555 SchedWriteRes<[KryoUnitLS]> {
1556 let Latency = 3; let NumMicroOps = 1;
1558 def : InstRW<[KryoWrite_3cyc_LS_259ln],
1559 (instregex "LDUR(BB|HH|W|X)i")>;
1560 def KryoWrite_4cyc_LS_266ln :
1561 SchedWriteRes<[KryoUnitLS]> {
1562 let Latency = 4; let NumMicroOps = 1;
1564 def : InstRW<[KryoWrite_4cyc_LS_266ln],
1565 (instregex "LDURS(B|H)?(W|X)i")>;
1566 def KryoWrite_3cyc_LS_258ln :
1567 SchedWriteRes<[KryoUnitLS]> {
1568 let Latency = 3; let NumMicroOps = 1;
1570 def : InstRW<[KryoWrite_3cyc_LS_258ln, WriteLDHi],
1571 (instregex "LDXP(W|X)")>;
1572 def KryoWrite_3cyc_LS_258_1ln :
1573 SchedWriteRes<[KryoUnitLS]> {
1574 let Latency = 3; let NumMicroOps = 1;
1576 def : InstRW<[KryoWrite_3cyc_LS_258_1ln],
1577 (instregex "LDXR(B|H|W|X)")>;
1578 def KryoWrite_2cyc_XY_XY_137ln :
1579 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1580 let Latency = 2; let NumMicroOps = 2;
1582 def : InstRW<[KryoWrite_2cyc_XY_XY_137ln],
1583 (instrs LSLVWr, LSLVXr)>;
1584 def KryoWrite_1cyc_XY_135ln :
1585 SchedWriteRes<[KryoUnitXY]> {
1586 let Latency = 1; let NumMicroOps = 1;
1588 def : InstRW<[KryoWrite_1cyc_XY_135ln],
1589 (instregex "(LS|AS|RO)RV(W|X)r")>;
1590 def KryoWrite_4cyc_X_84ln :
1591 SchedWriteRes<[KryoUnitX]> {
1592 let Latency = 4; let NumMicroOps = 1;
1594 def : InstRW<[KryoWrite_4cyc_X_84ln],
1595 (instrs MADDWrrr, MSUBWrrr)>;
1596 def KryoWrite_5cyc_X_85ln :
1597 SchedWriteRes<[KryoUnitX]> {
1598 let Latency = 5; let NumMicroOps = 1;
1600 def : InstRW<[KryoWrite_5cyc_X_85ln],
1601 (instrs MADDXrrr, MSUBXrrr)>;
1602 def KryoWrite_4cyc_X_noRSV_188ln :
1603 SchedWriteRes<[KryoUnitX]> {
1604 let Latency = 4; let NumMicroOps = 2;
1606 def : InstRW<[KryoWrite_4cyc_X_noRSV_188ln],
1607 (instregex "(MLA|MLS|MUL)(v8i8|v4i16|v2i32)(_indexed)?")>;
1608 def KryoWrite_4cyc_X_X_192ln :
1609 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
1610 let Latency = 4; let NumMicroOps = 2;
1612 def : InstRW<[KryoWrite_4cyc_X_X_192ln],
1613 (instregex "(MLA|MLS|MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?")>;
1614 def KryoWrite_1cyc_XY_noRSV_198ln :
1615 SchedWriteRes<[KryoUnitXY]> {
1616 let Latency = 1; let NumMicroOps = 2;
1618 def : InstRW<[KryoWrite_1cyc_XY_noRSV_198ln],
1619 (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)")>;
1620 def KryoWrite_1cyc_XY_XY_199ln :
1621 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1622 let Latency = 1; let NumMicroOps = 2;
1624 def : InstRW<[KryoWrite_1cyc_XY_XY_199ln],
1625 (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)")>;
1626 def KryoWrite_1cyc_X_89ln :
1627 SchedWriteRes<[KryoUnitX]> {
1628 let Latency = 1; let NumMicroOps = 1;
1630 def : InstRW<[KryoWrite_1cyc_X_89ln],
1631 (instrs MOVKWi, MOVKXi)>;
1632 def KryoWrite_1cyc_XY_91ln :
1633 SchedWriteRes<[KryoUnitXY]> {
1634 let Latency = 1; let NumMicroOps = 1;
1636 def : InstRW<[KryoWrite_1cyc_XY_91ln],
1637 (instrs MOVNWi, MOVNXi)>;
1638 def KryoWrite_1cyc_XY_90ln :
1639 SchedWriteRes<[KryoUnitXY]> {
1640 let Latency = 1; let NumMicroOps = 1;
1642 def : InstRW<[KryoWrite_1cyc_XY_90ln],
1643 (instrs MOVZWi, MOVZXi)>;
1644 def KryoWrite_2cyc_XY_93ln :
1645 SchedWriteRes<[KryoUnitXY]> {
1646 let Latency = 2; let NumMicroOps = 1;
1648 def : InstRW<[KryoWrite_2cyc_XY_93ln],
1650 def KryoWrite_0cyc_X_87ln :
1651 SchedWriteRes<[KryoUnitX]> {
1652 let Latency = 0; let NumMicroOps = 1;
1654 def : InstRW<[KryoWrite_0cyc_X_87ln],
1655 (instrs MSRpstateImm4)>;
1656 def : InstRW<[KryoWrite_0cyc_X_87ln],
1657 (instrs MSRpstateImm1)>;
1658 def KryoWrite_0cyc_XY_88ln :
1659 SchedWriteRes<[KryoUnitXY]> {
1660 let Latency = 0; let NumMicroOps = 1;
1662 def : InstRW<[KryoWrite_0cyc_XY_88ln],
1664 def KryoWrite_1cyc_XY_noRSV_143ln :
1665 SchedWriteRes<[KryoUnitXY]> {
1666 let Latency = 1; let NumMicroOps = 2;
1668 def : InstRW<[KryoWrite_1cyc_XY_noRSV_143ln],
1669 (instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>;
1670 def KryoWrite_1cyc_XY_XY_145ln :
1671 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1672 let Latency = 1; let NumMicroOps = 2;
1674 def : InstRW<[KryoWrite_1cyc_XY_XY_145ln],
1675 (instregex "NEG(v16i8|v8i16|v4i32|v2i64)")>;
1676 def KryoWrite_1cyc_XY_noRSV_193ln :
1677 SchedWriteRes<[KryoUnitXY]> {
1678 let Latency = 1; let NumMicroOps = 2;
1680 def : InstRW<[KryoWrite_1cyc_XY_noRSV_193ln],
1682 def KryoWrite_1cyc_XY_XY_194ln :
1683 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1684 let Latency = 1; let NumMicroOps = 2;
1686 def : InstRW<[KryoWrite_1cyc_XY_XY_194ln],
1688 def KryoWrite_2cyc_XY_noRSV_234ln :
1689 SchedWriteRes<[KryoUnitXY]> {
1690 let Latency = 2; let NumMicroOps = 2;
1692 def : InstRW<[KryoWrite_2cyc_XY_noRSV_234ln],
1694 def KryoWrite_2cyc_XY_XY_236ln :
1695 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1696 let Latency = 2; let NumMicroOps = 2;
1698 def : InstRW<[KryoWrite_2cyc_XY_XY_236ln],
1699 (instrs PMULv16i8)>;
1700 def KryoWrite_2cyc_XY_XY_235ln :
1701 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1702 let Latency = 2; let NumMicroOps = 2;
1704 def : InstRW<[KryoWrite_2cyc_XY_XY_235ln],
1705 (instrs PMULLv8i8, PMULLv16i8)>;
1706 def KryoWrite_3cyc_XY_XY_237ln :
1707 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1708 let Latency = 3; let NumMicroOps = 2;
1710 def : InstRW<[KryoWrite_3cyc_XY_XY_237ln],
1711 (instrs PMULLv1i64, PMULLv2i64)>;
1712 def KryoWrite_0cyc_LS_254ln :
1713 SchedWriteRes<[KryoUnitLS]> {
1714 let Latency = 0; let NumMicroOps = 1;
1716 def : InstRW<[KryoWrite_0cyc_LS_254ln],
1717 (instrs PRFMl, PRFMui)>;
1718 def KryoWrite_0cyc_LS_253ln :
1719 SchedWriteRes<[KryoUnitLS]> {
1720 let Latency = 0; let NumMicroOps = 1;
1722 def : InstRW<[KryoWrite_0cyc_LS_253ln],
1724 def KryoWrite_6cyc_XY_X_noRSV_175ln :
1725 SchedWriteRes<[KryoUnitXY, KryoUnitX]> {
1726 let Latency = 6; let NumMicroOps = 3;
1728 def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_175ln],
1729 (instregex "R(ADD|SUB)HNv.*")>;
1730 def KryoWrite_2cyc_XY_204ln :
1731 SchedWriteRes<[KryoUnitXY]> {
1732 let Latency = 2; let NumMicroOps = 1;
1734 def : InstRW<[KryoWrite_2cyc_XY_204ln],
1735 (instrs RBITWr, RBITXr)>;
1736 def KryoWrite_2cyc_XY_noRSV_218ln :
1737 SchedWriteRes<[KryoUnitXY]> {
1738 let Latency = 2; let NumMicroOps = 2;
1740 def : InstRW<[KryoWrite_2cyc_XY_noRSV_218ln],
1742 def KryoWrite_2cyc_XY_XY_219ln :
1743 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1744 let Latency = 2; let NumMicroOps = 2;
1746 def : InstRW<[KryoWrite_2cyc_XY_XY_219ln],
1747 (instrs RBITv16i8)>;
1748 def KryoWrite_1cyc_X_202ln :
1749 SchedWriteRes<[KryoUnitX]> {
1750 let Latency = 1; let NumMicroOps = 1;
1752 def : InstRW<[KryoWrite_1cyc_X_202ln],
1753 (instregex "REV(16|32)?(W|X)r")>;
1754 def KryoWrite_1cyc_XY_noRSV_214ln :
1755 SchedWriteRes<[KryoUnitXY]> {
1756 let Latency = 1; let NumMicroOps = 2;
1758 def : InstRW<[KryoWrite_1cyc_XY_noRSV_214ln],
1759 (instregex "REV(16|32|64)(v8i8|v4i16|v2i32)")>;
1760 def KryoWrite_1cyc_XY_XY_216ln :
1761 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1762 let Latency = 1; let NumMicroOps = 2;
1764 def : InstRW<[KryoWrite_1cyc_XY_XY_216ln],
1765 (instregex "REV(16|32|64)(v16i8|v8i16|v4i32)")>;
1766 def KryoWrite_3cyc_X_noRSV_244ln :
1767 SchedWriteRes<[KryoUnitX]> {
1768 let Latency = 3; let NumMicroOps = 2;
1770 def : InstRW<[KryoWrite_3cyc_X_noRSV_244ln],
1771 (instregex "S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)")>;
1772 def KryoWrite_3cyc_X_X_245ln :
1773 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
1774 let Latency = 3; let NumMicroOps = 2;
1776 def : InstRW<[KryoWrite_3cyc_X_X_245ln],
1777 (instregex "S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift")>;
1778 def KryoWrite_1cyc_XY_2ln :
1779 SchedWriteRes<[KryoUnitXY]> {
1780 let Latency = 1; let NumMicroOps = 1;
1782 def : InstRW<[KryoWrite_1cyc_XY_2ln, ReadI, ReadI],
1783 (instregex "SBCS?(W|X)r")>;
1784 def KryoWrite_2cyc_XA_XA_XA_24ln :
1785 SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> {
1786 let Latency = 2; let NumMicroOps = 3;
1788 def : InstRW<[KryoWrite_2cyc_XA_XA_XA_24ln],
1789 (instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr)>;
1790 def KryoWrite_1cyc_XY_noRSV_21ln :
1791 SchedWriteRes<[KryoUnitXY]> {
1792 let Latency = 1; let NumMicroOps = 2;
1794 def : InstRW<[KryoWrite_1cyc_XY_noRSV_21ln],
1796 def KryoWrite_2cyc_X_X_23ln :
1797 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
1798 let Latency = 2; let NumMicroOps = 2;
1800 def : InstRW<[KryoWrite_2cyc_X_X_23ln],
1801 (instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>;
1802 def KryoWrite_4cyc_XA_XA_XA_25ln :
1803 SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> {
1804 let Latency = 4; let NumMicroOps = 3;
1806 def : InstRW<[KryoWrite_4cyc_XA_XA_XA_25ln],
1807 (instrs SHA256Hrrr, SHA256H2rrr)>;
1808 def KryoWrite_3cyc_XY_XY_X_X_26ln :
1809 SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> {
1810 let Latency = 3; let NumMicroOps = 4;
1812 def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_26ln],
1813 (instrs SHA256SU1rrr)>;
1814 def KryoWrite_4cyc_X_noRSV_189ln :
1815 SchedWriteRes<[KryoUnitX]> {
1816 let Latency = 4; let NumMicroOps = 2;
1818 def : InstRW<[KryoWrite_4cyc_X_noRSV_189ln],
1819 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1820 def KryoWrite_3cyc_XY_noRSV_68ln :
1821 SchedWriteRes<[KryoUnitXY]> {
1822 let Latency = 3; let NumMicroOps = 2;
1824 def : InstRW<[KryoWrite_3cyc_XY_noRSV_68ln],
1825 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
1826 def KryoWrite_3cyc_XY_noRSV_157ln :
1827 SchedWriteRes<[KryoUnitXY]> {
1828 let Latency = 3; let NumMicroOps = 2;
1830 def : InstRW<[KryoWrite_3cyc_XY_noRSV_157ln],
1831 (instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>;
1832 def KryoWrite_3cyc_XY_XY_164ln :
1833 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
1834 let Latency = 3; let NumMicroOps = 2;
1836 def : InstRW<[KryoWrite_3cyc_XY_XY_164ln],
1837 (instregex "SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)")>;
1838 def KryoWrite_4cyc_X_noRSV_190ln :
1839 SchedWriteRes<[KryoUnitX]> {
1840 let Latency = 4; let NumMicroOps = 2;
1842 def : InstRW<[KryoWrite_4cyc_X_noRSV_190ln],
1843 (instregex "SQD(MLAL|MLSL|MULL)(i16|i32)")>;
1844 def KryoWrite_0cyc_LS_Y_274ln :
1845 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
1846 let Latency = 0; let NumMicroOps = 2;
1848 def : InstRW<[KryoWrite_0cyc_LS_Y_274ln],
1849 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;
1850 def KryoWrite_1cyc_LS_Y_X_301ln :
1851 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {
1852 let Latency = 1; let NumMicroOps = 3;
1854 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_301ln],
1855 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1856 def KryoWrite_1cyc_LS_Y_XY_305ln :
1857 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> {
1858 let Latency = 1; let NumMicroOps = 3;
1860 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_305ln],
1861 (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1862 def KryoWrite_0cyc_LS_Y_LS_Y_323ln :
1863 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
1864 let Latency = 0; let NumMicroOps = 4;
1866 def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_323ln],
1867 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
1868 def KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln :
1869 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {
1870 let Latency = 1; let NumMicroOps = 5;
1872 def : InstRW<[KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln],
1873 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
1874 def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln :
1875 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,
1877 let Latency = 0; let NumMicroOps = 6;
1879 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln],
1880 (instregex "ST1Three(v16b|v8h|v4s|v2d)$")>;
1881 def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln :
1882 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY,
1883 KryoUnitLS, KryoUnitY]> {
1884 let Latency = 1; let NumMicroOps = 7;
1886 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln],
1887 (instregex "ST1Three(v16b|v8h|v4s|v2d)_POST$")>;
1888 def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln :
1889 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,
1890 KryoUnitY, KryoUnitLS, KryoUnitY]> {
1891 let Latency = 0; let NumMicroOps = 8;
1893 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln],
1894 (instregex "ST1Four(v16b|v8h|v4s|v2d)$")>;
1895 def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln :
1896 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY,
1897 KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
1898 let Latency = 0; let NumMicroOps = 9;
1900 def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln],
1901 (instregex "ST1Four(v16b|v8h|v4s|v2d)_POST$")>;
1902 def KryoWrite_0cyc_LS_Y_275ln :
1903 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
1904 let Latency = 0; let NumMicroOps = 2;
1906 def : InstRW<[KryoWrite_0cyc_LS_Y_275ln],
1907 (instregex "ST2(Two(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64))$")>;
1908 def KryoWrite_1cyc_LS_Y_XY_306ln :
1909 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> {
1910 let Latency = 1; let NumMicroOps = 3;
1912 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_306ln],
1913 (instregex "ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))_POST$")>;
1914 def KryoWrite_0cyc_LS_Y_LS_Y_322ln :
1915 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
1916 let Latency = 0; let NumMicroOps = 4;
1918 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_322ln],
1919 (instregex "ST2Two(v16b|v8h|v4s|v2d)$")>;
1920 def KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln :
1921 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {
1922 let Latency = 1; let NumMicroOps = 5;
1924 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln],
1925 (instregex "ST2Two(v16b|v8h|v4s|v2d)_POST$")>;
1926 def KryoWrite_0cyc_LS_Y_LS_Y_324ln :
1927 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
1928 let Latency = 0; let NumMicroOps = 4;
1930 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_324ln],
1931 (instregex "ST3(Threev1d|(i8|i16|i32|i64))$")>;
1932 def KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln :
1933 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {
1934 let Latency = 1; let NumMicroOps = 5;
1936 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln],
1937 (instregex "ST3(Threev1d|(i8|i16|i32|i64))_POST$")>;
1938 def KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln :
1939 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,
1941 let Latency = 1; let NumMicroOps = 6;
1943 def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln],
1944 (instregex "ST3Three(v8b|v4h|v2s)$")>;
1945 def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln :
1946 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,
1948 let Latency = 0; let NumMicroOps = 6;
1950 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln],
1951 (instregex "ST3Threev2d$")>;
1952 def KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln :
1953 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY,
1954 KryoUnitLS, KryoUnitY]> {
1955 let Latency = 1; let NumMicroOps = 7;
1957 def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln],
1958 (instregex "ST3Three(v8b|v4h|v2s)_POST$")>;
1959 def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln :
1960 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY,
1961 KryoUnitLS, KryoUnitY]> {
1962 let Latency = 1; let NumMicroOps = 7;
1964 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln],
1965 (instregex "ST3Threev2d_POST$")>;
1966 def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln :
1967 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,
1968 KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY,
1969 KryoUnitLS, KryoUnitY]> {
1970 let Latency = 1; let NumMicroOps = 12;
1972 def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln],
1973 (instregex "ST3Three(v16b|v8h|v4s)$")>;
1974 def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln :
1975 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,
1976 KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY,
1977 KryoUnitXY, KryoUnitLS, KryoUnitY]> {
1978 let Latency = 1; let NumMicroOps = 13;
1980 def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln],
1981 (instregex "ST3Three(v16b|v8h|v4s)_POST$")>;
1982 def KryoWrite_0cyc_LS_Y_LS_Y_325ln :
1983 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
1984 let Latency = 0; let NumMicroOps = 4;
1986 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_325ln],
1987 (instregex "ST4(Fourv1d|(i8|i16|i32|i64))$")>;
1988 def KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln :
1989 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {
1990 let Latency = 1; let NumMicroOps = 5;
1992 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln],
1993 (instregex "ST4(Fourv1d|(i8|i16|i32|i64))_POST$")>;
1994 def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln :
1995 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,
1996 KryoUnitX, KryoUnitLS, KryoUnitY]> {
1997 let Latency = 1; let NumMicroOps = 8;
1999 def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln],
2000 (instregex "ST4Four(v8b|v4h|v2s)$")>;
2001 def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln :
2002 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,
2003 KryoUnitY, KryoUnitLS, KryoUnitY]> {
2004 let Latency = 0; let NumMicroOps = 8;
2006 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln],
2007 (instregex "ST4Fourv2d$")>;
2008 def KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln :
2009 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY,
2010 KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> {
2011 let Latency = 1; let NumMicroOps = 9;
2013 def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln],
2014 (instregex "ST4Four(v8b|v4h|v2s)_POST$")>;
2015 def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln :
2016 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY,
2017 KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
2018 let Latency = 0; let NumMicroOps = 9;
2020 def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln],
2021 (instregex "ST4Fourv2d_POST$")>;
2022 def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln :
2023 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,
2024 KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX,
2025 KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS,
2027 let Latency = 1; let NumMicroOps = 16;
2029 def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln],
2030 (instregex "ST4Four(v16b|v8h|v4s)$")>;
2031 def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln :
2032 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,
2033 KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX,
2034 KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitX, KryoUnitX,
2035 KryoUnitLS, KryoUnitY]> {
2036 let Latency = 1; let NumMicroOps = 17;
2038 def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln],
2039 (instregex "ST4Four(v16b|v8h|v4s)_POST$")>;
2040 def KryoWrite_0cyc_LS_LS_Y_299ln :
2041 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> {
2042 let Latency = 0; let NumMicroOps = 3;
2044 def : InstRW<[KryoWrite_0cyc_LS_LS_Y_299ln],
2045 (instregex "STLR(B|H|W|X)")>;
2046 def KryoWrite_3cyc_LS_LS_Y_307ln :
2047 SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> {
2048 let Latency = 3; let NumMicroOps = 3;
2050 def : InstRW<[KryoWrite_3cyc_LS_LS_Y_307ln],
2051 (instregex "STLX(P(W|X)|R(B|H|W|X))")>;
2052 def KryoWrite_0cyc_LS_Y_276ln :
2053 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2054 let Latency = 0; let NumMicroOps = 2;
2056 def : InstRW<[KryoWrite_0cyc_LS_Y_276ln],
2057 (instrs STNPDi, STNPSi)>;
2058 def KryoWrite_0cyc_LS_Y_LS_Y_326ln :
2059 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
2060 let Latency = 0; let NumMicroOps = 4;
2062 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_326ln],
2064 def KryoWrite_0cyc_LS_Y_280ln :
2065 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2066 let Latency = 0; let NumMicroOps = 2;
2068 def : InstRW<[KryoWrite_0cyc_LS_Y_280ln],
2069 (instrs STNPWi, STNPXi)>;
2070 def KryoWrite_0cyc_LS_Y_277ln :
2071 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2072 let Latency = 0; let NumMicroOps = 2;
2074 def : InstRW<[KryoWrite_0cyc_LS_Y_277ln],
2075 (instregex "STP(D|S)i")>;
2076 def KryoWrite_1cyc_LS_Y_X_303ln :
2077 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {
2078 let Latency = 1; let NumMicroOps = 3;
2080 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_303ln],
2081 (instregex "STP(D|S)(post|pre)")>;
2082 def KryoWrite_0cyc_LS_Y_LS_Y_327ln :
2083 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {
2084 let Latency = 0; let NumMicroOps = 4;
2086 def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_327ln],
2088 def KryoWrite_1cyc_LS_Y_X_LS_Y_343ln :
2089 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitLS, KryoUnitY]> {
2090 let Latency = 1; let NumMicroOps = 5;
2092 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_LS_Y_343ln],
2093 (instrs STPQpost, STPQpre)>;
2094 def KryoWrite_0cyc_LS_Y_279ln :
2095 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2096 let Latency = 0; let NumMicroOps = 2;
2098 def : InstRW<[KryoWrite_0cyc_LS_Y_279ln],
2099 (instregex "STP(W|X)i")>;
2100 def KryoWrite_1cyc_LS_X_Y_300ln :
2101 SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> {
2102 let Latency = 1; let NumMicroOps = 3;
2104 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_300ln],
2105 (instregex "STP(W|X)(post|pre)")>;
2106 def KryoWrite_0cyc_LS_Y_278ln :
2107 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2108 let Latency = 0; let NumMicroOps = 2;
2110 def : InstRW<[KryoWrite_0cyc_LS_Y_278ln],
2111 (instregex "STR(Q|D|S|H|B)ui")>;
2112 def KryoWrite_1cyc_X_LS_Y_295ln :
2113 SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> {
2114 let Latency = 1; let NumMicroOps = 3;
2116 def : InstRW<[KryoWrite_1cyc_X_LS_Y_295ln],
2117 (instregex "STR(D|S|H|B)ro(W|X)")>;
2118 def KryoWrite_1cyc_LS_Y_X_304ln :
2119 SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {
2120 let Latency = 1; let NumMicroOps = 3;
2122 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_304ln],
2123 (instregex "STR(Q|D|S|H|B)(post|pre)")>;
2124 def KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln :
2125 SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS,
2127 let Latency = 2; let NumMicroOps = 6;
2129 def : InstRW<[KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln],
2130 (instregex "STRQro(W|X)")>;
2131 def KryoWrite_0cyc_LS_Y_399ln :
2132 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2133 let Latency = 0; let NumMicroOps = 2;
2135 def : InstRW<[KryoWrite_0cyc_LS_Y_399ln],
2136 (instregex "STR(BB|HH|W|X)ui")>;
2137 def KryoWrite_1cyc_X_LS_Y_406ln :
2138 SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> {
2139 let Latency = 1; let NumMicroOps = 3;
2141 def : InstRW<[KryoWrite_1cyc_X_LS_Y_406ln],
2142 (instregex "STR(BB|HH|W|X)ro(W|X)")>;
2143 def KryoWrite_1cyc_LS_X_Y_407ln :
2144 SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> {
2145 let Latency = 1; let NumMicroOps = 3;
2147 def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_407ln],
2148 (instregex "STR(BB|HH|W|X)(post|pre)")>;
2149 def KryoWrite_0cyc_LS_Y_398ln :
2150 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2151 let Latency = 0; let NumMicroOps = 2;
2153 def : InstRW<[KryoWrite_0cyc_LS_Y_398ln],
2154 (instregex "STTR(B|H|W|X)i")>;
2155 def KryoWrite_0cyc_LS_Y_396ln :
2156 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2157 let Latency = 0; let NumMicroOps = 2;
2159 def : InstRW<[KryoWrite_0cyc_LS_Y_396ln],
2160 (instregex "STUR(Q|D|S|H|B)i")>;
2161 def KryoWrite_0cyc_LS_Y_397ln :
2162 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2163 let Latency = 0; let NumMicroOps = 2;
2165 def : InstRW<[KryoWrite_0cyc_LS_Y_397ln],
2166 (instregex "STUR(BB|HH|W|X)i")>;
2167 def KryoWrite_3cyc_LS_Y_404ln :
2168 SchedWriteRes<[KryoUnitLS, KryoUnitY]> {
2169 let Latency = 3; let NumMicroOps = 2;
2171 def : InstRW<[KryoWrite_3cyc_LS_Y_404ln],
2172 (instregex "STX(P(W|X)|R(B|H|W|X))")>;
2173 def KryoWrite_3cyc_XY_noRSV_160ln :
2174 SchedWriteRes<[KryoUnitXY]> {
2175 let Latency = 3; let NumMicroOps = 2;
2177 def : InstRW<[KryoWrite_3cyc_XY_noRSV_160ln],
2178 (instregex "^(SU|US)QADD(v8i8|v4i16|v2i32)")>;
2179 def KryoWrite_3cyc_XY_XY_167ln :
2180 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
2181 let Latency = 3; let NumMicroOps = 2;
2183 def : InstRW<[KryoWrite_3cyc_XY_XY_167ln],
2184 (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)")>;
2185 def KryoWrite_1cyc_XY_1ln :
2186 SchedWriteRes<[KryoUnitXY]> {
2187 let Latency = 1; let NumMicroOps = 1;
2189 def : InstRW<[KryoWrite_1cyc_XY_1ln, ReadI],
2190 (instregex "SUBS?(W|X)ri")>;
2191 def KryoWrite_2cyc_XY_XY_5ln :
2192 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
2193 let Latency = 2; let NumMicroOps = 2;
2195 def : InstRW<[KryoWrite_2cyc_XY_XY_5ln, ReadI, ReadIEReg],
2196 (instregex "SUBS?(W|X)rx")>;
2197 def KryoWrite_2cyc_XY_XY_5_1ln :
2198 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
2199 let Latency = 2; let NumMicroOps = 2;
2201 def : InstRW<[KryoWrite_2cyc_XY_XY_5_1ln, ReadI, ReadISReg],
2202 (instregex "SUBS?(W|X)rs")>;
2203 def KryoWrite_1cyc_XY_noRSV_6ln :
2204 SchedWriteRes<[KryoUnitXY]> {
2205 let Latency = 1; let NumMicroOps = 2;
2207 def : InstRW<[KryoWrite_1cyc_XY_noRSV_6ln, ReadI, ReadI],
2208 (instregex "SUBS?(W|X)rr")>;
2209 def KryoWrite_0cyc_LS_9ln :
2210 SchedWriteRes<[KryoUnitLS]> {
2211 let Latency = 0; let NumMicroOps = 1;
2213 def : InstRW<[KryoWrite_0cyc_LS_9ln],
2214 (instregex "SYSL?xt")>;
2215 def KryoWrite_1cyc_X_noRSV_205ln :
2216 SchedWriteRes<[KryoUnitX]> {
2217 let Latency = 1; let NumMicroOps = 2;
2219 def : InstRW<[KryoWrite_1cyc_X_noRSV_205ln],
2220 (instrs TBLv8i8One)>;
2221 def KryoWrite_1cyc_X_X_208ln :
2222 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
2223 let Latency = 1; let NumMicroOps = 2;
2225 def : InstRW<[KryoWrite_1cyc_X_X_208ln],
2226 (instrs TBLv16i8One)>;
2227 def KryoWrite_2cyc_X_X_X_noRSV_222ln :
2228 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX]> {
2229 let Latency = 2; let NumMicroOps = 4;
2231 def : InstRW<[KryoWrite_2cyc_X_X_X_noRSV_222ln],
2232 (instrs TBLv8i8Two)>;
2233 def KryoWrite_2cyc_X_X_X_X_X_X_224ln :
2234 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2236 let Latency = 2; let NumMicroOps = 6;
2238 def : InstRW<[KryoWrite_2cyc_X_X_X_X_X_X_224ln],
2239 (instrs TBLv16i8Two)>;
2240 def KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln :
2241 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {
2242 let Latency = 3; let NumMicroOps = 6;
2244 def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln],
2245 (instrs TBLv8i8Three)>;
2246 def KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln :
2247 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2248 KryoUnitX, KryoUnitX]> {
2249 let Latency = 3; let NumMicroOps = 8;
2251 def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln],
2252 (instrs TBLv8i8Four)>;
2253 def KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln :
2254 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2255 KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX,
2257 let Latency = 4; let NumMicroOps = 11;
2259 def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln],
2260 (instrs TBLv16i8Three)>;
2261 def KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln :
2262 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2263 KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2264 KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {
2265 let Latency = 4; let NumMicroOps = 15;
2267 def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln],
2268 (instrs TBLv16i8Four)>;
2269 def KryoWrite_2cyc_X_X_noRSV_220ln :
2270 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
2271 let Latency = 2; let NumMicroOps = 3;
2273 def : InstRW<[KryoWrite_2cyc_X_X_noRSV_220ln],
2274 (instrs TBXv8i8One)>;
2275 def KryoWrite_2cyc_X_X_X_X_221ln :
2276 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {
2277 let Latency = 2; let NumMicroOps = 4;
2279 def : InstRW<[KryoWrite_2cyc_X_X_X_X_221ln],
2280 (instrs TBXv16i8One)>;
2281 def KryoWrite_3cyc_X_X_X_X_noRSV_223ln :
2282 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {
2283 let Latency = 3; let NumMicroOps = 5;
2285 def : InstRW<[KryoWrite_3cyc_X_X_X_X_noRSV_223ln],
2286 (instrs TBXv8i8Two)>;
2287 def KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln :
2288 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2290 let Latency = 4; let NumMicroOps = 7;
2292 def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln],
2293 (instrs TBXv8i8Three)>;
2294 def KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln :
2295 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2296 KryoUnitX, KryoUnitX, KryoUnitX]> {
2297 let Latency = 3; let NumMicroOps = 8;
2299 def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln],
2300 (instrs TBXv16i8Two)>;
2301 def KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln :
2302 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2303 KryoUnitX, KryoUnitX, KryoUnitX]> {
2304 let Latency = 4; let NumMicroOps = 9;
2306 def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln],
2307 (instrs TBXv8i8Four)>;
2308 def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln :
2309 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2310 KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY,
2311 KryoUnitX, KryoUnitX, KryoUnitX]> {
2312 let Latency = 5; let NumMicroOps = 13;
2314 def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln],
2315 (instrs TBXv16i8Three)>;
2316 def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln :
2317 SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2318 KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,
2319 KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX,
2320 KryoUnitX, KryoUnitX]> {
2321 let Latency = 5; let NumMicroOps = 17;
2323 def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln],
2324 (instrs TBXv16i8Four)>;
2325 def KryoWrite_1cyc_XY_XY_217ln :
2326 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
2327 let Latency = 1; let NumMicroOps = 2;
2329 def : InstRW<[KryoWrite_1cyc_XY_XY_217ln],
2330 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2331 def KryoWrite_1cyc_X_X_211ln :
2332 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
2333 let Latency = 1; let NumMicroOps = 2;
2335 def : InstRW<[KryoWrite_1cyc_X_X_211ln],
2336 (instregex "(TRN1|TRN2)(v4i32|v8i16|v16i8)")>;
2337 def KryoWrite_1cyc_X_XY_213ln :
2338 SchedWriteRes<[KryoUnitX, KryoUnitXY]> {
2339 let Latency = 1; let NumMicroOps = 2;
2341 def : InstRW<[KryoWrite_1cyc_X_XY_213ln],
2342 (instregex "(TRN1|TRN2)(v2i32|v4i16|v8i8)")>;
2343 def KryoWrite_3cyc_XY_noRSV_156ln :
2344 SchedWriteRes<[KryoUnitXY]> {
2345 let Latency = 3; let NumMicroOps = 2;
2347 def : InstRW<[KryoWrite_3cyc_XY_noRSV_156ln],
2348 (instrs URECPEv2i32, URSQRTEv2i32)>;
2349 def KryoWrite_3cyc_XY_XY_168ln :
2350 SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {
2351 let Latency = 3; let NumMicroOps = 2;
2353 def : InstRW<[KryoWrite_3cyc_XY_XY_168ln],
2354 (instrs URECPEv4i32, URSQRTEv4i32)>;
2355 def KryoWrite_1cyc_X_X_210ln :
2356 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
2357 let Latency = 1; let NumMicroOps = 2;
2359 def : InstRW<[KryoWrite_1cyc_X_X_210ln],
2360 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2361 def KryoWrite_1cyc_X_noRSV_206ln :
2362 SchedWriteRes<[KryoUnitX]> {
2363 let Latency = 1; let NumMicroOps = 2;
2365 def : InstRW<[KryoWrite_1cyc_X_noRSV_206ln],
2366 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
2367 def KryoWrite_1cyc_XY_noRSV_215ln :
2368 SchedWriteRes<[KryoUnitXY]> {
2369 let Latency = 1; let NumMicroOps = 2;
2371 def : InstRW<[KryoWrite_1cyc_XY_noRSV_215ln],
2372 (instregex "XTNv.*")>;
2373 def KryoWrite_1cyc_X_X_209ln :
2374 SchedWriteRes<[KryoUnitX, KryoUnitX]> {
2375 let Latency = 1; let NumMicroOps = 2;
2377 def : InstRW<[KryoWrite_1cyc_X_X_209ln],
2378 (instregex "ZIP1(v4i32|v8i16|v16i8)")>;