contrib/llvm/lib/Target/AArch64/AArch64SchedM1.td

   1 //=- AArch64SchedM1.td - Samsung Exynos-M1 Scheduling Defs ---*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Samsung Exynos-M1 to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // The Exynos-M1 is a traditional superscalar microprocessor with a
  17 // 4-wide in-order stage for decode and dispatch and a wider issue stage.
  18 // The execution units and loads and stores are out-of-order.
  19
  20 def ExynosM1Model : SchedMachineModel {
  21   let IssueWidth            =  4; // Up to 4 uops per cycle.
  22   let MicroOpBufferSize     = 96; // ROB size.
  23   let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
  24   let LoadLatency           =  4; // Optimistic load cases.
  25   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
  26   let CompleteModel         =  1; // Use the default model otherwise.
  27
  28   list<Predicate> UnsupportedFeatures = [HasSVE];
  29 }
  30
  31 //===----------------------------------------------------------------------===//
  32 // Define each kind of processor resource and number available on the Exynos-M1,
  33 // which has 9 pipelines, each with its own queue with out-of-order dispatch.
  34
  35 def M1UnitA  : ProcResource<2>; // Simple integer
  36 def M1UnitC  : ProcResource<1>; // Simple and complex integer
  37 def M1UnitD  : ProcResource<1>; // Integer division (inside C, serialized)
  38 def M1UnitB  : ProcResource<2>; // Branch
  39 def M1UnitL  : ProcResource<1>; // Load
  40 def M1UnitS  : ProcResource<1>; // Store
  41 def M1PipeF0 : ProcResource<1>; // FP #0
  42 let Super = M1PipeF0 in {
  43   def M1UnitFMAC   : ProcResource<1>; // FP multiplication
  44   def M1UnitNAL0   : ProcResource<1>; // Simple vector
  45   def M1UnitNMISC  : ProcResource<1>; // Miscellanea
  46   def M1UnitFCVT   : ProcResource<1>; // FP conversion
  47   def M1UnitNCRYPT : ProcResource<1>; // Cryptographic
  48 }
  49 def M1PipeF1 : ProcResource<1>; // FP #1
  50 let Super = M1PipeF1 in {
  51   def M1UnitFADD : ProcResource<1>; // Simple FP
  52   def M1UnitNAL1 : ProcResource<1>; // Simple vector
  53   def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized)
  54   def M1UnitFST  : ProcResource<1>; // FP store
  55 }
  56
  57 let SchedModel = ExynosM1Model in {
  58   def M1UnitALU  : ProcResGroup<[M1UnitA,
  59                                  M1UnitC]>;    // All integer
  60   def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
  61                                  M1UnitNAL1]>; // All simple vector
  62 }
  63
  64 let SchedModel = ExynosM1Model in {
  65
  66 //===----------------------------------------------------------------------===//
  67 // Predicates.
  68
  69 def M1BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
  70                                             MI->getOperand(0).getReg() != AArch64::LR}]>;
  71 def M1ShiftLeftFastPred  : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
  72
  73 //===----------------------------------------------------------------------===//
  74 // Coarse scheduling model.
  75
  76 def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
  77 def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
  78 def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2;
  79                                              let ResourceCycles = [2]; }
  80 def M1WriteAB : SchedWriteRes<[M1UnitALU,
  81                                M1UnitC]>   { let Latency = 1;
  82                                              let NumMicroOps = 2; }
  83 def M1WriteAC : SchedWriteRes<[M1UnitALU,
  84                                M1UnitALU,
  85                                M1UnitC]>   { let Latency = 2;
  86                                              let NumMicroOps = 3; }
  87 def M1WriteAD : SchedWriteRes<[M1UnitALU,
  88                                M1UnitC]>   { let Latency = 2;
  89                                              let NumMicroOps = 2; }
  90 def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteA1]>,
  91                                    SchedVar<NoSchedPred,         [M1WriteAA]>]>;
  92 def M1WriteC1 : SchedWriteRes<[M1UnitC]>   { let Latency = 1; }
  93 def M1WriteC2 : SchedWriteRes<[M1UnitC]>   { let Latency = 2; }
  94
  95 def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
  96 def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteAB]>,
  97                                    SchedVar<NoSchedPred,          [M1WriteAC]>]>;
  98
  99 def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
 100 def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
 101 def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6;
 102                                            let ResourceCycles = [2]; }
 103 def M1WriteLB : SchedWriteRes<[M1UnitL,
 104                                M1UnitA]> { let Latency = 4;
 105                                            let NumMicroOps = 2; }
 106 def M1WriteLC : SchedWriteRes<[M1UnitL,
 107                                M1UnitA]> { let Latency = 5;
 108                                            let NumMicroOps = 2; }
 109 def M1WriteLD : SchedWriteRes<[M1UnitL,
 110                                M1UnitA]> { let Latency = 6;
 111                                            let NumMicroOps = 2;
 112                                            let ResourceCycles = [2]; }
 113 def M1WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 114                                            let NumMicroOps = 0; }
 115 def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
 116                                    SchedVar<NoSchedPred,         [M1WriteLC]>]>;
 117 def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
 118                                    SchedVar<NoSchedPred,         [M1WriteLD]>]>;
 119
 120 def M1WriteS1 : SchedWriteRes<[M1UnitS]>   { let Latency = 1; }
 121 def M1WriteS3 : SchedWriteRes<[M1UnitS]>   { let Latency = 3; }
 122 def M1WriteS4 : SchedWriteRes<[M1UnitS]>   { let Latency = 4; }
 123 def M1WriteSA : SchedWriteRes<[M1UnitS,
 124                                M1UnitFST,
 125                                M1UnitS,
 126                                M1UnitFST]> { let Latency = 1;
 127                                              let NumMicroOps = 2; }
 128 def M1WriteSB : SchedWriteRes<[M1UnitS,
 129                                M1UnitFST,
 130                                M1UnitA]>   { let Latency = 3;
 131                                              let NumMicroOps = 2; }
 132 def M1WriteSC : SchedWriteRes<[M1UnitS,
 133                                M1UnitFST,
 134                                M1UnitS,
 135                                M1UnitFST,
 136                                M1UnitA]>   { let Latency = 3;
 137                                              let NumMicroOps = 3; }
 138 def M1WriteSD : SchedWriteRes<[M1UnitS,
 139                                M1UnitFST,
 140                                M1UnitA]>   { let Latency = 1;
 141                                              let NumMicroOps = 2; }
 142 def M1WriteSE : SchedWriteRes<[M1UnitS,
 143                                M1UnitA]>   { let Latency = 2;
 144                                              let NumMicroOps = 2; }
 145 def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
 146                                    SchedVar<NoSchedPred,         [M1WriteSE]>]>;
 147 def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
 148                                    SchedVar<NoSchedPred,         [M1WriteSB]>]>;
 149
 150 def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
 151                                       SchedVar<NoSchedPred,   [ReadDefault]>]>;
 152
 153 // Branch instructions.
 154 def : WriteRes<WriteBr,    []>        { let Latency = 0; }
 155 def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
 156
 157 // Arithmetic and logical integer instructions.
 158 def : WriteRes<WriteI,     [M1UnitALU]> { let Latency = 1; }
 159 def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
 160 def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
 161 def : WriteRes<WriteIS,    [M1UnitALU]> { let Latency = 1; }
 162
 163 // Move instructions.
 164 def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
 165
 166 // Divide and multiply instructions.
 167 def : WriteRes<WriteID32, [M1UnitC,
 168                            M1UnitD]> { let Latency = 13;
 169                                        let ResourceCycles = [1, 13]; }
 170 def : WriteRes<WriteID64, [M1UnitC,
 171                            M1UnitD]> { let Latency = 21;
 172                                        let ResourceCycles = [1, 21]; }
 173 // TODO: Long multiplication take 5 cycles and also the ALU.
 174 def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
 175 def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4;
 176                                        let ResourceCycles = [2]; }
 177
 178 // Miscellaneous instructions.
 179 def : WriteRes<WriteExtr, [M1UnitALU,
 180                            M1UnitALU]> { let Latency = 2;
 181                                          let NumMicroOps = 2; }
 182
 183 // Addressing modes.
 184 def : WriteRes<WriteAdr, []> { let Latency = 1;
 185                                let NumMicroOps = 0; }
 186 def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
 187
 188 // Load instructions.
 189 def : WriteRes<WriteLD,    [M1UnitL]>   { let Latency = 4; }
 190 def : WriteRes<WriteLDHi,  []>          { let Latency = 4;
 191                                           let NumMicroOps = 0; }
 192 def : SchedAlias<WriteLDIdx, M1WriteLX>;
 193
 194 // Store instructions.
 195 def : WriteRes<WriteST,    [M1UnitS]> { let Latency = 1; }
 196 def : WriteRes<WriteSTP,   [M1UnitS]> { let Latency = 1; }
 197 def : WriteRes<WriteSTX,   [M1UnitS]> { let Latency = 1; }
 198 def : SchedAlias<WriteSTIdx, M1WriteSX>;
 199
 200 // FP data instructions.
 201 def : WriteRes<WriteF,    [M1UnitFADD]>  { let Latency = 3; }
 202 def : WriteRes<WriteFCmp, [M1UnitNMISC]> { let Latency = 4; }
 203 def : WriteRes<WriteFDiv, [M1UnitFVAR]>  { let Latency = 15;
 204                                            let ResourceCycles = [15]; }
 205 def : WriteRes<WriteFMul, [M1UnitFMAC]>  { let Latency = 4; }
 206
 207 // FP miscellaneous instructions.
 208 def : WriteRes<WriteFCvt,  [M1UnitFCVT]> { let Latency = 3; }
 209 def : WriteRes<WriteFImm,  [M1UnitNALU]> { let Latency = 1; }
 210 def : WriteRes<WriteFCopy, [M1UnitS]>    { let Latency = 4; }
 211
 212 // FP load instructions.
 213 def : WriteRes<WriteVLD,   [M1UnitL]> { let Latency = 5; }
 214
 215 // FP store instructions.
 216 def : WriteRes<WriteVST, [M1UnitS,
 217                           M1UnitFST]> { let Latency = 1;
 218                                         let NumMicroOps = 1; }
 219
 220 // ASIMD FP instructions.
 221 def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
 222
 223 // Other miscellaneous instructions.
 224 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 225 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 226 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 227 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 228
 229 //===----------------------------------------------------------------------===//
 230 // Fast forwarding.
 231
 232 // TODO: Add FP register forwarding rules.
 233 def : ReadAdvance<ReadI,       0>;
 234 def : ReadAdvance<ReadISReg,   0>;
 235 def : ReadAdvance<ReadIEReg,   0>;
 236 def : ReadAdvance<ReadIM,      0>;
 237 // TODO: The forwarding for WriteIM32 saves actually 2 cycles.
 238 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 239 def : ReadAdvance<ReadID,      0>;
 240 def : ReadAdvance<ReadExtrHi,  0>;
 241 def : ReadAdvance<ReadAdrBase, 0>;
 242 def : ReadAdvance<ReadVLD,     0>;
 243
 244 //===----------------------------------------------------------------------===//
 245 // Finer scheduling model.
 246
 247 def M1WriteNEONA   : SchedWriteRes<[M1UnitNALU,
 248                                     M1UnitNALU,
 249                                     M1UnitFADD]>   { let Latency = 9;
 250                                                      let NumMicroOps = 3; }
 251 def M1WriteNEONB   : SchedWriteRes<[M1UnitNALU,
 252                                     M1UnitFST]>    { let Latency = 5;
 253                                                      let NumMicroOps = 2;}
 254 def M1WriteNEONC   : SchedWriteRes<[M1UnitNALU,
 255                                     M1UnitFST]>    { let Latency = 6;
 256                                                      let NumMicroOps = 2; }
 257 def M1WriteNEOND   : SchedWriteRes<[M1UnitNALU,
 258                                     M1UnitFST,
 259                                     M1UnitL]>      { let Latency = 10;
 260                                                      let NumMicroOps = 3; }
 261 def M1WriteNEONE   : SchedWriteRes<[M1UnitFCVT,
 262                                     M1UnitFST]>    { let Latency = 8;
 263                                                      let NumMicroOps = 2; }
 264 def M1WriteNEONF   : SchedWriteRes<[M1UnitFCVT,
 265                                     M1UnitFST,
 266                                     M1UnitL]>      { let Latency = 13;
 267                                                      let NumMicroOps = 3; }
 268 def M1WriteNEONG   : SchedWriteRes<[M1UnitNMISC,
 269                                     M1UnitFST]>    { let Latency = 6;
 270                                                      let NumMicroOps = 2; }
 271 def M1WriteNEONH   : SchedWriteRes<[M1UnitNALU,
 272                                     M1UnitFST]>    { let Latency = 3;
 273                                                      let NumMicroOps = 2; }
 274 def M1WriteNEONI   : SchedWriteRes<[M1UnitFST,
 275                                     M1UnitL]>      { let Latency = 9;
 276                                                      let NumMicroOps = 2; }
 277 def M1WriteNEONJ   : SchedWriteRes<[M1UnitNMISC,
 278                                     M1UnitFMAC]>   { let Latency = 6;
 279                                                      let NumMicroOps = 2; }
 280 def M1WriteNEONK   : SchedWriteRes<[M1UnitNMISC,
 281                                     M1UnitFMAC]>   { let Latency = 7;
 282                                                      let NumMicroOps = 2; }
 283 def M1WriteNEONL   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2;
 284                                                      let ResourceCycles = [2]; }
 285 def M1WriteFADD3   : SchedWriteRes<[M1UnitFADD]>   { let Latency = 3; }
 286 def M1WriteFCVT3   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 3; }
 287 def M1WriteFCVT4   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 4; }
 288 def M1WriteFMAC4   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 4; }
 289 def M1WriteFMAC5   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 5; }
 290 // TODO
 291 def M1WriteFVAR15  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 15;
 292                                                      let ResourceCycles = [15]; }
 293 def M1WriteFVAR23  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 23;
 294                                                      let ResourceCycles = [23]; }
 295 def M1WriteNALU1   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 1; }
 296 def M1WriteNALU2   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2; }
 297 def M1WriteNAL11   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 1; }
 298 def M1WriteNAL12   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 2; }
 299 def M1WriteNAL13   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 3; }
 300 def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
 301 def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; }
 302 def M1WriteNMISC1  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 1; }
 303 def M1WriteNMISC2  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 2; }
 304 def M1WriteNMISC3  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 3; }
 305 def M1WriteNMISC4  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 4; }
 306 def M1WriteTB      : SchedWriteRes<[M1UnitC,
 307                                     M1UnitALU]>    { let Latency = 2;
 308                                                      let NumMicroOps = 2; }
 309 def M1WriteVLDA    : SchedWriteRes<[M1UnitL,
 310                                     M1UnitL]>      { let Latency = 6;
 311                                                      let NumMicroOps = 2; }
 312 def M1WriteVLDB    : SchedWriteRes<[M1UnitL,
 313                                     M1UnitL,
 314                                     M1UnitL]>      { let Latency = 7;
 315                                                      let NumMicroOps = 3; }
 316 def M1WriteVLDC    : SchedWriteRes<[M1UnitL,
 317                                     M1UnitL,
 318                                     M1UnitL,
 319                                     M1UnitL]>      { let Latency = 8;
 320                                                      let NumMicroOps = 4; }
 321 def M1WriteVLDD    : SchedWriteRes<[M1UnitL,
 322                                     M1UnitNALU]>   { let Latency = 7;
 323                                                      let NumMicroOps = 2;
 324                                                      let ResourceCycles = [2]; }
 325 def M1WriteVLDE    : SchedWriteRes<[M1UnitL,
 326                                     M1UnitNALU]>   { let Latency = 6;
 327                                                      let NumMicroOps = 2; }
 328 def M1WriteVLDF    : SchedWriteRes<[M1UnitL,
 329                                     M1UnitL]>      { let Latency = 10;
 330                                                      let NumMicroOps = 2;
 331                                                      let ResourceCycles = [5]; }
 332 def M1WriteVLDG    : SchedWriteRes<[M1UnitL,
 333                                     M1UnitNALU,
 334                                     M1UnitNALU]>   { let Latency = 7;
 335                                                      let NumMicroOps = 3;
 336                                                      let ResourceCycles = [2]; }
 337 def M1WriteVLDH    : SchedWriteRes<[M1UnitL,
 338                                     M1UnitNALU,
 339                                     M1UnitNALU]>   { let Latency = 6;
 340                                                      let NumMicroOps = 3; }
 341 def M1WriteVLDI    : SchedWriteRes<[M1UnitL,
 342                                     M1UnitL,
 343                                     M1UnitL]>      { let Latency = 12;
 344                                                      let NumMicroOps = 3;
 345                                                      let ResourceCycles = [6]; }
 346 def M1WriteVLDJ    : SchedWriteRes<[M1UnitL,
 347                                     M1UnitNALU,
 348                                     M1UnitNALU,
 349                                     M1UnitNALU]>   { let Latency = 9;
 350                                                      let NumMicroOps = 4;
 351                                                      let ResourceCycles = [4]; }
 352 def M1WriteVLDK    : SchedWriteRes<[M1UnitL,
 353                                     M1UnitNALU,
 354                                     M1UnitNALU,
 355                                     M1UnitNALU,
 356                                     M1UnitNALU]>   { let Latency = 9;
 357                                                      let NumMicroOps = 5;
 358                                                      let ResourceCycles = [4]; }
 359 def M1WriteVLDL    : SchedWriteRes<[M1UnitL,
 360                                     M1UnitNALU,
 361                                     M1UnitNALU,
 362                                     M1UnitL,
 363                                     M1UnitNALU]>   { let Latency = 7;
 364                                                      let NumMicroOps = 5;
 365                                                      let ResourceCycles = [2]; }
 366 def M1WriteVLDM    : SchedWriteRes<[M1UnitL,
 367                                     M1UnitNALU,
 368                                     M1UnitNALU,
 369                                     M1UnitL,
 370                                     M1UnitNALU,
 371                                     M1UnitNALU]>   { let Latency = 7;
 372                                                      let NumMicroOps = 6;
 373                                                      let ResourceCycles = [2]; }
 374 def M1WriteVLDN    : SchedWriteRes<[M1UnitL,
 375                                     M1UnitL,
 376                                     M1UnitL,
 377                                     M1UnitL]>      { let Latency = 14;
 378                                                      let NumMicroOps = 4;
 379                                                      let ResourceCycles = [7]; }
 380 def M1WriteVSTA    : WriteSequence<[WriteVST], 2>;
 381 def M1WriteVSTB    : WriteSequence<[WriteVST], 3>;
 382 def M1WriteVSTC    : WriteSequence<[WriteVST], 4>;
 383 def M1WriteVSTD    : SchedWriteRes<[M1UnitS,
 384                                     M1UnitFST,
 385                                     M1UnitFST]>    { let Latency = 7;
 386                                                      let NumMicroOps = 2;
 387                                                      let ResourceCycles = [7]; }
 388 def M1WriteVSTE    : SchedWriteRes<[M1UnitS,
 389                                     M1UnitFST,
 390                                     M1UnitS,
 391                                     M1UnitFST,
 392                                     M1UnitFST]>    { let Latency = 8;
 393                                                      let NumMicroOps = 3;
 394                                                      let ResourceCycles = [8]; }
 395 def M1WriteVSTF    : SchedWriteRes<[M1UnitNALU,
 396                                     M1UnitS,
 397                                     M1UnitFST,
 398                                     M1UnitS,
 399                                     M1UnitFST,
 400                                     M1UnitFST,
 401                                     M1UnitFST]>     { let Latency = 15;
 402                                                       let NumMicroOps = 5;
 403                                                       let ResourceCycles = [15]; }
 404 def M1WriteVSTG    : SchedWriteRes<[M1UnitNALU,
 405                                     M1UnitS,
 406                                     M1UnitFST,
 407                                     M1UnitS,
 408                                     M1UnitFST,
 409                                     M1UnitS,
 410                                     M1UnitFST,
 411                                     M1UnitFST,
 412                                     M1UnitFST]>     { let Latency = 16;
 413                                                       let NumMicroOps = 6;
 414                                                       let ResourceCycles = [16]; }
 415 def M1WriteVSTH    : SchedWriteRes<[M1UnitNALU,
 416                                     M1UnitS,
 417                                     M1UnitFST,
 418                                     M1UnitFST,
 419                                     M1UnitFST]>      { let Latency = 14;
 420                                                        let NumMicroOps = 4;
 421                                                        let ResourceCycles = [14]; }
 422 def M1WriteVSTI    : SchedWriteRes<[M1UnitNALU,
 423                                     M1UnitS,
 424                                     M1UnitFST,
 425                                     M1UnitS,
 426                                     M1UnitFST,
 427                                     M1UnitS,
 428                                     M1UnitFST,
 429                                     M1UnitS,
 430                                     M1UnitFST,
 431                                     M1UnitFST,
 432                                     M1UnitFST]>      { let Latency = 17;
 433                                                        let NumMicroOps = 7;
 434                                                        let ResourceCycles = [17]; }
 435
 436 // Branch instructions
 437 def : InstRW<[M1WriteB1], (instrs Bcc)>;
 438 def : InstRW<[M1WriteA1], (instrs BL)>;
 439 def : InstRW<[M1WriteBX], (instrs BLR)>;
 440 def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
 441 def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>;
 442
 443 // Arithmetic and logical integer instructions.
 444 def : InstRW<[M1WriteA1], (instrs COPY)>;
 445 def : InstRW<[M1WriteAX], (instregex ".+r[sx](64)?$")>;
 446
 447 // Divide and multiply instructions.
 448
 449 // Miscellaneous instructions.
 450
 451 // Load instructions.
 452 def : InstRW<[M1WriteLB,
 453               WriteLDHi,
 454               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 455 def : InstRW<[M1WriteLX,
 456               ReadAdrBase], (instregex "^PRFMro[WX]")>;
 457
 458 // Store instructions.
 459
 460 // FP data instructions.
 461 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)[DS]r")>;
 462 def : InstRW<[M1WriteFADD3],  (instregex "^F(ADD|SUB)[DS]rr")>;
 463 def : InstRW<[M1WriteNEONG],  (instregex "^FCCMPE?[DS]rr")>;
 464 def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>;
 465 def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>;
 466 def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>;
 467 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>;
 468 def : InstRW<[M1WriteFMAC4],  (instregex "^FN?MUL[DS]rr")>;
 469 def : InstRW<[M1WriteFMAC5],  (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 470 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT.+r")>;
 471 def : InstRW<[M1WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 472 def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>;
 473 def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>;
 474
 475 // FP miscellaneous instructions.
 476 def : InstRW<[M1WriteFCVT3],  (instregex "^FCVT[DS][DS]r")>;
 477 def : InstRW<[M1WriteNEONF],  (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
 478 def : InstRW<[M1WriteNEONE],  (instregex "^[SU]CVTF[SU]")>;
 479 def : InstRW<[M1WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 480 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 481 def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>;
 482 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 483 def : InstRW<[M1WriteS4],     (instregex "^FMOV[WX][DS](High)?r")>;
 484 def : InstRW<[M1WriteNEONI],  (instregex "^FMOV[DS][WX](High)?r")>;
 485
 486 // FP load instructions.
 487 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 488 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 489 def : InstRW<[WriteVLD,
 490               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 491 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 492 def : InstRW<[M1WriteLY,
 493               ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
 494 def : InstRW<[M1WriteLD,
 495               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 496 def : InstRW<[WriteVLD,
 497               M1WriteLH],   (instregex "^LDN?P[DS]i")>;
 498 def : InstRW<[M1WriteLA,
 499               M1WriteLH],   (instregex "^LDN?PQi")>;
 500 def : InstRW<[M1WriteLC,
 501               M1WriteLH,
 502               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 503 def : InstRW<[M1WriteLD,
 504               M1WriteLH,
 505               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 506
 507 // FP store instructions.
 508 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 509 def : InstRW<[WriteVST,
 510               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 511 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 512 def : InstRW<[M1WriteSY,
 513               ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
 514 def : InstRW<[M1WriteSB,
 515               ReadAdrBase], (instregex "^STRQro[WX]")>;
 516 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 517 def : InstRW<[WriteVST,
 518               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 519 def : InstRW<[M1WriteSC,
 520               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 521
 522 // ASIMD instructions.
 523 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
 524 def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>;
 525 def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>;
 526 def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>;
 527 def : InstRW<[M1WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 528 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>;
 529 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>;
 530 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>;
 531 def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>;
 532 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>;
 533 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>;
 534 def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 535 def : InstRW<[M1WriteNALU1],  (instregex "^CMTSTv")>;
 536 def : InstRW<[M1WriteNALU1],  (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 537 def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>;
 538 def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>;
 539 def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>;
 540 def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>;
 541 def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>;
 542 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>;
 543 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>;
 544 def : InstRW<[M1WriteNAL13],  (instregex "^(S|SR|U|UR)SRAv")>;
 545 def : InstRW<[M1WriteNALU1],  (instregex "^SHL[dv]")>;
 546 def : InstRW<[M1WriteNALU1],  (instregex "^[SU]SH[LR][dv]")>;
 547 def : InstRW<[M1WriteNALU1],  (instregex "^S[RS]I[dv]")>;
 548 def : InstRW<[M1WriteNAL13],  (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 549 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]RSH[LR][dv]")>;
 550 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 551
 552 // ASIMD FP instructions.
 553 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)v")>;
 554 def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>;
 555 def : InstRW<[M1WriteNEONA],  (instregex "^FADDP")>;
 556 def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 557 def : InstRW<[M1WriteFCVT3],  (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>;
 558 def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>;
 559 def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>;
 560 def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>;
 561 def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>;
 562 def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>;
 563 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
 564 def : InstRW<[M1WriteNEONJ],  (instregex "^FMULX?v.i")>;
 565 def : InstRW<[M1WriteFMAC4],  (instregex "^FMULX?v.f")>;
 566 def : InstRW<[M1WriteNEONK],  (instregex "^FML[AS]v.i")>;
 567 def : InstRW<[M1WriteFMAC5],  (instregex "^FML[AS]v.f")>;
 568 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT[AIMNPXZ]v")>;
 569
 570 // ASIMD miscellaneous instructions.
 571 def : InstRW<[M1WriteNALU1],  (instregex "^RBITv")>;
 572 def : InstRW<[M1WriteNAL11],  (instregex "^(BIF|BIT|BSL)v")>;
 573 def : InstRW<[M1WriteNEONB],  (instregex "^DUPv.+gpr")>;
 574 def : InstRW<[M1WriteNALU1],  (instregex "^DUPv.+lane")>;
 575 def : InstRW<[M1WriteNALU1],  (instregex "^EXTv8")>;
 576 def : InstRW<[M1WriteNEONL],  (instregex "^EXTv16")>;
 577 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]?Q?XTU?Nv")>;
 578 def : InstRW<[M1WriteNALU1],  (instregex "^CPY")>;
 579 def : InstRW<[M1WriteNALU1],  (instregex "^INSv.+lane")>;
 580 def : InstRW<[M1WriteNALU1],  (instregex "^MOVI[Dv]")>;
 581 def : InstRW<[M1WriteNALU1],  (instregex "^FMOVv")>;
 582 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 583 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)Sv")>;
 584 def : InstRW<[M1WriteNALU1],  (instregex "^REV(16|32|64)v")>;
 585 def : InstRW<[M1WriteNAL11],  (instregex "^TB[LX]v8i8One")>;
 586 def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
 587                               (instregex "^TB[LX]v8i8Two")>;
 588 def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
 589                               (instregex "^TB[LX]v8i8Three")>;
 590 def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
 591                               (instregex "^TB[LX]v8i8Four")>;
 592 def : InstRW<[M1WriteNAL12],  (instregex "^TB[LX]v16i8One")>;
 593 def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
 594                               (instregex "^TB[LX]v16i8Two")>;
 595 def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
 596                               (instregex "^TB[LX]v16i8Three")>;
 597 def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
 598                               (instregex "^TB[LX]v16i8Four")>;
 599 def : InstRW<[M1WriteNEOND],  (instregex "^[SU]MOVv")>;
 600 def : InstRW<[M1WriteNEONC],  (instregex "^INSv.+gpr")>;
 601 def : InstRW<[M1WriteNALU1],  (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>;
 602 def : InstRW<[M1WriteNALU2],  (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>;
 603 def : InstRW<[M1WriteNALU1],  (instregex "^ZIP[12]v")>;
 604
 605 // ASIMD load instructions.
 606 def : InstRW<[M1WriteVLDD],   (instregex "LD1i(8|16|32)$")>;
 607 def : InstRW<[M1WriteVLDD,
 608               WriteAdr],      (instregex "LD1i(8|16|32)_POST$")>;
 609 def : InstRW<[M1WriteVLDE],   (instregex "LD1i(64)$")>;
 610 def : InstRW<[M1WriteVLDE,
 611               WriteAdr],      (instregex "LD1i(64)_POST$")>;
 612
 613 def : InstRW<[M1WriteL5],     (instregex "LD1Rv(8b|4h|2s)$")>;
 614 def : InstRW<[M1WriteL5,
 615               WriteAdr],      (instregex "LD1Rv(8b|4h|2s)_POST$")>;
 616 def : InstRW<[M1WriteL5],     (instregex "LD1Rv(1d)$")>;
 617 def : InstRW<[M1WriteL5,
 618               WriteAdr],      (instregex "LD1Rv(1d)_POST$")>;
 619 def : InstRW<[M1WriteL5],     (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 620 def : InstRW<[M1WriteL5,
 621               WriteAdr],      (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 622
 623 def : InstRW<[M1WriteL5],     (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 624 def : InstRW<[M1WriteL5,
 625               WriteAdr],      (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 626 def : InstRW<[M1WriteL5],     (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 627 def : InstRW<[M1WriteL5,
 628               WriteAdr],      (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 629 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 630 def : InstRW<[M1WriteVLDA,
 631               WriteAdr],      (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 632 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 633 def : InstRW<[M1WriteVLDA,
 634               WriteAdr],      (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 635 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 636 def : InstRW<[M1WriteVLDB,
 637               WriteAdr],      (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 638 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 639 def : InstRW<[M1WriteVLDB,
 640               WriteAdr],      (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 641 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 642 def : InstRW<[M1WriteVLDC,
 643               WriteAdr],      (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 644 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 645 def : InstRW<[M1WriteVLDC,
 646               WriteAdr],      (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 647
 648 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(8|16)$")>;
 649 def : InstRW<[M1WriteVLDG,
 650               WriteAdr],      (instregex "LD2i(8|16)_POST$")>;
 651 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(32)$")>;
 652 def : InstRW<[M1WriteVLDG,
 653               WriteAdr],      (instregex "LD2i(32)_POST$")>;
 654 def : InstRW<[M1WriteVLDH],   (instregex "LD2i(64)$")>;
 655 def : InstRW<[M1WriteVLDH,
 656               WriteAdr],      (instregex "LD2i(64)_POST$")>;
 657
 658 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(8b|4h|2s)$")>;
 659 def : InstRW<[M1WriteVLDA,
 660               WriteAdr],      (instregex "LD2Rv(8b|4h|2s)_POST$")>;
 661 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(1d)$")>;
 662 def : InstRW<[M1WriteVLDA,
 663               WriteAdr],      (instregex "LD2Rv(1d)_POST$")>;
 664 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 665 def : InstRW<[M1WriteVLDA,
 666               WriteAdr],      (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 667
 668 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(8b|4h|2s)$")>;
 669 def : InstRW<[M1WriteVLDF,
 670               WriteAdr],      (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 671 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(16b|8h|4s)$")>;
 672 def : InstRW<[M1WriteVLDF,
 673               WriteAdr],      (instregex "LD2Twov(16b|8h|4s)_POST$")>;
 674 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(2d)$")>;
 675 def : InstRW<[M1WriteVLDF,
 676               WriteAdr],      (instregex "LD2Twov(2d)_POST$")>;
 677
 678 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(8|16)$")>;
 679 def : InstRW<[M1WriteVLDJ,
 680               WriteAdr],      (instregex "LD3i(8|16)_POST$")>;
 681 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(32)$")>;
 682 def : InstRW<[M1WriteVLDJ,
 683               WriteAdr],      (instregex "LD3i(32)_POST$")>;
 684 def : InstRW<[M1WriteVLDL],   (instregex "LD3i(64)$")>;
 685 def : InstRW<[M1WriteVLDL,
 686               WriteAdr],      (instregex "LD3i(64)_POST$")>;
 687
 688 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(8b|4h|2s)$")>;
 689 def : InstRW<[M1WriteVLDB,
 690               WriteAdr],      (instregex "LD3Rv(8b|4h|2s)_POST$")>;
 691 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(1d)$")>;
 692 def : InstRW<[M1WriteVLDB,
 693               WriteAdr],      (instregex "LD3Rv(1d)_POST$")>;
 694 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(16b|8h|4s)$")>;
 695 def : InstRW<[M1WriteVLDB,
 696               WriteAdr],      (instregex "LD3Rv(16b|8h|4s)_POST$")>;
 697 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(2d)$")>;
 698 def : InstRW<[M1WriteVLDB,
 699               WriteAdr],      (instregex "LD3Rv(2d)_POST$")>;
 700
 701 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(8b|4h|2s)$")>;
 702 def : InstRW<[M1WriteVLDI,
 703               WriteAdr],      (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 704 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(16b|8h|4s)$")>;
 705 def : InstRW<[M1WriteVLDI,
 706               WriteAdr],      (instregex "LD3Threev(16b|8h|4s)_POST$")>;
 707 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(2d)$")>;
 708 def : InstRW<[M1WriteVLDI,
 709               WriteAdr],      (instregex "LD3Threev(2d)_POST$")>;
 710
 711 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(8|16)$")>;
 712 def : InstRW<[M1WriteVLDK,
 713               WriteAdr],      (instregex "LD4i(8|16)_POST$")>;
 714 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(32)$")>;
 715 def : InstRW<[M1WriteVLDK,
 716               WriteAdr],      (instregex "LD4i(32)_POST$")>;
 717 def : InstRW<[M1WriteVLDM],   (instregex "LD4i(64)$")>;
 718 def : InstRW<[M1WriteVLDM,
 719               WriteAdr],      (instregex "LD4i(64)_POST$")>;
 720
 721 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(8b|4h|2s)$")>;
 722 def : InstRW<[M1WriteVLDC,
 723               WriteAdr],      (instregex "LD4Rv(8b|4h|2s)_POST$")>;
 724 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(1d)$")>;
 725 def : InstRW<[M1WriteVLDC,
 726               WriteAdr],      (instregex "LD4Rv(1d)_POST$")>;
 727 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(16b|8h|4s)$")>;
 728 def : InstRW<[M1WriteVLDC,
 729               WriteAdr],      (instregex "LD4Rv(16b|8h|4s)_POST$")>;
 730 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(2d)$")>;
 731 def : InstRW<[M1WriteVLDC,
 732               WriteAdr],      (instregex "LD4Rv(2d)_POST$")>;
 733
 734 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(8b|4h|2s)$")>;
 735 def : InstRW<[M1WriteVLDN,
 736               WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 737 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(16b|8h|4s)$")>;
 738 def : InstRW<[M1WriteVLDN,
 739               WriteAdr],      (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
 740 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(2d)$")>;
 741 def : InstRW<[M1WriteVLDN,
 742               WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
 743
 744 // ASIMD store instructions.
 745 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(8|16|32)$")>;
 746 def : InstRW<[M1WriteVSTD,
 747               WriteAdr],      (instregex "ST1i(8|16|32)_POST$")>;
 748 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(64)$")>;
 749 def : InstRW<[M1WriteVSTD,
 750               WriteAdr],      (instregex "ST1i(64)_POST$")>;
 751
 752 def : InstRW<[WriteVST],      (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 753 def : InstRW<[WriteVST,
 754               WriteAdr],      (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 755 def : InstRW<[WriteVST],      (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 756 def : InstRW<[WriteVST,
 757               WriteAdr],      (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 758 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 759 def : InstRW<[M1WriteVSTA,
 760               WriteAdr],      (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 761 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 762 def : InstRW<[M1WriteVSTA,
 763               WriteAdr],      (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 764 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 765 def : InstRW<[M1WriteVSTB,
 766               WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 767 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 768 def : InstRW<[M1WriteVSTB,
 769               WriteAdr],      (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 770 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 771 def : InstRW<[M1WriteVSTC,
 772               WriteAdr],      (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 773 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 774 def : InstRW<[M1WriteVSTC,
 775               WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 776
 777 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(8|16|32)$")>;
 778 def : InstRW<[M1WriteVSTD,
 779               WriteAdr],      (instregex "ST2i(8|16|32)_POST$")>;
 780 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(64)$")>;
 781 def : InstRW<[M1WriteVSTD,
 782               WriteAdr],      (instregex "ST2i(64)_POST$")>;
 783
 784 def : InstRW<[M1WriteVSTD],   (instregex "ST2Twov(8b|4h|2s)$")>;
 785 def : InstRW<[M1WriteVSTD,
 786               WriteAdr],      (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 787 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(16b|8h|4s)$")>;
 788 def : InstRW<[M1WriteVSTE,
 789               WriteAdr],      (instregex "ST2Twov(16b|8h|4s)_POST$")>;
 790 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(2d)$")>;
 791 def : InstRW<[M1WriteVSTE,
 792               WriteAdr],      (instregex "ST2Twov(2d)_POST$")>;
 793
 794 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(8|16)$")>;
 795 def : InstRW<[M1WriteVSTH,
 796               WriteAdr],      (instregex "ST3i(8|16)_POST$")>;
 797 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(32)$")>;
 798 def : InstRW<[M1WriteVSTH,
 799               WriteAdr],      (instregex "ST3i(32)_POST$")>;
 800 def : InstRW<[M1WriteVSTF],   (instregex "ST3i(64)$")>;
 801 def : InstRW<[M1WriteVSTF,
 802               WriteAdr],      (instregex "ST3i(64)_POST$")>;
 803
 804 def : InstRW<[M1WriteVSTF],   (instregex "ST3Threev(8b|4h|2s)$")>;
 805 def : InstRW<[M1WriteVSTF,
 806               WriteAdr],      (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 807 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(16b|8h|4s)$")>;
 808 def : InstRW<[M1WriteVSTG,
 809               WriteAdr],      (instregex "ST3Threev(16b|8h|4s)_POST$")>;
 810 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(2d)$")>;
 811 def : InstRW<[M1WriteVSTG,
 812               WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
 813
 814 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(8|16)$")>;
 815 def : InstRW<[M1WriteVSTH,
 816               WriteAdr],      (instregex "ST4i(8|16)_POST$")>;
 817 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(32)$")>;
 818 def : InstRW<[M1WriteVSTH,
 819               WriteAdr],      (instregex "ST4i(32)_POST$")>;
 820 def : InstRW<[M1WriteVSTF],   (instregex "ST4i(64)$")>;
 821 def : InstRW<[M1WriteVSTF,
 822               WriteAdr],      (instregex "ST4i(64)_POST$")>;
 823
 824 def : InstRW<[M1WriteVSTF],   (instregex "ST4Fourv(8b|4h|2s)$")>;
 825 def : InstRW<[M1WriteVSTF,
 826               WriteAdr],      (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 827 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(16b|8h|4s)$")>;
 828 def : InstRW<[M1WriteVSTI,
 829               WriteAdr],      (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
 830 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(2d)$")>;
 831 def : InstRW<[M1WriteVSTI,
 832               WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
 833
 834 // Cryptography instructions.
 835 def M1WriteAES : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
 836 def M1ReadAES  : SchedReadAdvance<1, [M1WriteAES]>;
 837 def : InstRW<[M1WriteAES], (instregex "^AES[DE]")>;
 838 def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AESI?MC")>;
 839
 840 def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
 841 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
 842 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;
 843 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>;
 844 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>;
 845
 846 // CRC instructions.
 847 def : InstRW<[M1WriteC2], (instregex "^CRC32")>;
 848
 849 } // SchedModel = ExynosM1Model