1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/Support/TargetRegistry.h"
23 #define DEBUG_TYPE "aarch64-subtarget"
25 #define GET_SUBTARGETINFO_CTOR
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #include "AArch64GenSubtargetInfo.inc"
30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
31 "converter pass"), cl::init(true), cl::Hidden);
33 // If OS supports TBI, use this flag to enable it.
35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
36 "an address is ignored"), cl::init(false), cl::Hidden);
39 UseNonLazyBind("aarch64-enable-nonlazybind",
40 cl::desc("Call nonlazybind functions via direct GOT load"),
41 cl::init(false), cl::Hidden);
44 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
45 StringRef CPUString) {
46 // Determine default and user-specified characteristics
48 if (CPUString.empty())
49 CPUString = "generic";
51 ParseSubtargetFeatures(CPUString, FS);
52 initializeProperties();
57 void AArch64Subtarget::initializeProperties() {
58 // Initialize CPU specific properties. We should add a tablegen feature for
59 // this in the future so we can specify it together with the subtarget
61 switch (ARMProcFamily) {
64 PrefetchDistance = 280;
65 MinPrefetchStride = 2048;
66 MaxPrefetchIterationsAhead = 3;
69 MaxInterleaveFactor = 4;
72 MaxInterleaveFactor = 4;
74 PrefFunctionAlignment = 4;
75 PrefLoopAlignment = 3;
78 MaxInterleaveFactor = 4;
79 VectorInsertExtractBaseCost = 2;
82 MaxInterleaveFactor = 4;
83 VectorInsertExtractBaseCost = 2;
85 PrefetchDistance = 740;
86 MinPrefetchStride = 1024;
87 MaxPrefetchIterationsAhead = 11;
91 PrefFunctionAlignment = 3;
92 PrefLoopAlignment = 2;
93 MaxInterleaveFactor = 4;
94 PrefetchDistance = 128;
95 MinPrefetchStride = 1024;
96 MaxPrefetchIterationsAhead = 4;
103 PrefFunctionAlignment = 3;
104 PrefLoopAlignment = 2;
106 case CortexA35: break;
107 case CortexA53: break;
108 case CortexA72: break;
109 case CortexA73: break;
114 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
115 const std::string &FS,
116 const TargetMachine &TM, bool LittleEndian)
117 : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
118 IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
119 InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
120 TLInfo(TM, *this), GISel() {}
122 const CallLowering *AArch64Subtarget::getCallLowering() const {
123 assert(GISel && "Access to GlobalISel APIs not set");
124 return GISel->getCallLowering();
127 const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
128 assert(GISel && "Access to GlobalISel APIs not set");
129 return GISel->getInstructionSelector();
132 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
133 assert(GISel && "Access to GlobalISel APIs not set");
134 return GISel->getLegalizerInfo();
137 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
138 assert(GISel && "Access to GlobalISel APIs not set");
139 return GISel->getRegBankInfo();
142 /// Find the target operand flags that describe how a global value should be
143 /// referenced for the current subtarget.
145 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
146 const TargetMachine &TM) const {
147 // MachO large model always goes via a GOT, simply to get a single 8-byte
148 // absolute relocation on all global addresses.
149 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
150 return AArch64II::MO_GOT;
152 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
153 return AArch64II::MO_GOT;
155 // The small code model's direct accesses use ADRP, which cannot
156 // necessarily produce the value 0 (if the code is above 4GB).
157 if (useSmallAddressing() && GV->hasExternalWeakLinkage())
158 return AArch64II::MO_GOT;
160 return AArch64II::MO_NO_FLAG;
163 unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
164 const GlobalValue *GV, const TargetMachine &TM) const {
165 // MachO large model always goes via a GOT, because we don't have the
166 // relocations available to do anything else..
167 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
168 !GV->hasInternalLinkage())
169 return AArch64II::MO_GOT;
171 // NonLazyBind goes via GOT unless we know it's available locally.
172 auto *F = dyn_cast<Function>(GV);
173 if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
174 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
175 return AArch64II::MO_GOT;
177 return AArch64II::MO_NO_FLAG;
180 /// This function returns the name of a function which has an interface
181 /// like the non-standard bzero function, if such a function exists on
182 /// the current subtarget and it is considered prefereable over
183 /// memset with zero passed as the second argument. Otherwise it
185 const char *AArch64Subtarget::getBZeroEntry() const {
186 // Prefer bzero on Darwin only.
193 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
194 unsigned NumRegionInstrs) const {
195 // LNT run (at least on Cyclone) showed reasonably significant gains for
196 // bi-directional scheduling. 253.perlbmk.
197 Policy.OnlyTopDown = false;
198 Policy.OnlyBottomUp = false;
199 // Enabling or Disabling the latency heuristic is a close call: It seems to
200 // help nearly no benchmark on out-of-order architectures, on the other hand
201 // it regresses register pressure on a few benchmarking.
202 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
205 bool AArch64Subtarget::enableEarlyIfConversion() const {
206 return EnableEarlyIfConvert;
209 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
210 if (!UseAddressTopByteIgnored)
213 if (TargetTriple.isiOS()) {
214 unsigned Major, Minor, Micro;
215 TargetTriple.getiOSVersion(Major, Minor, Micro);
222 std::unique_ptr<PBQPRAConstraint>
223 AArch64Subtarget::getCustomPBQPConstraints() const {
224 return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;