1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/Support/TargetRegistry.h"
23 #define DEBUG_TYPE "aarch64-subtarget"
25 #define GET_SUBTARGETINFO_CTOR
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #include "AArch64GenSubtargetInfo.inc"
30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
31 "converter pass"), cl::init(true), cl::Hidden);
33 // If OS supports TBI, use this flag to enable it.
35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
36 "an address is ignored"), cl::init(false), cl::Hidden);
39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
40 StringRef CPUString) {
41 // Determine default and user-specified characteristics
43 if (CPUString.empty())
44 CPUString = "generic";
46 ParseSubtargetFeatures(CPUString, FS);
47 initializeProperties();
52 void AArch64Subtarget::initializeProperties() {
53 // Initialize CPU specific properties. We should add a tablegen feature for
54 // this in the future so we can specify it together with the subtarget
56 switch (ARMProcFamily) {
59 PrefetchDistance = 280;
60 MinPrefetchStride = 2048;
61 MaxPrefetchIterationsAhead = 3;
64 MaxInterleaveFactor = 4;
67 MaxInterleaveFactor = 4;
69 PrefFunctionAlignment = 4;
70 PrefLoopAlignment = 3;
73 MaxInterleaveFactor = 4;
74 VectorInsertExtractBaseCost = 2;
77 MaxInterleaveFactor = 4;
78 VectorInsertExtractBaseCost = 2;
80 PrefetchDistance = 740;
81 MinPrefetchStride = 1024;
82 MaxPrefetchIterationsAhead = 11;
85 MaxInterleaveFactor = 4;
87 case CortexA35: break;
88 case CortexA53: break;
89 case CortexA72: break;
90 case CortexA73: break;
95 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
96 const std::string &FS,
97 const TargetMachine &TM, bool LittleEndian)
98 : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
99 IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
100 InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
101 TLInfo(TM, *this), GISel() {}
103 const CallLowering *AArch64Subtarget::getCallLowering() const {
104 assert(GISel && "Access to GlobalISel APIs not set");
105 return GISel->getCallLowering();
108 const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
109 assert(GISel && "Access to GlobalISel APIs not set");
110 return GISel->getInstructionSelector();
113 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
114 assert(GISel && "Access to GlobalISel APIs not set");
115 return GISel->getLegalizerInfo();
118 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
119 assert(GISel && "Access to GlobalISel APIs not set");
120 return GISel->getRegBankInfo();
123 /// Find the target operand flags that describe how a global value should be
124 /// referenced for the current subtarget.
126 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
127 const TargetMachine &TM) const {
128 // MachO large model always goes via a GOT, simply to get a single 8-byte
129 // absolute relocation on all global addresses.
130 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
131 return AArch64II::MO_GOT;
133 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
134 return AArch64II::MO_GOT;
136 // The small code mode's direct accesses use ADRP, which cannot necessarily
137 // produce the value 0 (if the code is above 4GB).
138 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
139 return AArch64II::MO_GOT;
141 return AArch64II::MO_NO_FLAG;
144 /// This function returns the name of a function which has an interface
145 /// like the non-standard bzero function, if such a function exists on
146 /// the current subtarget and it is considered prefereable over
147 /// memset with zero passed as the second argument. Otherwise it
149 const char *AArch64Subtarget::getBZeroEntry() const {
150 // Prefer bzero on Darwin only.
157 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
158 unsigned NumRegionInstrs) const {
159 // LNT run (at least on Cyclone) showed reasonably significant gains for
160 // bi-directional scheduling. 253.perlbmk.
161 Policy.OnlyTopDown = false;
162 Policy.OnlyBottomUp = false;
163 // Enabling or Disabling the latency heuristic is a close call: It seems to
164 // help nearly no benchmark on out-of-order architectures, on the other hand
165 // it regresses register pressure on a few benchmarking.
166 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
169 bool AArch64Subtarget::enableEarlyIfConversion() const {
170 return EnableEarlyIfConvert;
173 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
174 if (!UseAddressTopByteIgnored)
177 if (TargetTriple.isiOS()) {
178 unsigned Major, Minor, Micro;
179 TargetTriple.getiOSVersion(Major, Minor, Micro);
186 std::unique_ptr<PBQPRAConstraint>
187 AArch64Subtarget::getCustomPBQPConstraints() const {
188 return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;