1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64Subtarget.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64PBQPRegAlloc.h"
19 #include "AArch64TargetMachine.h"
21 #ifdef LLVM_BUILD_GLOBAL_ISEL
22 #include "AArch64CallLowering.h"
23 #include "AArch64LegalizerInfo.h"
24 #include "AArch64RegisterBankInfo.h"
25 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
26 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
27 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
28 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/Support/TargetRegistry.h"
37 #define DEBUG_TYPE "aarch64-subtarget"
39 #define GET_SUBTARGETINFO_CTOR
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #include "AArch64GenSubtargetInfo.inc"
44 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
45 "converter pass"), cl::init(true), cl::Hidden);
47 // If OS supports TBI, use this flag to enable it.
49 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
50 "an address is ignored"), cl::init(false), cl::Hidden);
53 UseNonLazyBind("aarch64-enable-nonlazybind",
54 cl::desc("Call nonlazybind functions via direct GOT load"),
55 cl::init(false), cl::Hidden);
58 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
59 StringRef CPUString) {
60 // Determine default and user-specified characteristics
62 if (CPUString.empty())
63 CPUString = "generic";
65 ParseSubtargetFeatures(CPUString, FS);
66 initializeProperties();
71 void AArch64Subtarget::initializeProperties() {
72 // Initialize CPU specific properties. We should add a tablegen feature for
73 // this in the future so we can specify it together with the subtarget
75 switch (ARMProcFamily) {
78 PrefetchDistance = 280;
79 MinPrefetchStride = 2048;
80 MaxPrefetchIterationsAhead = 3;
83 MaxInterleaveFactor = 4;
84 PrefFunctionAlignment = 4;
87 MaxInterleaveFactor = 4;
89 PrefFunctionAlignment = 4;
90 PrefLoopAlignment = 3;
93 MaxInterleaveFactor = 4;
94 // FIXME: remove this to enable 64-bit SLP if performance looks good.
95 MinVectorRegisterBitWidth = 128;
97 PrefetchDistance = 820;
98 MinPrefetchStride = 2048;
99 MaxPrefetchIterationsAhead = 8;
102 MaxInterleaveFactor = 4;
103 VectorInsertExtractBaseCost = 2;
105 PrefetchDistance = 740;
106 MinPrefetchStride = 1024;
107 MaxPrefetchIterationsAhead = 11;
108 // FIXME: remove this to enable 64-bit SLP if performance looks good.
109 MinVectorRegisterBitWidth = 128;
113 PrefFunctionAlignment = 3;
114 PrefLoopAlignment = 2;
115 MaxInterleaveFactor = 4;
116 PrefetchDistance = 128;
117 MinPrefetchStride = 1024;
118 MaxPrefetchIterationsAhead = 4;
119 // FIXME: remove this to enable 64-bit SLP if performance looks good.
120 MinVectorRegisterBitWidth = 128;
127 PrefFunctionAlignment = 3;
128 PrefLoopAlignment = 2;
129 // FIXME: remove this to enable 64-bit SLP if performance looks good.
130 MinVectorRegisterBitWidth = 128;
132 case CortexA35: break;
133 case CortexA53: break;
135 PrefFunctionAlignment = 4;
137 case CortexA73: break;
142 #ifdef LLVM_BUILD_GLOBAL_ISEL
145 struct AArch64GISelActualAccessor : public GISelAccessor {
146 std::unique_ptr<CallLowering> CallLoweringInfo;
147 std::unique_ptr<InstructionSelector> InstSelector;
148 std::unique_ptr<LegalizerInfo> Legalizer;
149 std::unique_ptr<RegisterBankInfo> RegBankInfo;
151 const CallLowering *getCallLowering() const override {
152 return CallLoweringInfo.get();
155 const InstructionSelector *getInstructionSelector() const override {
156 return InstSelector.get();
159 const LegalizerInfo *getLegalizerInfo() const override {
160 return Legalizer.get();
163 const RegisterBankInfo *getRegBankInfo() const override {
164 return RegBankInfo.get();
168 } // end anonymous namespace
171 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
172 const std::string &FS,
173 const TargetMachine &TM, bool LittleEndian)
174 : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
175 IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
176 InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
177 TLInfo(TM, *this), GISel() {
178 #ifndef LLVM_BUILD_GLOBAL_ISEL
179 GISelAccessor *AArch64GISel = new GISelAccessor();
181 AArch64GISelActualAccessor *AArch64GISel = new AArch64GISelActualAccessor();
182 AArch64GISel->CallLoweringInfo.reset(
183 new AArch64CallLowering(*getTargetLowering()));
184 AArch64GISel->Legalizer.reset(new AArch64LegalizerInfo());
186 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
188 // FIXME: At this point, we can't rely on Subtarget having RBI.
189 // It's awkward to mix passing RBI and the Subtarget; should we pass
191 AArch64GISel->InstSelector.reset(createAArch64InstructionSelector(
192 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
194 AArch64GISel->RegBankInfo.reset(RBI);
196 setGISelAccessor(*AArch64GISel);
199 const CallLowering *AArch64Subtarget::getCallLowering() const {
200 assert(GISel && "Access to GlobalISel APIs not set");
201 return GISel->getCallLowering();
204 const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
205 assert(GISel && "Access to GlobalISel APIs not set");
206 return GISel->getInstructionSelector();
209 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
210 assert(GISel && "Access to GlobalISel APIs not set");
211 return GISel->getLegalizerInfo();
214 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
215 assert(GISel && "Access to GlobalISel APIs not set");
216 return GISel->getRegBankInfo();
219 /// Find the target operand flags that describe how a global value should be
220 /// referenced for the current subtarget.
222 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
223 const TargetMachine &TM) const {
224 // MachO large model always goes via a GOT, simply to get a single 8-byte
225 // absolute relocation on all global addresses.
226 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
227 return AArch64II::MO_GOT;
229 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
230 return AArch64II::MO_GOT;
232 // The small code model's direct accesses use ADRP, which cannot
233 // necessarily produce the value 0 (if the code is above 4GB).
234 if (useSmallAddressing() && GV->hasExternalWeakLinkage())
235 return AArch64II::MO_GOT;
237 return AArch64II::MO_NO_FLAG;
240 unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
241 const GlobalValue *GV, const TargetMachine &TM) const {
242 // MachO large model always goes via a GOT, because we don't have the
243 // relocations available to do anything else..
244 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
245 !GV->hasInternalLinkage())
246 return AArch64II::MO_GOT;
248 // NonLazyBind goes via GOT unless we know it's available locally.
249 auto *F = dyn_cast<Function>(GV);
250 if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
251 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
252 return AArch64II::MO_GOT;
254 return AArch64II::MO_NO_FLAG;
257 /// This function returns the name of a function which has an interface
258 /// like the non-standard bzero function, if such a function exists on
259 /// the current subtarget and it is considered prefereable over
260 /// memset with zero passed as the second argument. Otherwise it
262 const char *AArch64Subtarget::getBZeroEntry() const {
263 // Prefer bzero on Darwin only.
270 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
271 unsigned NumRegionInstrs) const {
272 // LNT run (at least on Cyclone) showed reasonably significant gains for
273 // bi-directional scheduling. 253.perlbmk.
274 Policy.OnlyTopDown = false;
275 Policy.OnlyBottomUp = false;
276 // Enabling or Disabling the latency heuristic is a close call: It seems to
277 // help nearly no benchmark on out-of-order architectures, on the other hand
278 // it regresses register pressure on a few benchmarking.
279 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
282 bool AArch64Subtarget::enableEarlyIfConversion() const {
283 return EnableEarlyIfConvert;
286 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
287 if (!UseAddressTopByteIgnored)
290 if (TargetTriple.isiOS()) {
291 unsigned Major, Minor, Micro;
292 TargetTriple.getiOSVersion(Major, Minor, Micro);
299 std::unique_ptr<PBQPRAConstraint>
300 AArch64Subtarget::getCustomPBQPConstraints() const {
301 return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;