1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
56 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
57 ARMProcFamilyEnum ARMProcFamily = Others;
59 bool HasV8_1aOps = false;
60 bool HasV8_2aOps = false;
62 bool HasFPARMv8 = false;
64 bool HasCrypto = false;
69 bool HasPerfMon = false;
70 bool HasFullFP16 = false;
72 bool HasLSLFast = false;
75 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
76 bool HasZeroCycleRegMove = false;
78 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
79 bool HasZeroCycleZeroing = false;
81 // StrictAlign - Disallow unaligned memory accesses.
82 bool StrictAlign = false;
84 // NegativeImmediates - transform instructions with negative immediates
85 bool NegativeImmediates = true;
87 // Enable 64-bit vectorization in SLP.
88 unsigned MinVectorRegisterBitWidth = 64;
91 bool PredictableSelectIsExpensive = false;
92 bool BalanceFPOps = false;
93 bool CustomAsCheapAsMove = false;
94 bool UsePostRAScheduler = false;
95 bool Misaligned128StoreIsSlow = false;
96 bool Paired128IsSlow = false;
97 bool UseAlternateSExtLoadCVTF32Pattern = false;
98 bool HasArithmeticBccFusion = false;
99 bool HasArithmeticCbzFusion = false;
100 bool HasFuseAES = false;
101 bool HasFuseLiterals = false;
102 bool DisableLatencySchedHeuristic = false;
103 bool UseRSqrt = false;
104 uint8_t MaxInterleaveFactor = 2;
105 uint8_t VectorInsertExtractBaseCost = 3;
106 uint16_t CacheLineSize = 0;
107 uint16_t PrefetchDistance = 0;
108 uint16_t MinPrefetchStride = 1;
109 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
110 unsigned PrefFunctionAlignment = 0;
111 unsigned PrefLoopAlignment = 0;
112 unsigned MaxJumpTableSize = 0;
113 unsigned WideningBaseCost = 0;
115 // ReserveX18 - X18 is not available as a general purpose register.
120 /// TargetTriple - What processor and OS we're targeting.
123 AArch64FrameLowering FrameLowering;
124 AArch64InstrInfo InstrInfo;
125 AArch64SelectionDAGInfo TSInfo;
126 AArch64TargetLowering TLInfo;
127 /// Gather the accessor points to GlobalISel-related APIs.
128 /// This is used to avoid ifndefs spreading around while GISel is
129 /// an optional library.
130 std::unique_ptr<GISelAccessor> GISel;
133 /// initializeSubtargetDependencies - Initializes using CPUString and the
134 /// passed in feature string so that we can use initializer lists for
135 /// subtarget initialization.
136 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
137 StringRef CPUString);
139 /// Initialize properties based on the selected processor family.
140 void initializeProperties();
143 /// This constructor initializes the data members to match that
144 /// of the specified triple.
145 AArch64Subtarget(const Triple &TT, const std::string &CPU,
146 const std::string &FS, const TargetMachine &TM,
149 /// This object will take onwership of \p GISelAccessor.
150 void setGISelAccessor(GISelAccessor &GISel) {
151 this->GISel.reset(&GISel);
154 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
157 const AArch64FrameLowering *getFrameLowering() const override {
158 return &FrameLowering;
160 const AArch64TargetLowering *getTargetLowering() const override {
163 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
164 const AArch64RegisterInfo *getRegisterInfo() const override {
165 return &getInstrInfo()->getRegisterInfo();
167 const CallLowering *getCallLowering() const override;
168 const InstructionSelector *getInstructionSelector() const override;
169 const LegalizerInfo *getLegalizerInfo() const override;
170 const RegisterBankInfo *getRegBankInfo() const override;
171 const Triple &getTargetTriple() const { return TargetTriple; }
172 bool enableMachineScheduler() const override { return true; }
173 bool enablePostRAScheduler() const override {
174 return UsePostRAScheduler;
177 /// Returns ARM processor family.
178 /// Avoid this function! CPU specifics should be kept local to this class
179 /// and preferably modeled with SubtargetFeatures or properties in
180 /// initializeProperties().
181 ARMProcFamilyEnum getProcFamily() const {
182 return ARMProcFamily;
185 bool hasV8_1aOps() const { return HasV8_1aOps; }
186 bool hasV8_2aOps() const { return HasV8_2aOps; }
188 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
190 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
192 bool requiresStrictAlign() const { return StrictAlign; }
194 bool isXRaySupported() const override { return true; }
196 unsigned getMinVectorRegisterBitWidth() const {
197 return MinVectorRegisterBitWidth;
200 bool isX18Reserved() const { return ReserveX18; }
201 bool hasFPARMv8() const { return HasFPARMv8; }
202 bool hasNEON() const { return HasNEON; }
203 bool hasCrypto() const { return HasCrypto; }
204 bool hasCRC() const { return HasCRC; }
205 bool hasLSE() const { return HasLSE; }
206 bool hasRAS() const { return HasRAS; }
207 bool hasRDM() const { return HasRDM; }
208 bool balanceFPOps() const { return BalanceFPOps; }
209 bool predictableSelectIsExpensive() const {
210 return PredictableSelectIsExpensive;
212 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
213 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
214 bool isPaired128Slow() const { return Paired128IsSlow; }
215 bool useAlternateSExtLoadCVTF32Pattern() const {
216 return UseAlternateSExtLoadCVTF32Pattern;
218 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
219 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
220 bool hasFuseAES() const { return HasFuseAES; }
221 bool hasFuseLiterals() const { return HasFuseLiterals; }
223 /// \brief Return true if the CPU supports any kind of instruction fusion.
224 bool hasFusion() const {
225 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
226 hasFuseAES() || hasFuseLiterals();
229 bool useRSqrt() const { return UseRSqrt; }
230 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
231 unsigned getVectorInsertExtractBaseCost() const {
232 return VectorInsertExtractBaseCost;
234 unsigned getCacheLineSize() const { return CacheLineSize; }
235 unsigned getPrefetchDistance() const { return PrefetchDistance; }
236 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
237 unsigned getMaxPrefetchIterationsAhead() const {
238 return MaxPrefetchIterationsAhead;
240 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
241 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
243 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
245 unsigned getWideningBaseCost() const { return WideningBaseCost; }
247 /// CPU has TBI (top byte of addresses is ignored during HW address
248 /// translation) and OS enables it.
249 bool supportsAddressTopByteIgnored() const;
251 bool hasPerfMon() const { return HasPerfMon; }
252 bool hasFullFP16() const { return HasFullFP16; }
253 bool hasSPE() const { return HasSPE; }
254 bool hasLSLFast() const { return HasLSLFast; }
255 bool hasSVE() const { return HasSVE; }
257 bool isLittleEndian() const { return IsLittle; }
259 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
260 bool isTargetIOS() const { return TargetTriple.isiOS(); }
261 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
262 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
263 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
264 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
266 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
267 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
268 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
270 bool useAA() const override { return UseAA; }
272 bool useSmallAddressing() const {
273 switch (TLInfo.getTargetMachine().getCodeModel()) {
274 case CodeModel::Kernel:
275 // Kernel is currently allowed only for Fuchsia targets,
276 // where it is the same as Small for almost all purposes.
277 case CodeModel::Small:
284 /// ParseSubtargetFeatures - Parses features string setting specified
285 /// subtarget options. Definition of function is auto generated by tblgen.
286 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
288 /// ClassifyGlobalReference - Find the target operand flags that describe
289 /// how a global value should be referenced for the current subtarget.
290 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
291 const TargetMachine &TM) const;
293 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
294 const TargetMachine &TM) const;
296 /// This function returns the name of a function which has an interface
297 /// like the non-standard bzero function, if such a function exists on
298 /// the current subtarget and it is considered prefereable over
299 /// memset with zero passed as the second argument. Otherwise it
301 const char *getBZeroEntry() const;
303 void overrideSchedPolicy(MachineSchedPolicy &Policy,
304 unsigned NumRegionInstrs) const override;
306 bool enableEarlyIfConversion() const override;
308 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
310 bool isCallingConvWin64(CallingConv::ID CC) const {
313 return isTargetWindows();
314 case CallingConv::Win64:
321 } // End llvm namespace