1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
56 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
57 ARMProcFamilyEnum ARMProcFamily = Others;
59 bool HasV8_1aOps = false;
60 bool HasV8_2aOps = false;
62 bool HasFPARMv8 = false;
64 bool HasCrypto = false;
69 bool HasPerfMon = false;
70 bool HasFullFP16 = false;
72 bool HasLSLFast = false;
74 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
75 bool HasZeroCycleRegMove = false;
77 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
78 bool HasZeroCycleZeroing = false;
80 // StrictAlign - Disallow unaligned memory accesses.
81 bool StrictAlign = false;
83 // NegativeImmediates - transform instructions with negative immediates
84 bool NegativeImmediates = true;
86 // Enable 64-bit vectorization in SLP.
87 unsigned MinVectorRegisterBitWidth = 64;
90 bool PredictableSelectIsExpensive = false;
91 bool BalanceFPOps = false;
92 bool CustomAsCheapAsMove = false;
93 bool UsePostRAScheduler = false;
94 bool Misaligned128StoreIsSlow = false;
95 bool Paired128IsSlow = false;
96 bool UseAlternateSExtLoadCVTF32Pattern = false;
97 bool HasArithmeticBccFusion = false;
98 bool HasArithmeticCbzFusion = false;
99 bool HasFuseAES = false;
100 bool HasFuseLiterals = false;
101 bool DisableLatencySchedHeuristic = false;
102 bool UseRSqrt = false;
103 uint8_t MaxInterleaveFactor = 2;
104 uint8_t VectorInsertExtractBaseCost = 3;
105 uint16_t CacheLineSize = 0;
106 uint16_t PrefetchDistance = 0;
107 uint16_t MinPrefetchStride = 1;
108 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
109 unsigned PrefFunctionAlignment = 0;
110 unsigned PrefLoopAlignment = 0;
111 unsigned MaxJumpTableSize = 0;
112 unsigned WideningBaseCost = 0;
114 // ReserveX18 - X18 is not available as a general purpose register.
119 /// TargetTriple - What processor and OS we're targeting.
122 AArch64FrameLowering FrameLowering;
123 AArch64InstrInfo InstrInfo;
124 AArch64SelectionDAGInfo TSInfo;
125 AArch64TargetLowering TLInfo;
126 /// Gather the accessor points to GlobalISel-related APIs.
127 /// This is used to avoid ifndefs spreading around while GISel is
128 /// an optional library.
129 std::unique_ptr<GISelAccessor> GISel;
132 /// initializeSubtargetDependencies - Initializes using CPUString and the
133 /// passed in feature string so that we can use initializer lists for
134 /// subtarget initialization.
135 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
136 StringRef CPUString);
138 /// Initialize properties based on the selected processor family.
139 void initializeProperties();
142 /// This constructor initializes the data members to match that
143 /// of the specified triple.
144 AArch64Subtarget(const Triple &TT, const std::string &CPU,
145 const std::string &FS, const TargetMachine &TM,
148 /// This object will take onwership of \p GISelAccessor.
149 void setGISelAccessor(GISelAccessor &GISel) {
150 this->GISel.reset(&GISel);
153 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
156 const AArch64FrameLowering *getFrameLowering() const override {
157 return &FrameLowering;
159 const AArch64TargetLowering *getTargetLowering() const override {
162 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
163 const AArch64RegisterInfo *getRegisterInfo() const override {
164 return &getInstrInfo()->getRegisterInfo();
166 const CallLowering *getCallLowering() const override;
167 const InstructionSelector *getInstructionSelector() const override;
168 const LegalizerInfo *getLegalizerInfo() const override;
169 const RegisterBankInfo *getRegBankInfo() const override;
170 const Triple &getTargetTriple() const { return TargetTriple; }
171 bool enableMachineScheduler() const override { return true; }
172 bool enablePostRAScheduler() const override {
173 return UsePostRAScheduler;
176 /// Returns ARM processor family.
177 /// Avoid this function! CPU specifics should be kept local to this class
178 /// and preferably modeled with SubtargetFeatures or properties in
179 /// initializeProperties().
180 ARMProcFamilyEnum getProcFamily() const {
181 return ARMProcFamily;
184 bool hasV8_1aOps() const { return HasV8_1aOps; }
185 bool hasV8_2aOps() const { return HasV8_2aOps; }
187 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
189 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
191 bool requiresStrictAlign() const { return StrictAlign; }
193 bool isXRaySupported() const override { return true; }
195 unsigned getMinVectorRegisterBitWidth() const {
196 return MinVectorRegisterBitWidth;
199 bool isX18Reserved() const { return ReserveX18; }
200 bool hasFPARMv8() const { return HasFPARMv8; }
201 bool hasNEON() const { return HasNEON; }
202 bool hasCrypto() const { return HasCrypto; }
203 bool hasCRC() const { return HasCRC; }
204 bool hasLSE() const { return HasLSE; }
205 bool hasRAS() const { return HasRAS; }
206 bool hasRDM() const { return HasRDM; }
207 bool balanceFPOps() const { return BalanceFPOps; }
208 bool predictableSelectIsExpensive() const {
209 return PredictableSelectIsExpensive;
211 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
212 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
213 bool isPaired128Slow() const { return Paired128IsSlow; }
214 bool useAlternateSExtLoadCVTF32Pattern() const {
215 return UseAlternateSExtLoadCVTF32Pattern;
217 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
218 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
219 bool hasFuseAES() const { return HasFuseAES; }
220 bool hasFuseLiterals() const { return HasFuseLiterals; }
221 bool useRSqrt() const { return UseRSqrt; }
222 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
223 unsigned getVectorInsertExtractBaseCost() const {
224 return VectorInsertExtractBaseCost;
226 unsigned getCacheLineSize() const { return CacheLineSize; }
227 unsigned getPrefetchDistance() const { return PrefetchDistance; }
228 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
229 unsigned getMaxPrefetchIterationsAhead() const {
230 return MaxPrefetchIterationsAhead;
232 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
233 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
235 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
237 unsigned getWideningBaseCost() const { return WideningBaseCost; }
239 /// CPU has TBI (top byte of addresses is ignored during HW address
240 /// translation) and OS enables it.
241 bool supportsAddressTopByteIgnored() const;
243 bool hasPerfMon() const { return HasPerfMon; }
244 bool hasFullFP16() const { return HasFullFP16; }
245 bool hasSPE() const { return HasSPE; }
246 bool hasLSLFast() const { return HasLSLFast; }
248 bool isLittleEndian() const { return IsLittle; }
250 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
251 bool isTargetIOS() const { return TargetTriple.isiOS(); }
252 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
253 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
254 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
255 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
257 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
258 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
259 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
261 bool useAA() const override { return UseAA; }
263 bool useSmallAddressing() const {
264 switch (TLInfo.getTargetMachine().getCodeModel()) {
265 case CodeModel::Kernel:
266 // Kernel is currently allowed only for Fuchsia targets,
267 // where it is the same as Small for almost all purposes.
268 case CodeModel::Small:
275 /// ParseSubtargetFeatures - Parses features string setting specified
276 /// subtarget options. Definition of function is auto generated by tblgen.
277 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
279 /// ClassifyGlobalReference - Find the target operand flags that describe
280 /// how a global value should be referenced for the current subtarget.
281 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
282 const TargetMachine &TM) const;
284 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
285 const TargetMachine &TM) const;
287 /// This function returns the name of a function which has an interface
288 /// like the non-standard bzero function, if such a function exists on
289 /// the current subtarget and it is considered prefereable over
290 /// memset with zero passed as the second argument. Otherwise it
292 const char *getBZeroEntry() const;
294 void overrideSchedPolicy(MachineSchedPolicy &Policy,
295 unsigned NumRegionInstrs) const override;
297 bool enableEarlyIfConversion() const override;
299 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
301 } // End llvm namespace