1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
52 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
53 ARMProcFamilyEnum ARMProcFamily = Others;
55 bool HasV8_1aOps = false;
56 bool HasV8_2aOps = false;
58 bool HasFPARMv8 = false;
60 bool HasCrypto = false;
64 bool HasPerfMon = false;
65 bool HasFullFP16 = false;
68 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
69 bool HasZeroCycleRegMove = false;
71 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
72 bool HasZeroCycleZeroing = false;
74 // StrictAlign - Disallow unaligned memory accesses.
75 bool StrictAlign = false;
77 bool PredictableSelectIsExpensive = false;
78 bool BalanceFPOps = false;
79 bool CustomAsCheapAsMove = false;
80 bool UsePostRAScheduler = false;
81 bool Misaligned128StoreIsSlow = false;
82 bool Paired128IsSlow = false;
83 bool UseAlternateSExtLoadCVTF32Pattern = false;
84 bool HasArithmeticBccFusion = false;
85 bool HasArithmeticCbzFusion = false;
86 bool DisableLatencySchedHeuristic = false;
87 bool UseRSqrt = false;
88 uint8_t MaxInterleaveFactor = 2;
89 uint8_t VectorInsertExtractBaseCost = 3;
90 uint16_t CacheLineSize = 0;
91 uint16_t PrefetchDistance = 0;
92 uint16_t MinPrefetchStride = 1;
93 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
94 unsigned PrefFunctionAlignment = 0;
95 unsigned PrefLoopAlignment = 0;
96 unsigned MaxJumpTableSize = 0;
98 // ReserveX18 - X18 is not available as a general purpose register.
103 /// TargetTriple - What processor and OS we're targeting.
106 AArch64FrameLowering FrameLowering;
107 AArch64InstrInfo InstrInfo;
108 AArch64SelectionDAGInfo TSInfo;
109 AArch64TargetLowering TLInfo;
110 /// Gather the accessor points to GlobalISel-related APIs.
111 /// This is used to avoid ifndefs spreading around while GISel is
112 /// an optional library.
113 std::unique_ptr<GISelAccessor> GISel;
116 /// initializeSubtargetDependencies - Initializes using CPUString and the
117 /// passed in feature string so that we can use initializer lists for
118 /// subtarget initialization.
119 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
120 StringRef CPUString);
122 /// Initialize properties based on the selected processor family.
123 void initializeProperties();
126 /// This constructor initializes the data members to match that
127 /// of the specified triple.
128 AArch64Subtarget(const Triple &TT, const std::string &CPU,
129 const std::string &FS, const TargetMachine &TM,
132 /// This object will take onwership of \p GISelAccessor.
133 void setGISelAccessor(GISelAccessor &GISel) {
134 this->GISel.reset(&GISel);
137 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
140 const AArch64FrameLowering *getFrameLowering() const override {
141 return &FrameLowering;
143 const AArch64TargetLowering *getTargetLowering() const override {
146 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
147 const AArch64RegisterInfo *getRegisterInfo() const override {
148 return &getInstrInfo()->getRegisterInfo();
150 const CallLowering *getCallLowering() const override;
151 const InstructionSelector *getInstructionSelector() const override;
152 const LegalizerInfo *getLegalizerInfo() const override;
153 const RegisterBankInfo *getRegBankInfo() const override;
154 const Triple &getTargetTriple() const { return TargetTriple; }
155 bool enableMachineScheduler() const override { return true; }
156 bool enablePostRAScheduler() const override {
157 return UsePostRAScheduler;
160 /// Returns ARM processor family.
161 /// Avoid this function! CPU specifics should be kept local to this class
162 /// and preferably modeled with SubtargetFeatures or properties in
163 /// initializeProperties().
164 ARMProcFamilyEnum getProcFamily() const {
165 return ARMProcFamily;
168 bool hasV8_1aOps() const { return HasV8_1aOps; }
169 bool hasV8_2aOps() const { return HasV8_2aOps; }
171 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
173 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
175 bool requiresStrictAlign() const { return StrictAlign; }
177 bool isXRaySupported() const override { return true; }
179 bool isX18Reserved() const { return ReserveX18; }
180 bool hasFPARMv8() const { return HasFPARMv8; }
181 bool hasNEON() const { return HasNEON; }
182 bool hasCrypto() const { return HasCrypto; }
183 bool hasCRC() const { return HasCRC; }
184 bool hasLSE() const { return HasLSE; }
185 bool hasRAS() const { return HasRAS; }
186 bool balanceFPOps() const { return BalanceFPOps; }
187 bool predictableSelectIsExpensive() const {
188 return PredictableSelectIsExpensive;
190 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
191 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
192 bool isPaired128Slow() const { return Paired128IsSlow; }
193 bool useAlternateSExtLoadCVTF32Pattern() const {
194 return UseAlternateSExtLoadCVTF32Pattern;
196 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
197 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
198 bool useRSqrt() const { return UseRSqrt; }
199 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
200 unsigned getVectorInsertExtractBaseCost() const {
201 return VectorInsertExtractBaseCost;
203 unsigned getCacheLineSize() const { return CacheLineSize; }
204 unsigned getPrefetchDistance() const { return PrefetchDistance; }
205 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
206 unsigned getMaxPrefetchIterationsAhead() const {
207 return MaxPrefetchIterationsAhead;
209 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
210 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
212 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
214 /// CPU has TBI (top byte of addresses is ignored during HW address
215 /// translation) and OS enables it.
216 bool supportsAddressTopByteIgnored() const;
218 bool hasPerfMon() const { return HasPerfMon; }
219 bool hasFullFP16() const { return HasFullFP16; }
220 bool hasSPE() const { return HasSPE; }
222 bool isLittleEndian() const { return IsLittle; }
224 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
225 bool isTargetIOS() const { return TargetTriple.isiOS(); }
226 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
227 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
228 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
230 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
231 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
232 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
234 bool useAA() const override { return UseAA; }
236 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
237 /// that still makes it profitable to inline the call.
238 unsigned getMaxInlineSizeThreshold() const { return 64; }
240 /// ParseSubtargetFeatures - Parses features string setting specified
241 /// subtarget options. Definition of function is auto generated by tblgen.
242 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
244 /// ClassifyGlobalReference - Find the target operand flags that describe
245 /// how a global value should be referenced for the current subtarget.
246 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
247 const TargetMachine &TM) const;
249 /// This function returns the name of a function which has an interface
250 /// like the non-standard bzero function, if such a function exists on
251 /// the current subtarget and it is considered prefereable over
252 /// memset with zero passed as the second argument. Otherwise it
254 const char *getBZeroEntry() const;
256 void overrideSchedPolicy(MachineSchedPolicy &Policy,
257 unsigned NumRegionInstrs) const override;
259 bool enableEarlyIfConversion() const override;
261 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
263 } // End llvm namespace