1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
56 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
57 ARMProcFamilyEnum ARMProcFamily = Others;
59 bool HasV8_1aOps = false;
60 bool HasV8_2aOps = false;
62 bool HasFPARMv8 = false;
64 bool HasCrypto = false;
69 bool HasPerfMon = false;
70 bool HasFullFP16 = false;
72 bool HasLSLFast = false;
74 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
75 bool HasZeroCycleRegMove = false;
77 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
78 bool HasZeroCycleZeroing = false;
80 // StrictAlign - Disallow unaligned memory accesses.
81 bool StrictAlign = false;
83 // NegativeImmediates - transform instructions with negative immediates
84 bool NegativeImmediates = true;
87 bool PredictableSelectIsExpensive = false;
88 bool BalanceFPOps = false;
89 bool CustomAsCheapAsMove = false;
90 bool UsePostRAScheduler = false;
91 bool Misaligned128StoreIsSlow = false;
92 bool Paired128IsSlow = false;
93 bool UseAlternateSExtLoadCVTF32Pattern = false;
94 bool HasArithmeticBccFusion = false;
95 bool HasArithmeticCbzFusion = false;
96 bool HasFuseAES = false;
97 bool HasFuseLiterals = false;
98 bool DisableLatencySchedHeuristic = false;
99 bool UseRSqrt = false;
100 uint8_t MaxInterleaveFactor = 2;
101 uint8_t VectorInsertExtractBaseCost = 3;
102 uint16_t CacheLineSize = 0;
103 uint16_t PrefetchDistance = 0;
104 uint16_t MinPrefetchStride = 1;
105 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
106 unsigned PrefFunctionAlignment = 0;
107 unsigned PrefLoopAlignment = 0;
108 unsigned MaxJumpTableSize = 0;
110 // ReserveX18 - X18 is not available as a general purpose register.
115 /// TargetTriple - What processor and OS we're targeting.
118 AArch64FrameLowering FrameLowering;
119 AArch64InstrInfo InstrInfo;
120 AArch64SelectionDAGInfo TSInfo;
121 AArch64TargetLowering TLInfo;
122 /// Gather the accessor points to GlobalISel-related APIs.
123 /// This is used to avoid ifndefs spreading around while GISel is
124 /// an optional library.
125 std::unique_ptr<GISelAccessor> GISel;
128 /// initializeSubtargetDependencies - Initializes using CPUString and the
129 /// passed in feature string so that we can use initializer lists for
130 /// subtarget initialization.
131 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
132 StringRef CPUString);
134 /// Initialize properties based on the selected processor family.
135 void initializeProperties();
138 /// This constructor initializes the data members to match that
139 /// of the specified triple.
140 AArch64Subtarget(const Triple &TT, const std::string &CPU,
141 const std::string &FS, const TargetMachine &TM,
144 /// This object will take onwership of \p GISelAccessor.
145 void setGISelAccessor(GISelAccessor &GISel) {
146 this->GISel.reset(&GISel);
149 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
152 const AArch64FrameLowering *getFrameLowering() const override {
153 return &FrameLowering;
155 const AArch64TargetLowering *getTargetLowering() const override {
158 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
159 const AArch64RegisterInfo *getRegisterInfo() const override {
160 return &getInstrInfo()->getRegisterInfo();
162 const CallLowering *getCallLowering() const override;
163 const InstructionSelector *getInstructionSelector() const override;
164 const LegalizerInfo *getLegalizerInfo() const override;
165 const RegisterBankInfo *getRegBankInfo() const override;
166 const Triple &getTargetTriple() const { return TargetTriple; }
167 bool enableMachineScheduler() const override { return true; }
168 bool enablePostRAScheduler() const override {
169 return UsePostRAScheduler;
172 /// Returns ARM processor family.
173 /// Avoid this function! CPU specifics should be kept local to this class
174 /// and preferably modeled with SubtargetFeatures or properties in
175 /// initializeProperties().
176 ARMProcFamilyEnum getProcFamily() const {
177 return ARMProcFamily;
180 bool hasV8_1aOps() const { return HasV8_1aOps; }
181 bool hasV8_2aOps() const { return HasV8_2aOps; }
183 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
185 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
187 bool requiresStrictAlign() const { return StrictAlign; }
189 bool isXRaySupported() const override { return true; }
191 bool isX18Reserved() const { return ReserveX18; }
192 bool hasFPARMv8() const { return HasFPARMv8; }
193 bool hasNEON() const { return HasNEON; }
194 bool hasCrypto() const { return HasCrypto; }
195 bool hasCRC() const { return HasCRC; }
196 bool hasLSE() const { return HasLSE; }
197 bool hasRAS() const { return HasRAS; }
198 bool hasRDM() const { return HasRDM; }
199 bool balanceFPOps() const { return BalanceFPOps; }
200 bool predictableSelectIsExpensive() const {
201 return PredictableSelectIsExpensive;
203 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
204 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
205 bool isPaired128Slow() const { return Paired128IsSlow; }
206 bool useAlternateSExtLoadCVTF32Pattern() const {
207 return UseAlternateSExtLoadCVTF32Pattern;
209 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
210 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
211 bool hasFuseAES() const { return HasFuseAES; }
212 bool hasFuseLiterals() const { return HasFuseLiterals; }
213 bool useRSqrt() const { return UseRSqrt; }
214 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
215 unsigned getVectorInsertExtractBaseCost() const {
216 return VectorInsertExtractBaseCost;
218 unsigned getCacheLineSize() const { return CacheLineSize; }
219 unsigned getPrefetchDistance() const { return PrefetchDistance; }
220 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
221 unsigned getMaxPrefetchIterationsAhead() const {
222 return MaxPrefetchIterationsAhead;
224 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
225 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
227 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
229 /// CPU has TBI (top byte of addresses is ignored during HW address
230 /// translation) and OS enables it.
231 bool supportsAddressTopByteIgnored() const;
233 bool hasPerfMon() const { return HasPerfMon; }
234 bool hasFullFP16() const { return HasFullFP16; }
235 bool hasSPE() const { return HasSPE; }
236 bool hasLSLFast() const { return HasLSLFast; }
238 bool isLittleEndian() const { return IsLittle; }
240 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
241 bool isTargetIOS() const { return TargetTriple.isiOS(); }
242 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
243 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
244 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
245 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
247 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
248 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
249 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
251 bool useAA() const override { return UseAA; }
253 bool useSmallAddressing() const {
254 switch (TLInfo.getTargetMachine().getCodeModel()) {
255 case CodeModel::Kernel:
256 // Kernel is currently allowed only for Fuchsia targets,
257 // where it is the same as Small for almost all purposes.
258 case CodeModel::Small:
265 /// ParseSubtargetFeatures - Parses features string setting specified
266 /// subtarget options. Definition of function is auto generated by tblgen.
267 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
269 /// ClassifyGlobalReference - Find the target operand flags that describe
270 /// how a global value should be referenced for the current subtarget.
271 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
272 const TargetMachine &TM) const;
274 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
275 const TargetMachine &TM) const;
277 /// This function returns the name of a function which has an interface
278 /// like the non-standard bzero function, if such a function exists on
279 /// the current subtarget and it is considered prefereable over
280 /// memset with zero passed as the second argument. Otherwise it
282 const char *getBZeroEntry() const;
284 void overrideSchedPolicy(MachineSchedPolicy &Policy,
285 unsigned NumRegionInstrs) const override;
287 bool enableEarlyIfConversion() const override;
289 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
291 } // End llvm namespace