1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
56 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
57 ARMProcFamilyEnum ARMProcFamily = Others;
59 bool HasV8_1aOps = false;
60 bool HasV8_2aOps = false;
62 bool HasFPARMv8 = false;
64 bool HasCrypto = false;
69 bool HasPerfMon = false;
70 bool HasFullFP16 = false;
72 bool HasLSLFast = false;
74 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
75 bool HasZeroCycleRegMove = false;
77 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
78 bool HasZeroCycleZeroing = false;
80 // StrictAlign - Disallow unaligned memory accesses.
81 bool StrictAlign = false;
83 // NegativeImmediates - transform instructions with negative immediates
84 bool NegativeImmediates = true;
86 // Enable 64-bit vectorization in SLP.
87 unsigned MinVectorRegisterBitWidth = 64;
90 bool PredictableSelectIsExpensive = false;
91 bool BalanceFPOps = false;
92 bool CustomAsCheapAsMove = false;
93 bool UsePostRAScheduler = false;
94 bool Misaligned128StoreIsSlow = false;
95 bool Paired128IsSlow = false;
96 bool UseAlternateSExtLoadCVTF32Pattern = false;
97 bool HasArithmeticBccFusion = false;
98 bool HasArithmeticCbzFusion = false;
99 bool HasFuseAES = false;
100 bool HasFuseLiterals = false;
101 bool DisableLatencySchedHeuristic = false;
102 bool UseRSqrt = false;
103 uint8_t MaxInterleaveFactor = 2;
104 uint8_t VectorInsertExtractBaseCost = 3;
105 uint16_t CacheLineSize = 0;
106 uint16_t PrefetchDistance = 0;
107 uint16_t MinPrefetchStride = 1;
108 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
109 unsigned PrefFunctionAlignment = 0;
110 unsigned PrefLoopAlignment = 0;
111 unsigned MaxJumpTableSize = 0;
112 unsigned WideningBaseCost = 0;
114 // ReserveX18 - X18 is not available as a general purpose register.
119 /// TargetTriple - What processor and OS we're targeting.
122 AArch64FrameLowering FrameLowering;
123 AArch64InstrInfo InstrInfo;
124 AArch64SelectionDAGInfo TSInfo;
125 AArch64TargetLowering TLInfo;
126 /// Gather the accessor points to GlobalISel-related APIs.
127 /// This is used to avoid ifndefs spreading around while GISel is
128 /// an optional library.
129 std::unique_ptr<GISelAccessor> GISel;
134 /// initializeSubtargetDependencies - Initializes using CPUString and the
135 /// passed in feature string so that we can use initializer lists for
136 /// subtarget initialization.
137 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
138 StringRef CPUString);
140 /// Initialize properties based on the selected processor family.
141 void initializeProperties();
144 /// This constructor initializes the data members to match that
145 /// of the specified triple.
146 AArch64Subtarget(const Triple &TT, const std::string &CPU,
147 const std::string &FS, const TargetMachine &TM,
148 bool LittleEndian, bool ForCodeSize);
150 /// This object will take onwership of \p GISelAccessor.
151 void setGISelAccessor(GISelAccessor &GISel) {
152 this->GISel.reset(&GISel);
155 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
158 const AArch64FrameLowering *getFrameLowering() const override {
159 return &FrameLowering;
161 const AArch64TargetLowering *getTargetLowering() const override {
164 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
165 const AArch64RegisterInfo *getRegisterInfo() const override {
166 return &getInstrInfo()->getRegisterInfo();
168 const CallLowering *getCallLowering() const override;
169 const InstructionSelector *getInstructionSelector() const override;
170 const LegalizerInfo *getLegalizerInfo() const override;
171 const RegisterBankInfo *getRegBankInfo() const override;
172 const Triple &getTargetTriple() const { return TargetTriple; }
173 bool enableMachineScheduler() const override { return true; }
174 bool enablePostRAScheduler() const override {
175 return UsePostRAScheduler;
178 /// Returns ARM processor family.
179 /// Avoid this function! CPU specifics should be kept local to this class
180 /// and preferably modeled with SubtargetFeatures or properties in
181 /// initializeProperties().
182 ARMProcFamilyEnum getProcFamily() const {
183 return ARMProcFamily;
186 bool hasV8_1aOps() const { return HasV8_1aOps; }
187 bool hasV8_2aOps() const { return HasV8_2aOps; }
189 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
191 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
193 bool requiresStrictAlign() const { return StrictAlign; }
195 bool isXRaySupported() const override { return true; }
197 unsigned getMinVectorRegisterBitWidth() const {
198 return MinVectorRegisterBitWidth;
201 bool isX18Reserved() const { return ReserveX18; }
202 bool hasFPARMv8() const { return HasFPARMv8; }
203 bool hasNEON() const { return HasNEON; }
204 bool hasCrypto() const { return HasCrypto; }
205 bool hasCRC() const { return HasCRC; }
206 bool hasLSE() const { return HasLSE; }
207 bool hasRAS() const { return HasRAS; }
208 bool hasRDM() const { return HasRDM; }
209 bool balanceFPOps() const { return BalanceFPOps; }
210 bool predictableSelectIsExpensive() const {
211 return PredictableSelectIsExpensive;
213 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
214 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
215 bool isPaired128Slow() const { return Paired128IsSlow; }
216 bool useAlternateSExtLoadCVTF32Pattern() const {
217 return UseAlternateSExtLoadCVTF32Pattern;
219 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
220 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
221 bool hasFuseAES() const { return HasFuseAES; }
222 bool hasFuseLiterals() const { return HasFuseLiterals; }
223 bool useRSqrt() const { return UseRSqrt; }
224 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
225 unsigned getVectorInsertExtractBaseCost() const {
226 return VectorInsertExtractBaseCost;
228 unsigned getCacheLineSize() const { return CacheLineSize; }
229 unsigned getPrefetchDistance() const { return PrefetchDistance; }
230 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
231 unsigned getMaxPrefetchIterationsAhead() const {
232 return MaxPrefetchIterationsAhead;
234 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
235 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
237 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
239 unsigned getWideningBaseCost() const { return WideningBaseCost; }
241 /// CPU has TBI (top byte of addresses is ignored during HW address
242 /// translation) and OS enables it.
243 bool supportsAddressTopByteIgnored() const;
245 bool hasPerfMon() const { return HasPerfMon; }
246 bool hasFullFP16() const { return HasFullFP16; }
247 bool hasSPE() const { return HasSPE; }
248 bool hasLSLFast() const { return HasLSLFast; }
250 bool isLittleEndian() const { return IsLittle; }
252 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
253 bool isTargetIOS() const { return TargetTriple.isiOS(); }
254 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
255 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
256 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
257 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
259 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
260 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
261 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
263 bool useAA() const override { return UseAA; }
265 bool useSmallAddressing() const {
266 switch (TLInfo.getTargetMachine().getCodeModel()) {
267 case CodeModel::Kernel:
268 // Kernel is currently allowed only for Fuchsia targets,
269 // where it is the same as Small for almost all purposes.
270 case CodeModel::Small:
277 bool getForCodeSize() const { return ForCodeSize; }
279 /// ParseSubtargetFeatures - Parses features string setting specified
280 /// subtarget options. Definition of function is auto generated by tblgen.
281 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
283 /// ClassifyGlobalReference - Find the target operand flags that describe
284 /// how a global value should be referenced for the current subtarget.
285 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
286 const TargetMachine &TM) const;
288 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
289 const TargetMachine &TM) const;
291 /// This function returns the name of a function which has an interface
292 /// like the non-standard bzero function, if such a function exists on
293 /// the current subtarget and it is considered prefereable over
294 /// memset with zero passed as the second argument. Otherwise it
296 const char *getBZeroEntry() const;
298 void overrideSchedPolicy(MachineSchedPolicy &Policy,
299 unsigned NumRegionInstrs) const override;
301 bool enableEarlyIfConversion() const override;
303 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
305 } // End llvm namespace