1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum : uint8_t {
51 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
52 ARMProcFamilyEnum ARMProcFamily = Others;
54 bool HasV8_1aOps = false;
55 bool HasV8_2aOps = false;
57 bool HasFPARMv8 = false;
59 bool HasCrypto = false;
62 bool HasPerfMon = false;
63 bool HasFullFP16 = false;
66 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
67 bool HasZeroCycleRegMove = false;
69 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
70 bool HasZeroCycleZeroing = false;
72 // StrictAlign - Disallow unaligned memory accesses.
73 bool StrictAlign = false;
74 bool MergeNarrowLoads = false;
76 bool PredictableSelectIsExpensive = false;
77 bool BalanceFPOps = false;
78 bool CustomAsCheapAsMove = false;
79 bool UsePostRAScheduler = false;
80 bool Misaligned128StoreIsSlow = false;
81 bool AvoidQuadLdStPairs = false;
82 bool UseAlternateSExtLoadCVTF32Pattern = false;
83 bool HasMacroOpFusion = false;
84 bool DisableLatencySchedHeuristic = false;
85 bool UseRSqrt = false;
86 uint8_t MaxInterleaveFactor = 2;
87 uint8_t VectorInsertExtractBaseCost = 3;
88 uint16_t CacheLineSize = 0;
89 uint16_t PrefetchDistance = 0;
90 uint16_t MinPrefetchStride = 1;
91 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
92 unsigned PrefFunctionAlignment = 0;
93 unsigned PrefLoopAlignment = 0;
95 // ReserveX18 - X18 is not available as a general purpose register.
100 /// CPUString - String name of used CPU.
101 std::string CPUString;
103 /// TargetTriple - What processor and OS we're targeting.
106 AArch64FrameLowering FrameLowering;
107 AArch64InstrInfo InstrInfo;
108 AArch64SelectionDAGInfo TSInfo;
109 AArch64TargetLowering TLInfo;
110 /// Gather the accessor points to GlobalISel-related APIs.
111 /// This is used to avoid ifndefs spreading around while GISel is
112 /// an optional library.
113 std::unique_ptr<GISelAccessor> GISel;
116 /// initializeSubtargetDependencies - Initializes using CPUString and the
117 /// passed in feature string so that we can use initializer lists for
118 /// subtarget initialization.
119 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
121 /// Initialize properties based on the selected processor family.
122 void initializeProperties();
125 /// This constructor initializes the data members to match that
126 /// of the specified triple.
127 AArch64Subtarget(const Triple &TT, const std::string &CPU,
128 const std::string &FS, const TargetMachine &TM,
131 /// This object will take onwership of \p GISelAccessor.
132 void setGISelAccessor(GISelAccessor &GISel) {
133 this->GISel.reset(&GISel);
136 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
139 const AArch64FrameLowering *getFrameLowering() const override {
140 return &FrameLowering;
142 const AArch64TargetLowering *getTargetLowering() const override {
145 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
146 const AArch64RegisterInfo *getRegisterInfo() const override {
147 return &getInstrInfo()->getRegisterInfo();
149 const CallLowering *getCallLowering() const override;
150 const RegisterBankInfo *getRegBankInfo() const override;
151 const Triple &getTargetTriple() const { return TargetTriple; }
152 bool enableMachineScheduler() const override { return true; }
153 bool enablePostRAScheduler() const override {
154 return UsePostRAScheduler;
157 /// Returns ARM processor family.
158 /// Avoid this function! CPU specifics should be kept local to this class
159 /// and preferably modeled with SubtargetFeatures or properties in
160 /// initializeProperties().
161 ARMProcFamilyEnum getProcFamily() const {
162 return ARMProcFamily;
165 bool hasV8_1aOps() const { return HasV8_1aOps; }
166 bool hasV8_2aOps() const { return HasV8_2aOps; }
168 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
170 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
172 bool requiresStrictAlign() const { return StrictAlign; }
174 bool isX18Reserved() const { return ReserveX18; }
175 bool hasFPARMv8() const { return HasFPARMv8; }
176 bool hasNEON() const { return HasNEON; }
177 bool hasCrypto() const { return HasCrypto; }
178 bool hasCRC() const { return HasCRC; }
179 bool hasRAS() const { return HasRAS; }
180 bool mergeNarrowLoads() const { return MergeNarrowLoads; }
181 bool balanceFPOps() const { return BalanceFPOps; }
182 bool predictableSelectIsExpensive() const {
183 return PredictableSelectIsExpensive;
185 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
186 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
187 bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }
188 bool useAlternateSExtLoadCVTF32Pattern() const {
189 return UseAlternateSExtLoadCVTF32Pattern;
191 bool hasMacroOpFusion() const { return HasMacroOpFusion; }
192 bool useRSqrt() const { return UseRSqrt; }
193 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
194 unsigned getVectorInsertExtractBaseCost() const {
195 return VectorInsertExtractBaseCost;
197 unsigned getCacheLineSize() const { return CacheLineSize; }
198 unsigned getPrefetchDistance() const { return PrefetchDistance; }
199 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
200 unsigned getMaxPrefetchIterationsAhead() const {
201 return MaxPrefetchIterationsAhead;
203 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
204 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
206 /// CPU has TBI (top byte of addresses is ignored during HW address
207 /// translation) and OS enables it.
208 bool supportsAddressTopByteIgnored() const;
210 bool hasPerfMon() const { return HasPerfMon; }
211 bool hasFullFP16() const { return HasFullFP16; }
212 bool hasSPE() const { return HasSPE; }
214 bool isLittleEndian() const { return IsLittle; }
216 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
217 bool isTargetIOS() const { return TargetTriple.isiOS(); }
218 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
219 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
220 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
222 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
223 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
224 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
226 bool useAA() const override { return UseAA; }
228 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
229 /// that still makes it profitable to inline the call.
230 unsigned getMaxInlineSizeThreshold() const { return 64; }
232 /// ParseSubtargetFeatures - Parses features string setting specified
233 /// subtarget options. Definition of function is auto generated by tblgen.
234 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
236 /// ClassifyGlobalReference - Find the target operand flags that describe
237 /// how a global value should be referenced for the current subtarget.
238 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
239 const TargetMachine &TM) const;
241 /// This function returns the name of a function which has an interface
242 /// like the non-standard bzero function, if such a function exists on
243 /// the current subtarget and it is considered prefereable over
244 /// memset with zero passed as the second argument. Otherwise it
246 const char *getBZeroEntry() const;
248 void overrideSchedPolicy(MachineSchedPolicy &Policy,
249 unsigned NumRegionInstrs) const override;
251 bool enableEarlyIfConversion() const override;
253 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
255 } // End llvm namespace