1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "AArch64TargetMachine.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Target/TargetLoweringObjectFile.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47 cl::desc("Enable the CCMP formation pass"),
48 cl::init(true), cl::Hidden);
51 EnableCondBrTuning("aarch64-enable-cond-br-tune",
52 cl::desc("Enable the conditional branch tuning pass"),
53 cl::init(true), cl::Hidden);
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56 cl::desc("Enable the machine combiner pass"),
57 cl::init(true), cl::Hidden);
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60 cl::desc("Suppress STP for AArch64"),
61 cl::init(true), cl::Hidden);
63 static cl::opt<bool> EnableAdvSIMDScalar(
64 "aarch64-enable-simd-scalar",
65 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66 cl::init(false), cl::Hidden);
69 EnablePromoteConstant("aarch64-enable-promote-const",
70 cl::desc("Enable the promote constant pass"),
71 cl::init(true), cl::Hidden);
73 static cl::opt<bool> EnableCollectLOH(
74 "aarch64-enable-collect-loh",
75 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76 cl::init(true), cl::Hidden);
79 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80 cl::desc("Enable the pass that removes dead"
81 " definitons and replaces stores to"
82 " them with stores to the zero"
86 static cl::opt<bool> EnableRedundantCopyElimination(
87 "aarch64-enable-copyelim",
88 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92 cl::desc("Enable the load/store pair"
93 " optimization pass"),
94 cl::init(true), cl::Hidden);
96 static cl::opt<bool> EnableAtomicTidy(
97 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98 cl::desc("Run SimplifyCFG after expanding atomic operations"
99 " to make use of cmpxchg flow-based information"),
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104 cl::desc("Run early if-conversion"),
108 EnableCondOpt("aarch64-enable-condopt",
109 cl::desc("Enable the condition optimizer pass"),
110 cl::init(true), cl::Hidden);
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114 cl::desc("Work around Cortex-A53 erratum 835769"),
118 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119 cl::desc("Enable optimizations on complex GEPs"),
123 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124 cl::desc("Relax out of range conditional branches"));
126 // FIXME: Unify control over GlobalMerge.
127 static cl::opt<cl::boolOrDefault>
128 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
129 cl::desc("Enable the global merge pass"));
132 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
133 cl::desc("Enable the loop data prefetch pass"),
136 static cl::opt<int> EnableGlobalISelAtO(
137 "aarch64-enable-global-isel-at-O", cl::Hidden,
138 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
141 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
142 cl::init(true), cl::Hidden);
144 extern "C" void LLVMInitializeAArch64Target() {
145 // Register the target.
146 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
147 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
148 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
149 auto PR = PassRegistry::getPassRegistry();
150 initializeGlobalISel(*PR);
151 initializeAArch64A53Fix835769Pass(*PR);
152 initializeAArch64A57FPLoadBalancingPass(*PR);
153 initializeAArch64AdvSIMDScalarPass(*PR);
154 initializeAArch64CollectLOHPass(*PR);
155 initializeAArch64ConditionalComparesPass(*PR);
156 initializeAArch64ConditionOptimizerPass(*PR);
157 initializeAArch64DeadRegisterDefinitionsPass(*PR);
158 initializeAArch64ExpandPseudoPass(*PR);
159 initializeAArch64LoadStoreOptPass(*PR);
160 initializeAArch64VectorByElementOptPass(*PR);
161 initializeAArch64PromoteConstantPass(*PR);
162 initializeAArch64RedundantCopyEliminationPass(*PR);
163 initializeAArch64StorePairSuppressPass(*PR);
164 initializeFalkorHWPFFixPass(*PR);
165 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
166 initializeLDTLSCleanupPass(*PR);
169 //===----------------------------------------------------------------------===//
170 // AArch64 Lowering public interface.
171 //===----------------------------------------------------------------------===//
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173 if (TT.isOSBinFormatMachO())
174 return llvm::make_unique<AArch64_MachoTargetObjectFile>();
175 if (TT.isOSBinFormatCOFF())
176 return llvm::make_unique<AArch64_COFFTargetObjectFile>();
178 return llvm::make_unique<AArch64_ELFTargetObjectFile>();
181 // Helper function to build a DataLayout string
182 static std::string computeDataLayout(const Triple &TT,
183 const MCTargetOptions &Options,
185 if (Options.getABIName() == "ilp32")
186 return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
187 if (TT.isOSBinFormatMachO())
188 return "e-m:o-i64:64-i128:128-n32:64-S128";
189 if (TT.isOSBinFormatCOFF())
190 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
192 return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
193 return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
196 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
197 Optional<Reloc::Model> RM) {
198 // AArch64 Darwin is always PIC.
201 // On ELF platforms the default static relocation model has a smart enough
202 // linker to cope with referencing external symbols defined in a shared
203 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
204 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
205 return Reloc::Static;
209 /// Create an AArch64 architecture model.
211 AArch64TargetMachine::AArch64TargetMachine(
212 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
213 const TargetOptions &Options, Optional<Reloc::Model> RM,
214 CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
215 // This nested ternary is horrible, but DL needs to be properly
216 // initialized before TLInfo is constructed.
217 : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
219 TT, CPU, FS, Options,
220 getEffectiveRelocModel(TT, RM), CM, OL),
221 TLOF(createTLOF(getTargetTriple())),
222 isLittle(LittleEndian) {
226 AArch64TargetMachine::~AArch64TargetMachine() = default;
228 const AArch64Subtarget *
229 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
230 Attribute CPUAttr = F.getFnAttribute("target-cpu");
231 Attribute FSAttr = F.getFnAttribute("target-features");
233 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
234 ? CPUAttr.getValueAsString().str()
236 std::string FS = !FSAttr.hasAttribute(Attribute::None)
237 ? FSAttr.getValueAsString().str()
240 auto &I = SubtargetMap[CPU + FS];
242 // This needs to be done before we create a new subtarget since any
243 // creation will depend on the TM and the code generation flags on the
244 // function that reside in TargetOptions.
245 resetTargetOptions(F);
246 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
252 void AArch64leTargetMachine::anchor() { }
254 AArch64leTargetMachine::AArch64leTargetMachine(
255 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
256 const TargetOptions &Options, Optional<Reloc::Model> RM,
257 CodeModel::Model CM, CodeGenOpt::Level OL)
258 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
260 void AArch64beTargetMachine::anchor() { }
262 AArch64beTargetMachine::AArch64beTargetMachine(
263 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
264 const TargetOptions &Options, Optional<Reloc::Model> RM,
265 CodeModel::Model CM, CodeGenOpt::Level OL)
266 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
270 /// AArch64 Code Generator Pass Configuration Options.
271 class AArch64PassConfig : public TargetPassConfig {
273 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
274 : TargetPassConfig(TM, PM) {
275 if (TM.getOptLevel() != CodeGenOpt::None)
276 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
279 AArch64TargetMachine &getAArch64TargetMachine() const {
280 return getTM<AArch64TargetMachine>();
284 createMachineScheduler(MachineSchedContext *C) const override {
285 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
286 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
287 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
288 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
290 DAG->addMutation(createAArch64MacroFusionDAGMutation());
295 createPostMachineScheduler(MachineSchedContext *C) const override {
296 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
297 if (ST.hasFusion()) {
298 // Run the Macro Fusion after RA again since literals are expanded from
299 // pseudos then (v. addPreSched2()).
300 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
301 DAG->addMutation(createAArch64MacroFusionDAGMutation());
308 void addIRPasses() override;
309 bool addPreISel() override;
310 bool addInstSelector() override;
311 #ifdef LLVM_BUILD_GLOBAL_ISEL
312 bool addIRTranslator() override;
313 bool addLegalizeMachineIR() override;
314 bool addRegBankSelect() override;
315 void addPreGlobalInstructionSelect() override;
316 bool addGlobalInstructionSelect() override;
318 bool addILPOpts() override;
319 void addPreRegAlloc() override;
320 void addPostRegAlloc() override;
321 void addPreSched2() override;
322 void addPreEmitPass() override;
324 bool isGlobalISelEnabled() const override;
327 } // end anonymous namespace
329 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
330 return TargetIRAnalysis([this](const Function &F) {
331 return TargetTransformInfo(AArch64TTIImpl(this, F));
335 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
336 return new AArch64PassConfig(*this, PM);
339 void AArch64PassConfig::addIRPasses() {
340 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
342 addPass(createAtomicExpandPass());
344 // Cmpxchg instructions are often used with a subsequent comparison to
345 // determine whether it succeeded. We can exploit existing control-flow in
346 // ldrex/strex loops to simplify this, but it needs tidying up.
347 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
348 addPass(createCFGSimplificationPass());
350 // Run LoopDataPrefetch
352 // Run this before LSR to remove the multiplies involved in computing the
353 // pointer values N iterations ahead.
354 if (TM->getOptLevel() != CodeGenOpt::None) {
355 if (EnableLoopDataPrefetch)
356 addPass(createLoopDataPrefetchPass());
357 if (EnableFalkorHWPFFix)
358 addPass(createFalkorMarkStridedAccessesPass());
361 TargetPassConfig::addIRPasses();
363 // Match interleaved memory accesses to ldN/stN intrinsics.
364 if (TM->getOptLevel() != CodeGenOpt::None)
365 addPass(createInterleavedAccessPass());
367 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
368 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
369 // and lower a GEP with multiple indices to either arithmetic operations or
370 // multiple GEPs with single index.
371 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
372 // Call EarlyCSE pass to find and remove subexpressions in the lowered
374 addPass(createEarlyCSEPass());
375 // Do loop invariant code motion in case part of the lowered result is
377 addPass(createLICMPass());
381 // Pass Pipeline Configuration
382 bool AArch64PassConfig::addPreISel() {
383 // Run promote constant before global merge, so that the promoted constants
384 // get a chance to be merged
385 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
386 addPass(createAArch64PromoteConstantPass());
387 // FIXME: On AArch64, this depends on the type.
388 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
389 // and the offset has to be a multiple of the related size in bytes.
390 if ((TM->getOptLevel() != CodeGenOpt::None &&
391 EnableGlobalMerge == cl::BOU_UNSET) ||
392 EnableGlobalMerge == cl::BOU_TRUE) {
393 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
394 (EnableGlobalMerge == cl::BOU_UNSET);
395 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
401 bool AArch64PassConfig::addInstSelector() {
402 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
404 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
405 // references to _TLS_MODULE_BASE_ as possible.
406 if (TM->getTargetTriple().isOSBinFormatELF() &&
407 getOptLevel() != CodeGenOpt::None)
408 addPass(createAArch64CleanupLocalDynamicTLSPass());
413 #ifdef LLVM_BUILD_GLOBAL_ISEL
414 bool AArch64PassConfig::addIRTranslator() {
415 addPass(new IRTranslator());
419 bool AArch64PassConfig::addLegalizeMachineIR() {
420 addPass(new Legalizer());
424 bool AArch64PassConfig::addRegBankSelect() {
425 addPass(new RegBankSelect());
429 void AArch64PassConfig::addPreGlobalInstructionSelect() {
430 // Workaround the deficiency of the fast register allocator.
431 if (TM->getOptLevel() == CodeGenOpt::None)
432 addPass(new Localizer());
435 bool AArch64PassConfig::addGlobalInstructionSelect() {
436 addPass(new InstructionSelect());
441 bool AArch64PassConfig::isGlobalISelEnabled() const {
442 return TM->getOptLevel() <= EnableGlobalISelAtO;
445 bool AArch64PassConfig::addILPOpts() {
447 addPass(createAArch64ConditionOptimizerPass());
449 addPass(createAArch64ConditionalCompares());
451 addPass(&MachineCombinerID);
452 if (EnableCondBrTuning)
453 addPass(createAArch64CondBrTuning());
454 if (EnableEarlyIfConversion)
455 addPass(&EarlyIfConverterID);
456 if (EnableStPairSuppress)
457 addPass(createAArch64StorePairSuppressPass());
458 addPass(createAArch64VectorByElementOptPass());
462 void AArch64PassConfig::addPreRegAlloc() {
463 // Change dead register definitions to refer to the zero register.
464 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
465 addPass(createAArch64DeadRegisterDefinitions());
467 // Use AdvSIMD scalar instructions whenever profitable.
468 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
469 addPass(createAArch64AdvSIMDScalar());
470 // The AdvSIMD pass may produce copies that can be rewritten to
471 // be register coaleascer friendly.
472 addPass(&PeepholeOptimizerID);
476 void AArch64PassConfig::addPostRegAlloc() {
477 // Remove redundant copy instructions.
478 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
479 addPass(createAArch64RedundantCopyEliminationPass());
481 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
482 // Improve performance for some FP/SIMD code for A57.
483 addPass(createAArch64A57FPLoadBalancing());
486 void AArch64PassConfig::addPreSched2() {
487 // Expand some pseudo instructions to allow proper scheduling.
488 addPass(createAArch64ExpandPseudoPass());
489 // Use load/store pair instructions when possible.
490 if (TM->getOptLevel() != CodeGenOpt::None) {
491 if (EnableLoadStoreOpt)
492 addPass(createAArch64LoadStoreOptimizationPass());
493 if (EnableFalkorHWPFFix)
494 addPass(createFalkorHWPFFixPass());
498 void AArch64PassConfig::addPreEmitPass() {
499 if (EnableA53Fix835769)
500 addPass(createAArch64A53Fix835769());
501 // Relax conditional branch instructions if they're otherwise out of
502 // range of their destination.
503 if (BranchRelaxation)
504 addPass(&BranchRelaxationPassID);
506 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
507 TM->getTargetTriple().isOSBinFormatMachO())
508 addPass(createAArch64CollectLOHPass());