1 //===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "AArch64TargetTransformInfo.h"
11 #include "MCTargetDesc/AArch64AddressingModes.h"
12 #include "llvm/Analysis/LoopInfo.h"
13 #include "llvm/Analysis/TargetTransformInfo.h"
14 #include "llvm/CodeGen/BasicTTIImpl.h"
15 #include "llvm/CodeGen/CostTable.h"
16 #include "llvm/CodeGen/TargetLowering.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/Support/Debug.h"
22 #define DEBUG_TYPE "aarch64tti"
24 static cl::opt<bool> EnableFalkorHWPFUnrollFix("enable-falkor-hwpf-unroll-fix",
25 cl::init(true), cl::Hidden);
27 bool AArch64TTIImpl::areInlineCompatible(const Function *Caller,
28 const Function *Callee) const {
29 const TargetMachine &TM = getTLI()->getTargetMachine();
31 const FeatureBitset &CallerBits =
32 TM.getSubtargetImpl(*Caller)->getFeatureBits();
33 const FeatureBitset &CalleeBits =
34 TM.getSubtargetImpl(*Callee)->getFeatureBits();
36 // Inline a callee if its target-features are a subset of the callers
38 return (CallerBits & CalleeBits) == CalleeBits;
41 /// \brief Calculate the cost of materializing a 64-bit value. This helper
42 /// method might only calculate a fraction of a larger immediate. Therefore it
43 /// is valid to return a cost of ZERO.
44 int AArch64TTIImpl::getIntImmCost(int64_t Val) {
45 // Check if the immediate can be encoded within an instruction.
46 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, 64))
52 // Calculate how many moves we will need to materialize this constant.
53 unsigned LZ = countLeadingZeros((uint64_t)Val);
54 return (64 - LZ + 15) / 16;
57 /// \brief Calculate the cost of materializing the given constant.
58 int AArch64TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
59 assert(Ty->isIntegerTy());
61 unsigned BitSize = Ty->getPrimitiveSizeInBits();
65 // Sign-extend all constants to a multiple of 64-bit.
68 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
70 // Split the constant into 64-bit chunks and calculate the cost for each
73 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
74 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
75 int64_t Val = Tmp.getSExtValue();
76 Cost += getIntImmCost(Val);
78 // We need at least one instruction to materialze the constant.
79 return std::max(1, Cost);
82 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
83 const APInt &Imm, Type *Ty) {
84 assert(Ty->isIntegerTy());
86 unsigned BitSize = Ty->getPrimitiveSizeInBits();
87 // There is no cost model for constants with a bit size of 0. Return TCC_Free
88 // here, so that constant hoisting will ignore this constant.
92 unsigned ImmIdx = ~0U;
96 case Instruction::GetElementPtr:
97 // Always hoist the base address of a GetElementPtr.
99 return 2 * TTI::TCC_Basic;
100 return TTI::TCC_Free;
101 case Instruction::Store:
104 case Instruction::Add:
105 case Instruction::Sub:
106 case Instruction::Mul:
107 case Instruction::UDiv:
108 case Instruction::SDiv:
109 case Instruction::URem:
110 case Instruction::SRem:
111 case Instruction::And:
112 case Instruction::Or:
113 case Instruction::Xor:
114 case Instruction::ICmp:
117 // Always return TCC_Free for the shift value of a shift instruction.
118 case Instruction::Shl:
119 case Instruction::LShr:
120 case Instruction::AShr:
122 return TTI::TCC_Free;
124 case Instruction::Trunc:
125 case Instruction::ZExt:
126 case Instruction::SExt:
127 case Instruction::IntToPtr:
128 case Instruction::PtrToInt:
129 case Instruction::BitCast:
130 case Instruction::PHI:
131 case Instruction::Call:
132 case Instruction::Select:
133 case Instruction::Ret:
134 case Instruction::Load:
139 int NumConstants = (BitSize + 63) / 64;
140 int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
141 return (Cost <= NumConstants * TTI::TCC_Basic)
142 ? static_cast<int>(TTI::TCC_Free)
145 return AArch64TTIImpl::getIntImmCost(Imm, Ty);
148 int AArch64TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
149 const APInt &Imm, Type *Ty) {
150 assert(Ty->isIntegerTy());
152 unsigned BitSize = Ty->getPrimitiveSizeInBits();
153 // There is no cost model for constants with a bit size of 0. Return TCC_Free
154 // here, so that constant hoisting will ignore this constant.
156 return TTI::TCC_Free;
160 return TTI::TCC_Free;
161 case Intrinsic::sadd_with_overflow:
162 case Intrinsic::uadd_with_overflow:
163 case Intrinsic::ssub_with_overflow:
164 case Intrinsic::usub_with_overflow:
165 case Intrinsic::smul_with_overflow:
166 case Intrinsic::umul_with_overflow:
168 int NumConstants = (BitSize + 63) / 64;
169 int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
170 return (Cost <= NumConstants * TTI::TCC_Basic)
171 ? static_cast<int>(TTI::TCC_Free)
175 case Intrinsic::experimental_stackmap:
176 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
177 return TTI::TCC_Free;
179 case Intrinsic::experimental_patchpoint_void:
180 case Intrinsic::experimental_patchpoint_i64:
181 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
182 return TTI::TCC_Free;
185 return AArch64TTIImpl::getIntImmCost(Imm, Ty);
188 TargetTransformInfo::PopcntSupportKind
189 AArch64TTIImpl::getPopcntSupport(unsigned TyWidth) {
190 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
191 if (TyWidth == 32 || TyWidth == 64)
192 return TTI::PSK_FastHardware;
193 // TODO: AArch64TargetLowering::LowerCTPOP() supports 128bit popcount.
194 return TTI::PSK_Software;
197 bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
198 ArrayRef<const Value *> Args) {
200 // A helper that returns a vector type from the given type. The number of
201 // elements in type Ty determine the vector width.
202 auto toVectorTy = [&](Type *ArgTy) {
203 return VectorType::get(ArgTy->getScalarType(),
204 DstTy->getVectorNumElements());
207 // Exit early if DstTy is not a vector type whose elements are at least
209 if (!DstTy->isVectorTy() || DstTy->getScalarSizeInBits() < 16)
212 // Determine if the operation has a widening variant. We consider both the
213 // "long" (e.g., usubl) and "wide" (e.g., usubw) versions of the
216 // TODO: Add additional widening operations (e.g., mul, shl, etc.) once we
217 // verify that their extending operands are eliminated during code
220 case Instruction::Add: // UADDL(2), SADDL(2), UADDW(2), SADDW(2).
221 case Instruction::Sub: // USUBL(2), SSUBL(2), USUBW(2), SSUBW(2).
227 // To be a widening instruction (either the "wide" or "long" versions), the
228 // second operand must be a sign- or zero extend having a single user. We
229 // only consider extends having a single user because they may otherwise not
231 if (Args.size() != 2 ||
232 (!isa<SExtInst>(Args[1]) && !isa<ZExtInst>(Args[1])) ||
233 !Args[1]->hasOneUse())
235 auto *Extend = cast<CastInst>(Args[1]);
237 // Legalize the destination type and ensure it can be used in a widening
239 auto DstTyL = TLI->getTypeLegalizationCost(DL, DstTy);
240 unsigned DstElTySize = DstTyL.second.getScalarSizeInBits();
241 if (!DstTyL.second.isVector() || DstElTySize != DstTy->getScalarSizeInBits())
244 // Legalize the source type and ensure it can be used in a widening
246 Type *SrcTy = toVectorTy(Extend->getSrcTy());
247 auto SrcTyL = TLI->getTypeLegalizationCost(DL, SrcTy);
248 unsigned SrcElTySize = SrcTyL.second.getScalarSizeInBits();
249 if (!SrcTyL.second.isVector() || SrcElTySize != SrcTy->getScalarSizeInBits())
252 // Get the total number of vector elements in the legalized types.
253 unsigned NumDstEls = DstTyL.first * DstTyL.second.getVectorNumElements();
254 unsigned NumSrcEls = SrcTyL.first * SrcTyL.second.getVectorNumElements();
256 // Return true if the legalized types have the same number of vector elements
257 // and the destination element type size is twice that of the source type.
258 return NumDstEls == NumSrcEls && 2 * SrcElTySize == DstElTySize;
261 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
262 const Instruction *I) {
263 int ISD = TLI->InstructionOpcodeToISD(Opcode);
264 assert(ISD && "Invalid opcode");
266 // If the cast is observable, and it is used by a widening instruction (e.g.,
267 // uaddl, saddw, etc.), it may be free.
268 if (I && I->hasOneUse()) {
269 auto *SingleUser = cast<Instruction>(*I->user_begin());
270 SmallVector<const Value *, 4> Operands(SingleUser->operand_values());
271 if (isWideningInstruction(Dst, SingleUser->getOpcode(), Operands)) {
272 // If the cast is the second operand, it is free. We will generate either
273 // a "wide" or "long" version of the widening instruction.
274 if (I == SingleUser->getOperand(1))
276 // If the cast is not the second operand, it will be free if it looks the
277 // same as the second operand. In this case, we will generate a "long"
278 // version of the widening instruction.
279 if (auto *Cast = dyn_cast<CastInst>(SingleUser->getOperand(1)))
280 if (I->getOpcode() == Cast->getOpcode() &&
281 cast<CastInst>(I)->getSrcTy() == Cast->getSrcTy())
286 EVT SrcTy = TLI->getValueType(DL, Src);
287 EVT DstTy = TLI->getValueType(DL, Dst);
289 if (!SrcTy.isSimple() || !DstTy.isSimple())
290 return BaseT::getCastInstrCost(Opcode, Dst, Src);
292 static const TypeConversionCostTblEntry
294 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
295 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
296 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
297 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
299 // The number of shll instructions for the extension.
300 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
301 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
302 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
303 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
304 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
305 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
306 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
307 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
308 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
309 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
310 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
311 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
312 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
313 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
314 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
315 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
317 // LowerVectorINT_TO_FP:
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
321 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
322 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
323 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
327 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
328 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
329 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
330 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
331 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
334 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
335 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
336 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
340 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
341 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
342 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
343 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
345 // Complex: to v16f32
346 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
347 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
350 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
351 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
352 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
353 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
354 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
355 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
358 // LowerVectorFP_TO_INT
359 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
360 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
361 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
362 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
363 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
364 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
366 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
367 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
368 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
369 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
370 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
371 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
372 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
374 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
375 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
376 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
377 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
378 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
380 // Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
381 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
382 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
383 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
384 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
385 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
386 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
389 if (const auto *Entry = ConvertCostTableLookup(ConversionTbl, ISD,
391 SrcTy.getSimpleVT()))
394 return BaseT::getCastInstrCost(Opcode, Dst, Src);
397 int AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
401 // Make sure we were given a valid extend opcode.
402 assert((Opcode == Instruction::SExt || Opcode == Instruction::ZExt) &&
405 // We are extending an element we extract from a vector, so the source type
406 // of the extend is the element type of the vector.
407 auto *Src = VecTy->getElementType();
409 // Sign- and zero-extends are for integer types only.
410 assert(isa<IntegerType>(Dst) && isa<IntegerType>(Src) && "Invalid type");
412 // Get the cost for the extract. We compute the cost (if any) for the extend
414 auto Cost = getVectorInstrCost(Instruction::ExtractElement, VecTy, Index);
416 // Legalize the types.
417 auto VecLT = TLI->getTypeLegalizationCost(DL, VecTy);
418 auto DstVT = TLI->getValueType(DL, Dst);
419 auto SrcVT = TLI->getValueType(DL, Src);
421 // If the resulting type is still a vector and the destination type is legal,
422 // we may get the extension for free. If not, get the default cost for the
424 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT))
425 return Cost + getCastInstrCost(Opcode, Dst, Src);
427 // The destination type should be larger than the element type. If not, get
428 // the default cost for the extend.
429 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits())
430 return Cost + getCastInstrCost(Opcode, Dst, Src);
434 llvm_unreachable("Opcode should be either SExt or ZExt");
436 // For sign-extends, we only need a smov, which performs the extension
438 case Instruction::SExt:
441 // For zero-extends, the extend is performed automatically by a umov unless
442 // the destination type is i64 and the element type is i8 or i16.
443 case Instruction::ZExt:
444 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
448 // If we are unable to perform the extend for free, get the default cost.
449 return Cost + getCastInstrCost(Opcode, Dst, Src);
452 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
454 assert(Val->isVectorTy() && "This must be a vector type");
457 // Legalize the type.
458 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
460 // This type is legalized to a scalar type.
461 if (!LT.second.isVector())
464 // The type may be split. Normalize the index to the new type.
465 unsigned Width = LT.second.getVectorNumElements();
466 Index = Index % Width;
468 // The element at index zero is already inside the vector.
473 // All other insert/extracts cost this much.
474 return ST->getVectorInsertExtractBaseCost();
477 int AArch64TTIImpl::getArithmeticInstrCost(
478 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
479 TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
480 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
481 // Legalize the type.
482 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
484 // If the instruction is a widening instruction (e.g., uaddl, saddw, etc.),
485 // add in the widening overhead specified by the sub-target. Since the
486 // extends feeding widening instructions are performed automatically, they
487 // aren't present in the generated code and have a zero cost. By adding a
488 // widening overhead here, we attach the total cost of the combined operation
489 // to the widening instruction.
491 if (isWideningInstruction(Ty, Opcode, Args))
492 Cost += ST->getWideningBaseCost();
494 int ISD = TLI->InstructionOpcodeToISD(Opcode);
496 if (ISD == ISD::SDIV &&
497 Opd2Info == TargetTransformInfo::OK_UniformConstantValue &&
498 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
499 // On AArch64, scalar signed division by constants power-of-two are
500 // normally expanded to the sequence ADD + CMP + SELECT + SRA.
501 // The OperandValue properties many not be same as that of previous
502 // operation; conservatively assume OP_None.
503 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Opd1Info, Opd2Info,
504 TargetTransformInfo::OP_None,
505 TargetTransformInfo::OP_None);
506 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Opd1Info, Opd2Info,
507 TargetTransformInfo::OP_None,
508 TargetTransformInfo::OP_None);
509 Cost += getArithmeticInstrCost(Instruction::Select, Ty, Opd1Info, Opd2Info,
510 TargetTransformInfo::OP_None,
511 TargetTransformInfo::OP_None);
512 Cost += getArithmeticInstrCost(Instruction::AShr, Ty, Opd1Info, Opd2Info,
513 TargetTransformInfo::OP_None,
514 TargetTransformInfo::OP_None);
520 return Cost + BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
521 Opd1PropInfo, Opd2PropInfo);
527 // These nodes are marked as 'custom' for combining purposes only.
528 // We know that they are legal. See LowerAdd in ISelLowering.
529 return (Cost + 1) * LT.first;
533 int AArch64TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
535 // Address computations in vectorized code with non-consecutive addresses will
536 // likely result in more instructions compared to scalar code where the
537 // computation can more often be merged into the index mode. The resulting
538 // extra micro-ops can significantly decrease throughput.
539 unsigned NumVectorInstToHideOverhead = 10;
540 int MaxMergeDistance = 64;
542 if (Ty->isVectorTy() && SE &&
543 !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
544 return NumVectorInstToHideOverhead;
546 // In many cases the address computation is not merged into the instruction
551 int AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
552 Type *CondTy, const Instruction *I) {
554 int ISD = TLI->InstructionOpcodeToISD(Opcode);
555 // We don't lower some vector selects well that are wider than the register
557 if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
558 // We would need this many instructions to hide the scalarization happening.
559 const int AmortizationCost = 20;
560 static const TypeConversionCostTblEntry
561 VectorSelectTbl[] = {
562 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 },
563 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
564 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
565 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
566 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
567 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
570 EVT SelCondTy = TLI->getValueType(DL, CondTy);
571 EVT SelValTy = TLI->getValueType(DL, ValTy);
572 if (SelCondTy.isSimple() && SelValTy.isSimple()) {
573 if (const auto *Entry = ConvertCostTableLookup(VectorSelectTbl, ISD,
574 SelCondTy.getSimpleVT(),
575 SelValTy.getSimpleVT()))
579 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
582 int AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
583 unsigned Alignment, unsigned AddressSpace,
584 const Instruction *I) {
585 auto LT = TLI->getTypeLegalizationCost(DL, Ty);
587 if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
588 LT.second.is128BitVector() && Alignment < 16) {
589 // Unaligned stores are extremely inefficient. We don't split all
590 // unaligned 128-bit stores because the negative impact that has shown in
591 // practice on inlined block copy code.
592 // We make such stores expensive so that we will only vectorize if there
593 // are 6 other instructions getting vectorized.
594 const int AmortizationCost = 6;
596 return LT.first * 2 * AmortizationCost;
599 if (Ty->isVectorTy() && Ty->getVectorElementType()->isIntegerTy(8) &&
600 Ty->getVectorNumElements() < 8) {
601 // We scalarize the loads/stores because there is not v.4b register and we
602 // have to promote the elements to v.4h.
603 unsigned NumVecElts = Ty->getVectorNumElements();
604 unsigned NumVectorizableInstsToAmortize = NumVecElts * 2;
605 // We generate 2 instructions per vector element.
606 return NumVectorizableInstsToAmortize * NumVecElts * 2;
612 int AArch64TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
614 ArrayRef<unsigned> Indices,
616 unsigned AddressSpace) {
617 assert(Factor >= 2 && "Invalid interleave factor");
618 assert(isa<VectorType>(VecTy) && "Expect a vector type");
620 if (Factor <= TLI->getMaxSupportedInterleaveFactor()) {
621 unsigned NumElts = VecTy->getVectorNumElements();
622 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
624 // ldN/stN only support legal vector types of size 64 or 128 in bits.
625 // Accesses having vector types that are a multiple of 128 bits can be
626 // matched to more than one ldN/stN instruction.
627 if (NumElts % Factor == 0 &&
628 TLI->isLegalInterleavedAccessType(SubVecTy, DL))
629 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL);
632 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
633 Alignment, AddressSpace);
636 int AArch64TTIImpl::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) {
638 for (auto *I : Tys) {
639 if (!I->isVectorTy())
641 if (I->getScalarSizeInBits() * I->getVectorNumElements() == 128)
642 Cost += getMemoryOpCost(Instruction::Store, I, 128, 0) +
643 getMemoryOpCost(Instruction::Load, I, 128, 0);
648 unsigned AArch64TTIImpl::getMaxInterleaveFactor(unsigned VF) {
649 return ST->getMaxInterleaveFactor();
652 // For Falkor, we want to avoid having too many strided loads in a loop since
653 // that can exhaust the HW prefetcher resources. We adjust the unroller
654 // MaxCount preference below to attempt to ensure unrolling doesn't create too
655 // many strided loads.
657 getFalkorUnrollingPreferences(Loop *L, ScalarEvolution &SE,
658 TargetTransformInfo::UnrollingPreferences &UP) {
659 enum { MaxStridedLoads = 7 };
660 auto countStridedLoads = [](Loop *L, ScalarEvolution &SE) {
661 int StridedLoads = 0;
662 // FIXME? We could make this more precise by looking at the CFG and
663 // e.g. not counting loads in each side of an if-then-else diamond.
664 for (const auto BB : L->blocks()) {
665 for (auto &I : *BB) {
666 LoadInst *LMemI = dyn_cast<LoadInst>(&I);
670 Value *PtrValue = LMemI->getPointerOperand();
671 if (L->isLoopInvariant(PtrValue))
674 const SCEV *LSCEV = SE.getSCEV(PtrValue);
675 const SCEVAddRecExpr *LSCEVAddRec = dyn_cast<SCEVAddRecExpr>(LSCEV);
676 if (!LSCEVAddRec || !LSCEVAddRec->isAffine())
679 // FIXME? We could take pairing of unrolled load copies into account
680 // by looking at the AddRec, but we would probably have to limit this
681 // to loops with no stores or other memory optimization barriers.
683 // We've seen enough strided loads that seeing more won't make a
685 if (StridedLoads > MaxStridedLoads / 2)
692 int StridedLoads = countStridedLoads(L, SE);
693 DEBUG(dbgs() << "falkor-hwpf: detected " << StridedLoads
694 << " strided loads\n");
695 // Pick the largest power of 2 unroll count that won't result in too many
698 UP.MaxCount = 1 << Log2_32(MaxStridedLoads / StridedLoads);
699 DEBUG(dbgs() << "falkor-hwpf: setting unroll MaxCount to " << UP.MaxCount
704 void AArch64TTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
705 TTI::UnrollingPreferences &UP) {
706 // Enable partial unrolling and runtime unrolling.
707 BaseT::getUnrollingPreferences(L, SE, UP);
709 // For inner loop, it is more likely to be a hot one, and the runtime check
710 // can be promoted out from LICM pass, so the overhead is less, let's try
711 // a larger threshold to unroll more loops.
712 if (L->getLoopDepth() > 1)
713 UP.PartialThreshold *= 2;
715 // Disable partial & runtime unrolling on -Os.
716 UP.PartialOptSizeThreshold = 0;
718 if (ST->getProcFamily() == AArch64Subtarget::Falkor &&
719 EnableFalkorHWPFUnrollFix)
720 getFalkorUnrollingPreferences(L, SE, UP);
723 Value *AArch64TTIImpl::getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
724 Type *ExpectedType) {
725 switch (Inst->getIntrinsicID()) {
728 case Intrinsic::aarch64_neon_st2:
729 case Intrinsic::aarch64_neon_st3:
730 case Intrinsic::aarch64_neon_st4: {
731 // Create a struct type
732 StructType *ST = dyn_cast<StructType>(ExpectedType);
735 unsigned NumElts = Inst->getNumArgOperands() - 1;
736 if (ST->getNumElements() != NumElts)
738 for (unsigned i = 0, e = NumElts; i != e; ++i) {
739 if (Inst->getArgOperand(i)->getType() != ST->getElementType(i))
742 Value *Res = UndefValue::get(ExpectedType);
743 IRBuilder<> Builder(Inst);
744 for (unsigned i = 0, e = NumElts; i != e; ++i) {
745 Value *L = Inst->getArgOperand(i);
746 Res = Builder.CreateInsertValue(Res, L, i);
750 case Intrinsic::aarch64_neon_ld2:
751 case Intrinsic::aarch64_neon_ld3:
752 case Intrinsic::aarch64_neon_ld4:
753 if (Inst->getType() == ExpectedType)
759 bool AArch64TTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
760 MemIntrinsicInfo &Info) {
761 switch (Inst->getIntrinsicID()) {
764 case Intrinsic::aarch64_neon_ld2:
765 case Intrinsic::aarch64_neon_ld3:
766 case Intrinsic::aarch64_neon_ld4:
768 Info.WriteMem = false;
769 Info.PtrVal = Inst->getArgOperand(0);
771 case Intrinsic::aarch64_neon_st2:
772 case Intrinsic::aarch64_neon_st3:
773 case Intrinsic::aarch64_neon_st4:
774 Info.ReadMem = false;
775 Info.WriteMem = true;
776 Info.PtrVal = Inst->getArgOperand(Inst->getNumArgOperands() - 1);
780 switch (Inst->getIntrinsicID()) {
783 case Intrinsic::aarch64_neon_ld2:
784 case Intrinsic::aarch64_neon_st2:
785 Info.MatchingId = VECTOR_LDST_TWO_ELEMENTS;
787 case Intrinsic::aarch64_neon_ld3:
788 case Intrinsic::aarch64_neon_st3:
789 Info.MatchingId = VECTOR_LDST_THREE_ELEMENTS;
791 case Intrinsic::aarch64_neon_ld4:
792 case Intrinsic::aarch64_neon_st4:
793 Info.MatchingId = VECTOR_LDST_FOUR_ELEMENTS;
799 /// See if \p I should be considered for address type promotion. We check if \p
800 /// I is a sext with right type and used in memory accesses. If it used in a
801 /// "complex" getelementptr, we allow it to be promoted without finding other
802 /// sext instructions that sign extended the same initial value. A getelementptr
803 /// is considered as "complex" if it has more than 2 operands.
804 bool AArch64TTIImpl::shouldConsiderAddressTypePromotion(
805 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) {
806 bool Considerable = false;
807 AllowPromotionWithoutCommonHeader = false;
808 if (!isa<SExtInst>(&I))
810 Type *ConsideredSExtType =
811 Type::getInt64Ty(I.getParent()->getParent()->getContext());
812 if (I.getType() != ConsideredSExtType)
814 // See if the sext is the one with the right type and used in at least one
815 // GetElementPtrInst.
816 for (const User *U : I.users()) {
817 if (const GetElementPtrInst *GEPInst = dyn_cast<GetElementPtrInst>(U)) {
819 // A getelementptr is considered as "complex" if it has more than 2
820 // operands. We will promote a SExt used in such complex GEP as we
821 // expect some computation to be merged if they are done on 64 bits.
822 if (GEPInst->getNumOperands() > 2) {
823 AllowPromotionWithoutCommonHeader = true;
831 unsigned AArch64TTIImpl::getCacheLineSize() {
832 return ST->getCacheLineSize();
835 unsigned AArch64TTIImpl::getPrefetchDistance() {
836 return ST->getPrefetchDistance();
839 unsigned AArch64TTIImpl::getMinPrefetchStride() {
840 return ST->getMinPrefetchStride();
843 unsigned AArch64TTIImpl::getMaxPrefetchIterationsAhead() {
844 return ST->getMaxPrefetchIterationsAhead();
847 bool AArch64TTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
848 TTI::ReductionFlags Flags) const {
849 assert(isa<VectorType>(Ty) && "Expected Ty to be a vector type");
850 unsigned ScalarBits = Ty->getScalarSizeInBits();
852 case Instruction::FAdd:
853 case Instruction::FMul:
854 case Instruction::And:
855 case Instruction::Or:
856 case Instruction::Xor:
857 case Instruction::Mul:
859 case Instruction::Add:
860 return ScalarBits * Ty->getVectorNumElements() >= 128;
861 case Instruction::ICmp:
862 return (ScalarBits < 64) &&
863 (ScalarBits * Ty->getVectorNumElements() >= 128);
864 case Instruction::FCmp:
867 llvm_unreachable("Unhandled reduction opcode");