1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AArch64 target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
21 #include "AArch64Subtarget.h"
22 #include "AArch64TargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/BasicTTIImpl.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
37 class ScalarEvolution;
42 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
43 using BaseT = BasicTTIImplBase<AArch64TTIImpl>;
44 using TTI = TargetTransformInfo;
48 const AArch64Subtarget *ST;
49 const AArch64TargetLowering *TLI;
51 const AArch64Subtarget *getST() const { return ST; }
52 const AArch64TargetLowering *getTLI() const { return TLI; }
54 enum MemIntrinsicType {
55 VECTOR_LDST_TWO_ELEMENTS,
56 VECTOR_LDST_THREE_ELEMENTS,
57 VECTOR_LDST_FOUR_ELEMENTS
60 bool isWideningInstruction(Type *Ty, unsigned Opcode,
61 ArrayRef<const Value *> Args);
64 explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
65 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
66 TLI(ST->getTargetLowering()) {}
68 bool areInlineCompatible(const Function *Caller,
69 const Function *Callee) const;
71 /// \name Scalar TTI Implementations
74 using BaseT::getIntImmCost;
75 int getIntImmCost(int64_t Val);
76 int getIntImmCost(const APInt &Imm, Type *Ty);
77 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
78 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
80 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
84 /// \name Vector TTI Implementations
87 bool enableInterleavedAccessVectorization() { return true; }
89 unsigned getNumberOfRegisters(bool Vector) {
98 unsigned getRegisterBitWidth(bool Vector) const {
107 unsigned getMinVectorRegisterBitWidth() {
108 return ST->getMinVectorRegisterBitWidth();
111 unsigned getMaxInterleaveFactor(unsigned VF);
113 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
114 const Instruction *I = nullptr);
116 int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
119 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
121 int getArithmeticInstrCost(
122 unsigned Opcode, Type *Ty,
123 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
124 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
125 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
126 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
127 ArrayRef<const Value *> Args = ArrayRef<const Value *>());
129 int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
131 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
132 const Instruction *I = nullptr);
134 int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
135 unsigned AddressSpace, const Instruction *I = nullptr);
137 int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
139 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
140 TTI::UnrollingPreferences &UP);
142 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
145 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
147 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
148 ArrayRef<unsigned> Indices, unsigned Alignment,
149 unsigned AddressSpace);
152 shouldConsiderAddressTypePromotion(const Instruction &I,
153 bool &AllowPromotionWithoutCommonHeader);
155 unsigned getCacheLineSize();
157 unsigned getPrefetchDistance();
159 unsigned getMinPrefetchStride();
161 unsigned getMaxPrefetchIterationsAhead();
163 bool shouldExpandReduction(const IntrinsicInst *II) const {
167 bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
168 TTI::ReductionFlags Flags) const;
172 } // end namespace llvm
174 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H