1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the functions necessary to decode AArch64 instruction
11 // bitpatterns into MCInsts (with the help of TableGenerated information from
12 // the instruction definitions).
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCDisassembler.h"
27 #include "llvm/MC/MCFixedLenDisassembler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MemoryObject.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
36 typedef MCDisassembler::DecodeStatus DecodeStatus;
39 /// AArch64 disassembler for all AArch64 platforms.
40 class AArch64Disassembler : public MCDisassembler {
41 const MCRegisterInfo *RegInfo;
43 /// Initializes the disassembler.
45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
46 : MCDisassembler(STI), RegInfo(Info) {
49 ~AArch64Disassembler() {
52 /// See MCDisassembler.
53 DecodeStatus getInstruction(MCInst &instr,
55 const MemoryObject ®ion,
58 raw_ostream &cStream) const;
60 const MCRegisterInfo *getRegInfo() const { return RegInfo; }
65 // Forward-declarations used in the auto-generated files.
66 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
67 uint64_t Address, const void *Decoder);
69 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
70 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
73 uint64_t Address, const void *Decoder);
75 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
76 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
79 uint64_t Address, const void *Decoder);
80 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
81 uint64_t Address, const void *Decoder);
82 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
83 uint64_t Address, const void *Decoder);
84 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
85 uint64_t Address, const void *Decoder);
86 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
87 unsigned RegNo, uint64_t Address,
89 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
90 unsigned RegNo, uint64_t Address,
93 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
99 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
102 const void *Decoder);
104 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
107 const void *Decoder);
109 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
112 const void *Decoder);
114 template<int RegWidth>
115 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
118 const void *Decoder);
120 template<int RegWidth>
121 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
124 const void *Decoder);
126 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
127 unsigned ShiftAmount,
129 const void *Decoder);
131 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
132 unsigned ShiftAmount,
134 const void *Decoder);
135 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
137 const void *Decoder);
139 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
141 const void *Decoder);
143 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
146 const void *Decoder);
148 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
151 const void *Decoder);
153 template<typename SomeNamedImmMapper>
154 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
157 const void *Decoder);
160 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
161 llvm::MCInst &Inst, unsigned Val,
162 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
167 const void *Decoder);
169 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
172 const void *Decoder);
175 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
178 const void *Decoder);
181 static bool Check(DecodeStatus &Out, DecodeStatus In);
183 #include "AArch64GenDisassemblerTables.inc"
184 #include "AArch64GenInstrInfo.inc"
186 static bool Check(DecodeStatus &Out, DecodeStatus In) {
188 case MCDisassembler::Success:
189 // Out stays the same.
191 case MCDisassembler::SoftFail:
194 case MCDisassembler::Fail:
198 llvm_unreachable("Invalid DecodeStatus!");
201 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
202 const MemoryObject &Region,
205 raw_ostream &cs) const {
210 // We want to read exactly 4 bytes of data.
211 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
213 return MCDisassembler::Fail;
216 // Encoded as a small-endian 32-bit word in the stream.
217 uint32_t insn = (bytes[3] << 24) |
222 // Calling the auto-generated decoder function.
223 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
225 if (result != MCDisassembler::Fail) {
232 return MCDisassembler::Fail;
235 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
236 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
237 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
240 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
241 uint64_t Address, const void *Decoder) {
243 return MCDisassembler::Fail;
245 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
246 Inst.addOperand(MCOperand::CreateReg(Register));
247 return MCDisassembler::Success;
251 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
252 uint64_t Address, const void *Decoder) {
254 return MCDisassembler::Fail;
256 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
257 Inst.addOperand(MCOperand::CreateReg(Register));
258 return MCDisassembler::Success;
261 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
263 const void *Decoder) {
265 return MCDisassembler::Fail;
267 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
268 Inst.addOperand(MCOperand::CreateReg(Register));
269 return MCDisassembler::Success;
273 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
274 uint64_t Address, const void *Decoder) {
276 return MCDisassembler::Fail;
278 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
279 Inst.addOperand(MCOperand::CreateReg(Register));
280 return MCDisassembler::Success;
284 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
285 uint64_t Address, const void *Decoder) {
287 return MCDisassembler::Fail;
289 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
290 Inst.addOperand(MCOperand::CreateReg(Register));
291 return MCDisassembler::Success;
295 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
296 uint64_t Address, const void *Decoder) {
298 return MCDisassembler::Fail;
300 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
301 Inst.addOperand(MCOperand::CreateReg(Register));
302 return MCDisassembler::Success;
307 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
308 uint64_t Address, const void *Decoder) {
310 return MCDisassembler::Fail;
312 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
313 Inst.addOperand(MCOperand::CreateReg(Register));
314 return MCDisassembler::Success;
318 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
319 uint64_t Address, const void *Decoder) {
321 return MCDisassembler::Fail;
323 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
324 Inst.addOperand(MCOperand::CreateReg(Register));
325 return MCDisassembler::Success;
330 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
331 uint64_t Address, const void *Decoder) {
333 return MCDisassembler::Fail;
335 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
336 Inst.addOperand(MCOperand::CreateReg(Register));
337 return MCDisassembler::Success;
341 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
342 uint64_t Address, const void *Decoder) {
344 return MCDisassembler::Fail;
346 uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
347 Inst.addOperand(MCOperand::CreateReg(Register));
348 return MCDisassembler::Success;
351 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
354 const void *Decoder) {
355 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
356 // S}. Hence we want to check bit 1.
357 if (!(OptionHiS & 2))
358 return MCDisassembler::Fail;
360 Inst.addOperand(MCOperand::CreateImm(OptionHiS));
361 return MCDisassembler::Success;
364 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
367 const void *Decoder) {
368 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
371 return MCDisassembler::Fail;
373 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
374 return MCDisassembler::Success;
377 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
380 const void *Decoder) {
381 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
383 return MCDisassembler::Fail;
385 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
386 return MCDisassembler::Success;
389 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
392 const void *Decoder) {
393 // Any bits are valid in the instruction (they're architecturally ignored),
394 // but a code generator should insert 0.
395 Inst.addOperand(MCOperand::CreateImm(0));
396 return MCDisassembler::Success;
401 template<int RegWidth>
402 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
405 const void *Decoder) {
406 unsigned Imm16 = FullImm & 0xffff;
407 unsigned Shift = FullImm >> 16;
409 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
411 Inst.addOperand(MCOperand::CreateImm(Imm16));
412 Inst.addOperand(MCOperand::CreateImm(Shift));
413 return MCDisassembler::Success;
416 template<int RegWidth>
417 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
420 const void *Decoder) {
422 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
423 return MCDisassembler::Fail;
425 Inst.addOperand(MCOperand::CreateImm(Bits));
426 return MCDisassembler::Success;
430 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
431 unsigned ShiftAmount,
433 const void *Decoder) {
434 // Only values 0-4 are valid for this 3-bit field
436 return MCDisassembler::Fail;
438 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
439 return MCDisassembler::Success;
442 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
443 unsigned ShiftAmount,
445 const void *Decoder) {
446 // Only values below 32 are valid for a 32-bit register
447 if (ShiftAmount > 31)
448 return MCDisassembler::Fail;
450 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
451 return MCDisassembler::Success;
454 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
456 const void *Decoder) {
457 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
458 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
459 unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
460 unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
461 unsigned SF = fieldFromInstruction(Insn, 31, 1);
463 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
464 // out assertions that it thinks should never be hit.
465 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
466 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
469 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
470 if (ImmR > 31 || ImmS > 31)
471 return MCDisassembler::Fail;
475 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
476 // BFM MCInsts use Rd as a source too.
477 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
478 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
480 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
481 // BFM MCInsts use Rd as a source too.
482 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
483 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
486 // ASR and LSR have more specific patterns so they won't get here:
487 assert(!(ImmS == 31 && !SF && Opc != BFM)
488 && "shift should have used auto decode");
489 assert(!(ImmS == 63 && SF && Opc != BFM)
490 && "shift should have used auto decode");
492 // Extension instructions similarly:
493 if (Opc == SBFM && ImmR == 0) {
494 assert((ImmS != 7 && ImmS != 15) && "extension got here");
495 assert((ImmS != 31 || SF == 0) && "extension got here");
496 } else if (Opc == UBFM && ImmR == 0) {
497 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
501 // It might be a LSL instruction, which actually takes the shift amount
502 // itself as an MCInst operand.
503 if (SF && (ImmS + 1) % 64 == ImmR) {
504 Inst.setOpcode(AArch64::LSLxxi);
505 Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
506 return MCDisassembler::Success;
507 } else if (!SF && (ImmS + 1) % 32 == ImmR) {
508 Inst.setOpcode(AArch64::LSLwwi);
509 Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
510 return MCDisassembler::Success;
514 // Otherwise it's definitely either an extract or an insert depending on which
515 // of ImmR or ImmS is larger.
516 unsigned ExtractOp, InsertOp;
518 default: llvm_unreachable("unexpected instruction trying to decode bitfield");
520 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
521 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
524 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
525 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
528 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
529 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
533 // Otherwise it's a boring insert or extract
534 Inst.addOperand(MCOperand::CreateImm(ImmR));
535 Inst.addOperand(MCOperand::CreateImm(ImmS));
539 Inst.setOpcode(InsertOp);
541 Inst.setOpcode(ExtractOp);
543 return MCDisassembler::Success;
546 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
548 const void *Decoder) {
549 // This decoder exists to add the dummy Lane operand to the MCInst, which must
550 // be 1 in assembly but has no other real manifestation.
551 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
552 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
553 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
556 DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
557 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
559 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
560 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
564 Inst.addOperand(MCOperand::CreateImm(1));
566 return MCDisassembler::Success;
570 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
573 const void *Decoder) {
574 DecodeStatus Result = MCDisassembler::Success;
575 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
576 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
577 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
578 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
579 unsigned L = fieldFromInstruction(Insn, 22, 1);
580 unsigned V = fieldFromInstruction(Insn, 26, 1);
581 unsigned Opc = fieldFromInstruction(Insn, 30, 2);
583 // Not an official name, but it turns out that bit 23 distinguishes indexed
584 // from non-indexed operations.
585 unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
587 if (Indexed && L == 0) {
588 // The MCInst for an indexed store has an out operand and 4 ins:
589 // Rn_wb, Rt, Rt2, Rn, Imm
590 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
593 // You shouldn't load to the same register twice in an instruction...
595 Result = MCDisassembler::SoftFail;
597 // ... or do any operation that writes-back to a transfer register. But note
598 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
599 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
600 Result = MCDisassembler::SoftFail;
602 // Exactly how we decode the MCInst's registers depends on the Opc and V
603 // fields of the instruction. These also obviously determine the size of the
604 // operation so we can fill in that information while we're at it.
606 // The instruction operates on the FP/SIMD registers
608 default: return MCDisassembler::Fail;
610 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
611 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
614 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
615 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
618 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
619 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
624 default: return MCDisassembler::Fail;
626 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
627 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
630 assert(L && "unexpected \"store signed\" attempt");
631 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
632 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
635 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
636 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
641 if (Indexed && L == 1) {
642 // The MCInst for an indexed load has 3 out operands and an 3 ins:
643 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
644 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
648 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
649 Inst.addOperand(MCOperand::CreateImm(SImm7));
654 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
657 const void *Decoder) {
658 unsigned Rt = fieldFromInstruction(Val, 0, 5);
659 unsigned Rn = fieldFromInstruction(Val, 5, 5);
660 unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
661 unsigned MemSize = fieldFromInstruction(Val, 30, 2);
663 DecodeStatus S = MCDisassembler::Success;
664 if (Rt == Rt2) S = MCDisassembler::SoftFail;
668 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
669 return MCDisassembler::Fail;
670 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
671 return MCDisassembler::Fail;
674 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
675 return MCDisassembler::Fail;
676 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
677 return MCDisassembler::Fail;
680 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
683 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
684 return MCDisassembler::Fail;
689 template<typename SomeNamedImmMapper>
690 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
693 const void *Decoder) {
694 SomeNamedImmMapper Mapper;
696 Mapper.toString(Val, ValidNamed);
697 if (ValidNamed || Mapper.validImm(Val)) {
698 Inst.addOperand(MCOperand::CreateImm(Val));
699 return MCDisassembler::Success;
702 return MCDisassembler::Fail;
705 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
709 const void *Decoder) {
711 Mapper.toString(Val, ValidNamed);
713 Inst.addOperand(MCOperand::CreateImm(Val));
715 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
718 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
721 const void *Decoder) {
722 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
726 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
729 const void *Decoder) {
730 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
734 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
737 const void *Decoder) {
738 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
739 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
740 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
742 unsigned Opc = fieldFromInstruction(Insn, 22, 2);
743 unsigned V = fieldFromInstruction(Insn, 26, 1);
744 unsigned Size = fieldFromInstruction(Insn, 30, 2);
746 if (Opc == 0 || (V == 1 && Opc == 2)) {
747 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
748 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
751 if (V == 0 && (Opc == 2 || Size == 3)) {
752 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
754 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
755 } else if (V == 1 && (Opc & 2)) {
756 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
760 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
763 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
766 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
769 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
774 if (Opc != 0 && (V != 1 || Opc != 2)) {
775 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
776 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
779 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
781 Inst.addOperand(MCOperand::CreateImm(Imm9));
783 // N.b. The official documentation says undpredictable if Rt == Rn, but this
784 // takes place at the architectural rather than encoding level:
786 // "STR xzr, [sp], #4" is perfectly valid.
787 if (V == 0 && Rt == Rn && Rn != 31)
788 return MCDisassembler::SoftFail;
790 return MCDisassembler::Success;
793 static MCDisassembler *createAArch64Disassembler(const Target &T,
794 const MCSubtargetInfo &STI) {
795 return new AArch64Disassembler(STI, T.createMCRegInfo(""));
798 extern "C" void LLVMInitializeAArch64Disassembler() {
799 TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
800 createAArch64Disassembler);