1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "AArch64RegisterInfo.h"
12 #include "MCTargetDesc/AArch64FixupKinds.h"
13 #include "llvm/ADT/Triple.h"
14 #include "llvm/BinaryFormat/MachO.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDirectives.h"
19 #include "llvm/MC/MCELFObjectWriter.h"
20 #include "llvm/MC/MCFixupKindInfo.h"
21 #include "llvm/MC/MCObjectWriter.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/MC/MCValue.h"
25 #include "llvm/Support/ErrorHandling.h"
30 class AArch64AsmBackend : public MCAsmBackend {
31 static const unsigned PCRelFlagVal =
32 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
36 AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
37 : MCAsmBackend(IsLittleEndian ? support::little : support::big),
40 unsigned getNumFixupKinds() const override {
41 return AArch64::NumTargetFixupKinds;
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
45 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
46 // This table *must* be in the order that the fixup_* kinds are defined
47 // in AArch64FixupKinds.h.
49 // Name Offset (bits) Size (bits) Flags
50 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
51 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
52 {"fixup_aarch64_add_imm12", 10, 12, 0},
53 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
54 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
55 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
56 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
57 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
58 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
59 {"fixup_aarch64_movw", 5, 16, 0},
60 {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
61 {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
62 {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
63 {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal},
64 {"fixup_aarch64_tlsdesc_call", 0, 0, 0}};
66 if (Kind < FirstTargetFixupKind)
67 return MCAsmBackend::getFixupKindInfo(Kind);
69 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
71 return Infos[Kind - FirstTargetFixupKind];
74 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
75 const MCValue &Target, MutableArrayRef<char> Data,
76 uint64_t Value, bool IsResolved,
77 const MCSubtargetInfo *STI) const override;
79 bool mayNeedRelaxation(const MCInst &Inst,
80 const MCSubtargetInfo &STI) const override;
81 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
82 const MCRelaxableFragment *DF,
83 const MCAsmLayout &Layout) const override;
84 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
85 MCInst &Res) const override;
86 bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
88 void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
90 unsigned getPointerSize() const { return 8; }
92 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
94 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
95 const MCValue &Target) override;
98 } // end anonymous namespace
100 /// The number of bytes the fixup may change.
101 static unsigned getFixupKindNumBytes(unsigned Kind) {
104 llvm_unreachable("Unknown fixup kind!");
106 case AArch64::fixup_aarch64_tlsdesc_call:
112 case AArch64::fixup_aarch64_movw:
117 case AArch64::fixup_aarch64_pcrel_branch14:
118 case AArch64::fixup_aarch64_add_imm12:
119 case AArch64::fixup_aarch64_ldst_imm12_scale1:
120 case AArch64::fixup_aarch64_ldst_imm12_scale2:
121 case AArch64::fixup_aarch64_ldst_imm12_scale4:
122 case AArch64::fixup_aarch64_ldst_imm12_scale8:
123 case AArch64::fixup_aarch64_ldst_imm12_scale16:
124 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
125 case AArch64::fixup_aarch64_pcrel_branch19:
128 case AArch64::fixup_aarch64_pcrel_adr_imm21:
129 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
130 case AArch64::fixup_aarch64_pcrel_branch26:
131 case AArch64::fixup_aarch64_pcrel_call26:
141 static unsigned AdrImmBits(unsigned Value) {
142 unsigned lo2 = Value & 0x3;
143 unsigned hi19 = (Value & 0x1ffffc) >> 2;
144 return (hi19 << 5) | (lo2 << 29);
147 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
148 MCContext &Ctx, const Triple &TheTriple,
150 unsigned Kind = Fixup.getKind();
151 int64_t SignedValue = static_cast<int64_t>(Value);
154 llvm_unreachable("Unknown fixup kind!");
155 case AArch64::fixup_aarch64_pcrel_adr_imm21:
156 if (SignedValue > 2097151 || SignedValue < -2097152)
157 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
158 return AdrImmBits(Value & 0x1fffffULL);
159 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
161 if (TheTriple.isOSBinFormatCOFF())
162 return AdrImmBits(Value & 0x1fffffULL);
163 return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
164 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
165 case AArch64::fixup_aarch64_pcrel_branch19:
166 // Signed 21-bit immediate
167 if (SignedValue > 2097151 || SignedValue < -2097152)
168 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
170 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
171 // Low two bits are not encoded.
172 return (Value >> 2) & 0x7ffff;
173 case AArch64::fixup_aarch64_add_imm12:
174 case AArch64::fixup_aarch64_ldst_imm12_scale1:
175 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
177 // Unsigned 12-bit immediate
179 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
181 case AArch64::fixup_aarch64_ldst_imm12_scale2:
182 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
184 // Unsigned 12-bit immediate which gets multiplied by 2
186 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
188 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
190 case AArch64::fixup_aarch64_ldst_imm12_scale4:
191 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
193 // Unsigned 12-bit immediate which gets multiplied by 4
195 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
197 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
199 case AArch64::fixup_aarch64_ldst_imm12_scale8:
200 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
202 // Unsigned 12-bit immediate which gets multiplied by 8
204 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
206 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
208 case AArch64::fixup_aarch64_ldst_imm12_scale16:
209 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
211 // Unsigned 12-bit immediate which gets multiplied by 16
212 if (Value >= 0x10000)
213 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
215 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
217 case AArch64::fixup_aarch64_movw:
218 Ctx.reportError(Fixup.getLoc(),
219 "no resolvable MOVZ/MOVK fixups supported yet");
221 case AArch64::fixup_aarch64_pcrel_branch14:
222 // Signed 16-bit immediate
223 if (SignedValue > 32767 || SignedValue < -32768)
224 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
225 // Low two bits are not encoded (4-byte alignment assumed).
227 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
228 return (Value >> 2) & 0x3fff;
229 case AArch64::fixup_aarch64_pcrel_branch26:
230 case AArch64::fixup_aarch64_pcrel_call26:
231 // Signed 28-bit immediate
232 if (SignedValue > 134217727 || SignedValue < -134217728)
233 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
234 // Low two bits are not encoded (4-byte alignment assumed).
236 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
237 return (Value >> 2) & 0x3ffffff;
248 /// getFixupKindContainereSizeInBytes - The number of bytes of the
249 /// container involved in big endian or 0 if the item is little endian
250 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
251 if (Endian == support::little)
256 llvm_unreachable("Unknown fixup kind!");
267 case AArch64::fixup_aarch64_tlsdesc_call:
268 case AArch64::fixup_aarch64_movw:
269 case AArch64::fixup_aarch64_pcrel_branch14:
270 case AArch64::fixup_aarch64_add_imm12:
271 case AArch64::fixup_aarch64_ldst_imm12_scale1:
272 case AArch64::fixup_aarch64_ldst_imm12_scale2:
273 case AArch64::fixup_aarch64_ldst_imm12_scale4:
274 case AArch64::fixup_aarch64_ldst_imm12_scale8:
275 case AArch64::fixup_aarch64_ldst_imm12_scale16:
276 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
277 case AArch64::fixup_aarch64_pcrel_branch19:
278 case AArch64::fixup_aarch64_pcrel_adr_imm21:
279 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
280 case AArch64::fixup_aarch64_pcrel_branch26:
281 case AArch64::fixup_aarch64_pcrel_call26:
282 // Instructions are always little endian
287 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
288 const MCValue &Target,
289 MutableArrayRef<char> Data, uint64_t Value,
291 const MCSubtargetInfo *STI) const {
292 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
294 return; // Doesn't change encoding.
295 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
296 MCContext &Ctx = Asm.getContext();
297 // Apply any target-specific value adjustments.
298 Value = adjustFixupValue(Fixup, Value, Ctx, TheTriple, IsResolved);
300 // Shift the value into position.
301 Value <<= Info.TargetOffset;
303 unsigned Offset = Fixup.getOffset();
304 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
306 // Used to point to big endian bytes.
307 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());
309 // For each byte of the fragment that the fixup touches, mask in the
310 // bits from the fixup value.
311 if (FulleSizeInBytes == 0) {
312 // Handle as little-endian
313 for (unsigned i = 0; i != NumBytes; ++i) {
314 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
317 // Handle as big-endian
318 assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!");
319 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");
320 for (unsigned i = 0; i != NumBytes; ++i) {
321 unsigned Idx = FulleSizeInBytes - 1 - i;
322 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
327 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst,
328 const MCSubtargetInfo &STI) const {
332 bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
334 const MCRelaxableFragment *DF,
335 const MCAsmLayout &Layout) const {
336 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic
337 // into the targets for now.
339 // Relax if the value is too big for a (signed) i8.
340 return int64_t(Value) != int64_t(int8_t(Value));
343 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
344 const MCSubtargetInfo &STI,
346 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
349 bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
350 // If the count is not 4-byte aligned, we must be writing data into the text
351 // section (otherwise we have unaligned instructions, and thus have far
352 // bigger problems), so just write zeros instead.
353 OS.write_zeros(Count % 4);
355 // We are properly aligned, so write NOPs as requested.
357 for (uint64_t i = 0; i != Count; ++i)
358 support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
362 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
363 const MCFixup &Fixup,
364 const MCValue &Target) {
365 // The ADRP instruction adds some multiple of 0x1000 to the current PC &
366 // ~0xfff. This means that the required offset to reach a symbol can vary by
367 // up to one step depending on where the ADRP is in memory. For example:
372 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
373 // we'll need that as an offset. At any other address "there" will be in the
374 // same page as the ADRP and the instruction should encode 0x0. Assuming the
375 // section isn't 0x1000-aligned, we therefore need to delegate this decision
376 // to the linker -- a relocation!
377 if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
386 /// Compact unwind encoding values.
387 enum CompactUnwindEncodings {
388 /// A "frameless" leaf function, where no non-volatile registers are
389 /// saved. The return remains in LR throughout the function.
390 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
392 /// No compact unwind encoding available. Instead the low 23-bits of
393 /// the compact unwind encoding is the offset of the DWARF FDE in the
394 /// __eh_frame section. This mode is never used in object files. It is only
395 /// generated by the linker in final linked images, which have only DWARF info
397 UNWIND_ARM64_MODE_DWARF = 0x03000000,
399 /// This is a standard arm64 prologue where FP/LR are immediately
400 /// pushed on the stack, then SP is copied to FP. If there are any
401 /// non-volatile register saved, they are copied into the stack fame in pairs
402 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
403 /// five X pairs and four D pairs can be saved, but the memory layout must be
404 /// in register number order.
405 UNWIND_ARM64_MODE_FRAME = 0x04000000,
407 /// Frame register pair encodings.
408 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
409 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
410 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
411 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
412 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
413 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
414 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
415 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
416 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
419 } // end CU namespace
421 // FIXME: This should be in a separate file.
422 class DarwinAArch64AsmBackend : public AArch64AsmBackend {
423 const MCRegisterInfo &MRI;
425 /// Encode compact unwind stack adjustment for frameless functions.
426 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
427 /// The stack size always needs to be 16 byte aligned.
428 uint32_t encodeStackAdjustment(uint32_t StackSize) const {
429 return (StackSize / 16) << 12;
433 DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
434 const MCRegisterInfo &MRI)
435 : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {}
437 std::unique_ptr<MCObjectTargetWriter>
438 createObjectTargetWriter() const override {
439 return createAArch64MachObjectWriter(MachO::CPU_TYPE_ARM64,
440 MachO::CPU_SUBTYPE_ARM64_ALL);
443 /// Generate the compact unwind encoding from the CFI directives.
444 uint32_t generateCompactUnwindEncoding(
445 ArrayRef<MCCFIInstruction> Instrs) const override {
447 return CU::UNWIND_ARM64_MODE_FRAMELESS;
450 unsigned StackSize = 0;
452 uint32_t CompactUnwindEncoding = 0;
453 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
454 const MCCFIInstruction &Inst = Instrs[i];
456 switch (Inst.getOperation()) {
458 // Cannot handle this directive: bail out.
459 return CU::UNWIND_ARM64_MODE_DWARF;
460 case MCCFIInstruction::OpDefCfa: {
461 // Defines a frame pointer.
463 getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true));
465 // Other CFA registers than FP are not supported by compact unwind.
466 // Fallback on DWARF.
467 // FIXME: When opt-remarks are supported in MC, add a remark to notify
469 if (XReg != AArch64::FP)
470 return CU::UNWIND_ARM64_MODE_DWARF;
472 assert(XReg == AArch64::FP && "Invalid frame pointer!");
473 assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
475 const MCCFIInstruction &LRPush = Instrs[++i];
476 assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
477 "Link register not pushed!");
478 const MCCFIInstruction &FPPush = Instrs[++i];
479 assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
480 "Frame pointer not pushed!");
482 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
483 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
485 LRReg = getXRegFromWReg(LRReg);
486 FPReg = getXRegFromWReg(FPReg);
488 assert(LRReg == AArch64::LR && FPReg == AArch64::FP &&
489 "Pushing invalid registers for frame!");
491 // Indicate that the function has a frame.
492 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
496 case MCCFIInstruction::OpDefCfaOffset: {
497 assert(StackSize == 0 && "We already have the CFA offset!");
498 StackSize = std::abs(Inst.getOffset());
501 case MCCFIInstruction::OpOffset: {
502 // Registers are saved in pairs. We expect there to be two consecutive
503 // `.cfi_offset' instructions with the appropriate registers specified.
504 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
506 return CU::UNWIND_ARM64_MODE_DWARF;
508 const MCCFIInstruction &Inst2 = Instrs[++i];
509 if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
510 return CU::UNWIND_ARM64_MODE_DWARF;
511 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
513 // N.B. The encodings must be in register number order, and the X
514 // registers before the D registers.
516 // X19/X20 pair = 0x00000001,
517 // X21/X22 pair = 0x00000002,
518 // X23/X24 pair = 0x00000004,
519 // X25/X26 pair = 0x00000008,
520 // X27/X28 pair = 0x00000010
521 Reg1 = getXRegFromWReg(Reg1);
522 Reg2 = getXRegFromWReg(Reg2);
524 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
525 (CompactUnwindEncoding & 0xF1E) == 0)
526 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
527 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
528 (CompactUnwindEncoding & 0xF1C) == 0)
529 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
530 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
531 (CompactUnwindEncoding & 0xF18) == 0)
532 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
533 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
534 (CompactUnwindEncoding & 0xF10) == 0)
535 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
536 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
537 (CompactUnwindEncoding & 0xF00) == 0)
538 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
540 Reg1 = getDRegFromBReg(Reg1);
541 Reg2 = getDRegFromBReg(Reg2);
543 // D8/D9 pair = 0x00000100,
544 // D10/D11 pair = 0x00000200,
545 // D12/D13 pair = 0x00000400,
546 // D14/D15 pair = 0x00000800
547 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
548 (CompactUnwindEncoding & 0xE00) == 0)
549 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
550 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
551 (CompactUnwindEncoding & 0xC00) == 0)
552 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
553 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
554 (CompactUnwindEncoding & 0x800) == 0)
555 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
556 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
557 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
559 // A pair was pushed which we cannot handle.
560 return CU::UNWIND_ARM64_MODE_DWARF;
569 // With compact unwind info we can only represent stack adjustments of up
571 if (StackSize > 65520)
572 return CU::UNWIND_ARM64_MODE_DWARF;
574 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
575 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
578 return CompactUnwindEncoding;
582 } // end anonymous namespace
586 class ELFAArch64AsmBackend : public AArch64AsmBackend {
591 ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
592 bool IsLittleEndian, bool IsILP32)
593 : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),
596 std::unique_ptr<MCObjectTargetWriter>
597 createObjectTargetWriter() const override {
598 return createAArch64ELFObjectWriter(OSABI, IsILP32);
605 class COFFAArch64AsmBackend : public AArch64AsmBackend {
607 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)
608 : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {}
610 std::unique_ptr<MCObjectTargetWriter>
611 createObjectTargetWriter() const override {
612 return createAArch64WinCOFFObjectWriter();
617 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
618 const MCSubtargetInfo &STI,
619 const MCRegisterInfo &MRI,
620 const MCTargetOptions &Options) {
621 const Triple &TheTriple = STI.getTargetTriple();
622 if (TheTriple.isOSBinFormatMachO())
623 return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
625 if (TheTriple.isOSBinFormatCOFF())
626 return new COFFAArch64AsmBackend(T, TheTriple);
628 assert(TheTriple.isOSBinFormatELF() && "Invalid target");
630 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
631 bool IsILP32 = Options.getABIName() == "ilp32";
632 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,
636 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
637 const MCSubtargetInfo &STI,
638 const MCRegisterInfo &MRI,
639 const MCTargetOptions &Options) {
640 const Triple &TheTriple = STI.getTargetTriple();
641 assert(TheTriple.isOSBinFormatELF() &&
642 "Big endian is only supported for ELF targets!");
643 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
644 bool IsILP32 = Options.getABIName() == "ilp32";
645 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,