contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

   1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides AArch64 specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18
  19 namespace llvm {
  20 class formatted_raw_ostream;
  21 class MCAsmBackend;
  22 class MCCodeEmitter;
  23 class MCContext;
  24 class MCInstrInfo;
  25 class MCInstPrinter;
  26 class MCRegisterInfo;
  27 class MCObjectWriter;
  28 class MCStreamer;
  29 class MCSubtargetInfo;
  30 class MCTargetOptions;
  31 class MCTargetStreamer;
  32 class StringRef;
  33 class Target;
  34 class Triple;
  35 class raw_ostream;
  36 class raw_pwrite_stream;
  37
  38 Target &getTheAArch64leTarget();
  39 Target &getTheAArch64beTarget();
  40 Target &getTheARM64Target();
  41
  42 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
  43                                           const MCRegisterInfo &MRI,
  44                                           MCContext &Ctx);
  45 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
  46                                         const MCRegisterInfo &MRI,
  47                                         const Triple &TT, StringRef CPU,
  48                                         const MCTargetOptions &Options);
  49 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
  50                                         const MCRegisterInfo &MRI,
  51                                         const Triple &TT, StringRef CPU,
  52                                         const MCTargetOptions &Options);
  53
  54 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
  55                                              uint8_t OSABI,
  56                                              bool IsLittleEndian,
  57                                              bool IsILP32);
  58
  59 MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,
  60                                               uint32_t CPUType,
  61                                               uint32_t CPUSubtype);
  62
  63 MCObjectWriter *createAArch64WinCOFFObjectWriter(raw_pwrite_stream &OS);
  64
  65 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
  66                                                  formatted_raw_ostream &OS,
  67                                                  MCInstPrinter *InstPrint,
  68                                                  bool isVerboseAsm);
  69
  70 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
  71                                                     const MCSubtargetInfo &STI);
  72
  73 } // End llvm namespace
  74
  75 // Defines symbolic names for AArch64 registers.  This defines a mapping from
  76 // register name to register number.
  77 //
  78 #define GET_REGINFO_ENUM
  79 #include "AArch64GenRegisterInfo.inc"
  80
  81 // Defines symbolic names for the AArch64 instructions.
  82 //
  83 #define GET_INSTRINFO_ENUM
  84 #include "AArch64GenInstrInfo.inc"
  85
  86 #define GET_SUBTARGETINFO_ENUM
  87 #include "AArch64GenSubtargetInfo.inc"
  88
  89 #endif