1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides basic encoding and assembly information for AArch64.
12 //===----------------------------------------------------------------------===//
13 #include "AArch64BaseInfo.h"
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/Support/Regex.h"
24 #include "AArch64GenSystemOperands.inc"
32 #include "AArch64GenSystemOperands.inc"
39 #include "AArch64GenSystemOperands.inc"
46 #include "AArch64GenSystemOperands.inc"
51 namespace AArch64ISB {
53 #include "AArch64GenSystemOperands.inc"
58 namespace AArch64TSB {
60 #include "AArch64GenSystemOperands.inc"
65 namespace AArch64PRFM {
67 #include "AArch64GenSystemOperands.inc"
72 namespace AArch64SVEPRFM {
73 #define GET_SVEPRFM_IMPL
74 #include "AArch64GenSystemOperands.inc"
79 namespace AArch64SVEPredPattern {
80 #define GET_SVEPREDPAT_IMPL
81 #include "AArch64GenSystemOperands.inc"
86 namespace AArch64ExactFPImm {
87 #define GET_EXACTFPIMM_IMPL
88 #include "AArch64GenSystemOperands.inc"
93 namespace AArch64PState {
94 #define GET_PSTATE_IMPL
95 #include "AArch64GenSystemOperands.inc"
100 namespace AArch64PSBHint {
102 #include "AArch64GenSystemOperands.inc"
107 namespace AArch64SysReg {
108 #define GET_SYSREG_IMPL
109 #include "AArch64GenSystemOperands.inc"
113 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
114 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
115 Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
117 std::string UpperName = Name.upper();
118 SmallVector<StringRef, 5> Ops;
119 if (!GenericRegPattern.match(UpperName, &Ops))
122 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
124 Ops[1].getAsInteger(10, Op0);
125 Ops[2].getAsInteger(10, Op1);
126 Ops[3].getAsInteger(10, CRn);
127 Ops[4].getAsInteger(10, CRm);
128 Ops[5].getAsInteger(10, Op2);
129 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
134 std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
135 assert(Bits < 0x10000);
136 uint32_t Op0 = (Bits >> 14) & 0x3;
137 uint32_t Op1 = (Bits >> 11) & 0x7;
138 uint32_t CRn = (Bits >> 7) & 0xf;
139 uint32_t CRm = (Bits >> 3) & 0xf;
140 uint32_t Op2 = Bits & 0x7;
142 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
143 utostr(CRm) + "_" + utostr(Op2);
147 namespace AArch64TLBI {
148 #define GET_TLBI_IMPL
149 #include "AArch64GenSystemOperands.inc"