contrib/llvm/lib/Target/AMDGPU/AMDGPU.h

   1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 /// \file
   9 //===----------------------------------------------------------------------===//
  10
  11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  13
  14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  15 #include "llvm/Target/TargetMachine.h"
  16
  17 namespace llvm {
  18
  19 class AMDGPUTargetMachine;
  20 class FunctionPass;
  21 class GCNTargetMachine;
  22 class ModulePass;
  23 class Pass;
  24 class Target;
  25 class TargetMachine;
  26 class PassRegistry;
  27 class Module;
  28
  29 // R600 Passes
  30 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
  31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
  32 FunctionPass *createR600EmitClauseMarkers();
  33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
  34 FunctionPass *createR600Packetizer(TargetMachine &tm);
  35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
  36 FunctionPass *createAMDGPUCFGStructurizerPass();
  37
  38 // SI Passes
  39 FunctionPass *createSITypeRewriter();
  40 FunctionPass *createSIAnnotateControlFlowPass();
  41 FunctionPass *createSIFoldOperandsPass();
  42 FunctionPass *createSIPeepholeSDWAPass();
  43 FunctionPass *createSILowerI1CopiesPass();
  44 FunctionPass *createSIShrinkInstructionsPass();
  45 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
  46 FunctionPass *createSIWholeQuadModePass();
  47 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
  48 FunctionPass *createSIFixSGPRCopiesPass();
  49 FunctionPass *createSIDebuggerInsertNopsPass();
  50 FunctionPass *createSIInsertWaitsPass();
  51 FunctionPass *createSIInsertWaitcntsPass();
  52 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
  53 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
  54
  55 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
  56 extern char &AMDGPUMachineCFGStructurizerID;
  57
  58 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
  59 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
  60 extern char &AMDGPUAnnotateKernelFeaturesID;
  61
  62 ModulePass *createAMDGPULowerIntrinsicsPass(const TargetMachine *TM = nullptr);
  63 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
  64 extern char &AMDGPULowerIntrinsicsID;
  65
  66 void initializeSIFoldOperandsPass(PassRegistry &);
  67 extern char &SIFoldOperandsID;
  68
  69 void initializeSIPeepholeSDWAPass(PassRegistry &);
  70 extern char &SIPeepholeSDWAID;
  71
  72 void initializeSIShrinkInstructionsPass(PassRegistry&);
  73 extern char &SIShrinkInstructionsID;
  74
  75 void initializeSIFixSGPRCopiesPass(PassRegistry &);
  76 extern char &SIFixSGPRCopiesID;
  77
  78 void initializeSIFixVGPRCopiesPass(PassRegistry &);
  79 extern char &SIFixVGPRCopiesID;
  80
  81 void initializeSILowerI1CopiesPass(PassRegistry &);
  82 extern char &SILowerI1CopiesID;
  83
  84 void initializeSILoadStoreOptimizerPass(PassRegistry &);
  85 extern char &SILoadStoreOptimizerID;
  86
  87 void initializeSIWholeQuadModePass(PassRegistry &);
  88 extern char &SIWholeQuadModeID;
  89
  90 void initializeSILowerControlFlowPass(PassRegistry &);
  91 extern char &SILowerControlFlowID;
  92
  93 void initializeSIInsertSkipsPass(PassRegistry &);
  94 extern char &SIInsertSkipsPassID;
  95
  96 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
  97 extern char &SIOptimizeExecMaskingID;
  98
  99 // Passes common to R600 and SI
 100 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
 101 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
 102 extern char &AMDGPUPromoteAllocaID;
 103
 104 Pass *createAMDGPUStructurizeCFGPass();
 105 FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
 106                                   CodeGenOpt::Level OptLevel);
 107 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 108 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
 109 FunctionPass *createAMDGPUAnnotateUniformValues();
 110
 111 ModulePass* createAMDGPUUnifyMetadataPass();
 112 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 113 extern char &AMDGPUUnifyMetadataID;
 114
 115 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
 116 extern char &SIFixControlFlowLiveIntervalsID;
 117
 118 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 119 extern char &AMDGPUAnnotateUniformValuesPassID;
 120
 121 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 122 extern char &AMDGPUCodeGenPrepareID;
 123
 124 void initializeSIAnnotateControlFlowPass(PassRegistry&);
 125 extern char &SIAnnotateControlFlowPassID;
 126
 127 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
 128 extern char &SIDebuggerInsertNopsID;
 129
 130 void initializeSIInsertWaitsPass(PassRegistry&);
 131 extern char &SIInsertWaitsID;
 132
 133 void initializeSIInsertWaitcntsPass(PassRegistry&);
 134 extern char &SIInsertWaitcntsID;
 135
 136 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
 137 extern char &AMDGPUUnifyDivergentExitNodesID;
 138
 139 ImmutablePass *createAMDGPUAAWrapperPass();
 140 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
 141
 142 Target &getTheAMDGPUTarget();
 143 Target &getTheGCNTarget();
 144
 145 namespace AMDGPU {
 146 enum TargetIndex {
 147   TI_CONSTDATA_START,
 148   TI_SCRATCH_RSRC_DWORD0,
 149   TI_SCRATCH_RSRC_DWORD1,
 150   TI_SCRATCH_RSRC_DWORD2,
 151   TI_SCRATCH_RSRC_DWORD3
 152 };
 153 }
 154
 155 } // End namespace llvm
 156
 157 /// OpenCL uses address spaces to differentiate between
 158 /// various memory regions on the hardware. On the CPU
 159 /// all of the address spaces point to the same memory,
 160 /// however on the GPU, each address space points to
 161 /// a separate piece of memory that is unique from other
 162 /// memory locations.
 163 struct AMDGPUAS {
 164   // The following address space values depend on the triple environment.
 165   unsigned PRIVATE_ADDRESS;  ///< Address space for private memory.
 166   unsigned FLAT_ADDRESS;     ///< Address space for flat memory.
 167   unsigned REGION_ADDRESS;   ///< Address space for region memory.
 168
 169   // The maximum value for flat, generic, local, private, constant and region.
 170   const static unsigned MAX_COMMON_ADDRESS = 5;
 171
 172   const static unsigned GLOBAL_ADDRESS   = 1;  ///< Address space for global memory (RAT0, VTX0).
 173   const static unsigned CONSTANT_ADDRESS = 2;  ///< Address space for constant memory (VTX2)
 174   const static unsigned LOCAL_ADDRESS    = 3;  ///< Address space for local memory.
 175   const static unsigned PARAM_D_ADDRESS  = 6;  ///< Address space for direct addressible parameter memory (CONST0)
 176   const static unsigned PARAM_I_ADDRESS  = 7;  ///< Address space for indirect addressible parameter memory (VTX1)
 177
 178   // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on this
 179   // order to be able to dynamically index a constant buffer, for example:
 180   //
 181   // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
 182
 183   const static unsigned CONSTANT_BUFFER_0 = 8;
 184   const static unsigned CONSTANT_BUFFER_1 = 9;
 185   const static unsigned CONSTANT_BUFFER_2 = 10;
 186   const static unsigned CONSTANT_BUFFER_3 = 11;
 187   const static unsigned CONSTANT_BUFFER_4 = 12;
 188   const static unsigned CONSTANT_BUFFER_5 = 13;
 189   const static unsigned CONSTANT_BUFFER_6 = 14;
 190   const static unsigned CONSTANT_BUFFER_7 = 15;
 191   const static unsigned CONSTANT_BUFFER_8 = 16;
 192   const static unsigned CONSTANT_BUFFER_9 = 17;
 193   const static unsigned CONSTANT_BUFFER_10 = 18;
 194   const static unsigned CONSTANT_BUFFER_11 = 19;
 195   const static unsigned CONSTANT_BUFFER_12 = 20;
 196   const static unsigned CONSTANT_BUFFER_13 = 21;
 197   const static unsigned CONSTANT_BUFFER_14 = 22;
 198   const static unsigned CONSTANT_BUFFER_15 = 23;
 199
 200   // Some places use this if the address space can't be determined.
 201   const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
 202 };
 203
 204 namespace llvm {
 205 namespace AMDGPU {
 206 AMDGPUAS getAMDGPUAS(const Module &M);
 207 AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
 208 AMDGPUAS getAMDGPUAS(Triple T);
 209 } // namespace AMDGPU
 210 } // namespace llvm
 211
 212 #endif