contrib/llvm/lib/Target/AMDGPU/AMDGPU.h

   1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 /// \file
   9 //===----------------------------------------------------------------------===//
  10
  11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  13
  14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  15 #include "llvm/Target/TargetMachine.h"
  16
  17 namespace llvm {
  18
  19 class AMDGPUTargetMachine;
  20 class FunctionPass;
  21 class GCNTargetMachine;
  22 class ModulePass;
  23 class Pass;
  24 class Target;
  25 class TargetMachine;
  26 class PassRegistry;
  27 class Module;
  28
  29 // R600 Passes
  30 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
  31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
  32 FunctionPass *createR600EmitClauseMarkers();
  33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
  34 FunctionPass *createR600Packetizer(TargetMachine &tm);
  35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
  36 FunctionPass *createAMDGPUCFGStructurizerPass();
  37
  38 // SI Passes
  39 FunctionPass *createSITypeRewriter();
  40 FunctionPass *createSIAnnotateControlFlowPass();
  41 FunctionPass *createSIFoldOperandsPass();
  42 FunctionPass *createSIPeepholeSDWAPass();
  43 FunctionPass *createSILowerI1CopiesPass();
  44 FunctionPass *createSIShrinkInstructionsPass();
  45 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
  46 FunctionPass *createSIWholeQuadModePass();
  47 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
  48 FunctionPass *createSIFixSGPRCopiesPass();
  49 FunctionPass *createSIDebuggerInsertNopsPass();
  50 FunctionPass *createSIInsertWaitsPass();
  51 FunctionPass *createSIInsertWaitcntsPass();
  52 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
  53
  54 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
  55 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
  56 extern char &AMDGPUAnnotateKernelFeaturesID;
  57
  58 ModulePass *createAMDGPULowerIntrinsicsPass(const TargetMachine *TM = nullptr);
  59 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
  60 extern char &AMDGPULowerIntrinsicsID;
  61
  62 void initializeSIFoldOperandsPass(PassRegistry &);
  63 extern char &SIFoldOperandsID;
  64
  65 void initializeSIPeepholeSDWAPass(PassRegistry &);
  66 extern char &SIPeepholeSDWAID;
  67
  68 void initializeSIShrinkInstructionsPass(PassRegistry&);
  69 extern char &SIShrinkInstructionsID;
  70
  71 void initializeSIFixSGPRCopiesPass(PassRegistry &);
  72 extern char &SIFixSGPRCopiesID;
  73
  74 void initializeSIFixVGPRCopiesPass(PassRegistry &);
  75 extern char &SIFixVGPRCopiesID;
  76
  77 void initializeSILowerI1CopiesPass(PassRegistry &);
  78 extern char &SILowerI1CopiesID;
  79
  80 void initializeSILoadStoreOptimizerPass(PassRegistry &);
  81 extern char &SILoadStoreOptimizerID;
  82
  83 void initializeSIWholeQuadModePass(PassRegistry &);
  84 extern char &SIWholeQuadModeID;
  85
  86 void initializeSILowerControlFlowPass(PassRegistry &);
  87 extern char &SILowerControlFlowID;
  88
  89 void initializeSIInsertSkipsPass(PassRegistry &);
  90 extern char &SIInsertSkipsPassID;
  91
  92 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
  93 extern char &SIOptimizeExecMaskingID;
  94
  95 // Passes common to R600 and SI
  96 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
  97 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
  98 extern char &AMDGPUPromoteAllocaID;
  99
 100 Pass *createAMDGPUStructurizeCFGPass();
 101 FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
 102                                   CodeGenOpt::Level OptLevel);
 103 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 104 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
 105 FunctionPass *createAMDGPUAnnotateUniformValues();
 106
 107 ModulePass* createAMDGPUUnifyMetadataPass();
 108 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 109 extern char &AMDGPUUnifyMetadataID;
 110
 111 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
 112 extern char &SIFixControlFlowLiveIntervalsID;
 113
 114 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 115 extern char &AMDGPUAnnotateUniformValuesPassID;
 116
 117 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 118 extern char &AMDGPUCodeGenPrepareID;
 119
 120 void initializeSIAnnotateControlFlowPass(PassRegistry&);
 121 extern char &SIAnnotateControlFlowPassID;
 122
 123 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
 124 extern char &SIDebuggerInsertNopsID;
 125
 126 void initializeSIInsertWaitsPass(PassRegistry&);
 127 extern char &SIInsertWaitsID;
 128
 129 void initializeSIInsertWaitcntsPass(PassRegistry&);
 130 extern char &SIInsertWaitcntsID;
 131
 132 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
 133 extern char &AMDGPUUnifyDivergentExitNodesID;
 134
 135 ImmutablePass *createAMDGPUAAWrapperPass();
 136 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
 137
 138 Target &getTheAMDGPUTarget();
 139 Target &getTheGCNTarget();
 140
 141 namespace AMDGPU {
 142 enum TargetIndex {
 143   TI_CONSTDATA_START,
 144   TI_SCRATCH_RSRC_DWORD0,
 145   TI_SCRATCH_RSRC_DWORD1,
 146   TI_SCRATCH_RSRC_DWORD2,
 147   TI_SCRATCH_RSRC_DWORD3
 148 };
 149 }
 150
 151 } // End namespace llvm
 152
 153 /// OpenCL uses address spaces to differentiate between
 154 /// various memory regions on the hardware. On the CPU
 155 /// all of the address spaces point to the same memory,
 156 /// however on the GPU, each address space points to
 157 /// a separate piece of memory that is unique from other
 158 /// memory locations.
 159 struct AMDGPUAS {
 160   // The following address space values depend on the triple environment.
 161   unsigned PRIVATE_ADDRESS;  ///< Address space for private memory.
 162   unsigned FLAT_ADDRESS;     ///< Address space for flat memory.
 163   unsigned REGION_ADDRESS;   ///< Address space for region memory.
 164
 165   // The maximum value for flat, generic, local, private, constant and region.
 166   const static unsigned MAX_COMMON_ADDRESS = 5;
 167
 168   const static unsigned GLOBAL_ADDRESS   = 1;  ///< Address space for global memory (RAT0, VTX0).
 169   const static unsigned CONSTANT_ADDRESS = 2;  ///< Address space for constant memory (VTX2)
 170   const static unsigned LOCAL_ADDRESS    = 3;  ///< Address space for local memory.
 171   const static unsigned PARAM_D_ADDRESS  = 6;  ///< Address space for direct addressible parameter memory (CONST0)
 172   const static unsigned PARAM_I_ADDRESS  = 7;  ///< Address space for indirect addressible parameter memory (VTX1)
 173
 174   // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on this
 175   // order to be able to dynamically index a constant buffer, for example:
 176   //
 177   // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
 178
 179   const static unsigned CONSTANT_BUFFER_0 = 8;
 180   const static unsigned CONSTANT_BUFFER_1 = 9;
 181   const static unsigned CONSTANT_BUFFER_2 = 10;
 182   const static unsigned CONSTANT_BUFFER_3 = 11;
 183   const static unsigned CONSTANT_BUFFER_4 = 12;
 184   const static unsigned CONSTANT_BUFFER_5 = 13;
 185   const static unsigned CONSTANT_BUFFER_6 = 14;
 186   const static unsigned CONSTANT_BUFFER_7 = 15;
 187   const static unsigned CONSTANT_BUFFER_8 = 16;
 188   const static unsigned CONSTANT_BUFFER_9 = 17;
 189   const static unsigned CONSTANT_BUFFER_10 = 18;
 190   const static unsigned CONSTANT_BUFFER_11 = 19;
 191   const static unsigned CONSTANT_BUFFER_12 = 20;
 192   const static unsigned CONSTANT_BUFFER_13 = 21;
 193   const static unsigned CONSTANT_BUFFER_14 = 22;
 194   const static unsigned CONSTANT_BUFFER_15 = 23;
 195
 196   // Some places use this if the address space can't be determined.
 197   const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
 198 };
 199
 200 namespace llvm {
 201 namespace AMDGPU {
 202 AMDGPUAS getAMDGPUAS(const Module &M);
 203 AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
 204 AMDGPUAS getAMDGPUAS(Triple T);
 205 } // namespace AMDGPU
 206 } // namespace llvm
 207
 208 #endif