1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
14 #include "llvm/Target/TargetMachine.h"
18 class AMDGPUTargetMachine;
20 class GCNTargetMachine;
28 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
29 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
30 FunctionPass *createR600EmitClauseMarkers();
31 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
32 FunctionPass *createR600Packetizer(TargetMachine &tm);
33 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
34 FunctionPass *createAMDGPUCFGStructurizerPass();
37 FunctionPass *createSITypeRewriter();
38 FunctionPass *createSIAnnotateControlFlowPass();
39 FunctionPass *createSIFoldOperandsPass();
40 FunctionPass *createSILowerI1CopiesPass();
41 FunctionPass *createSIShrinkInstructionsPass();
42 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
43 FunctionPass *createSIWholeQuadModePass();
44 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
45 FunctionPass *createSIFixSGPRCopiesPass();
46 FunctionPass *createSIDebuggerInsertNopsPass();
47 FunctionPass *createSIInsertWaitsPass();
48 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
50 ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
51 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
52 extern char &AMDGPUAnnotateKernelFeaturesID;
54 void initializeSIFoldOperandsPass(PassRegistry &);
55 extern char &SIFoldOperandsID;
57 void initializeSIShrinkInstructionsPass(PassRegistry&);
58 extern char &SIShrinkInstructionsID;
60 void initializeSIFixSGPRCopiesPass(PassRegistry &);
61 extern char &SIFixSGPRCopiesID;
63 void initializeSILowerI1CopiesPass(PassRegistry &);
64 extern char &SILowerI1CopiesID;
66 void initializeSILoadStoreOptimizerPass(PassRegistry &);
67 extern char &SILoadStoreOptimizerID;
69 void initializeSIWholeQuadModePass(PassRegistry &);
70 extern char &SIWholeQuadModeID;
72 void initializeSILowerControlFlowPass(PassRegistry &);
73 extern char &SILowerControlFlowID;
75 void initializeSIInsertSkipsPass(PassRegistry &);
76 extern char &SIInsertSkipsPassID;
78 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
79 extern char &SIOptimizeExecMaskingID;
81 // Passes common to R600 and SI
82 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
83 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
84 extern char &AMDGPUPromoteAllocaID;
86 Pass *createAMDGPUStructurizeCFGPass();
87 FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
88 CodeGenOpt::Level OptLevel);
89 ModulePass *createAMDGPUAlwaysInlinePass();
90 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
91 FunctionPass *createAMDGPUAnnotateUniformValues();
93 FunctionPass* createAMDGPUUnifyMetadataPass();
94 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
95 extern char &AMDGPUUnifyMetadataID;
97 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
98 extern char &SIFixControlFlowLiveIntervalsID;
100 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
101 extern char &AMDGPUAnnotateUniformValuesPassID;
103 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
104 extern char &AMDGPUCodeGenPrepareID;
106 void initializeSIAnnotateControlFlowPass(PassRegistry&);
107 extern char &SIAnnotateControlFlowPassID;
109 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
110 extern char &SIDebuggerInsertNopsID;
112 void initializeSIInsertWaitsPass(PassRegistry&);
113 extern char &SIInsertWaitsID;
115 Target &getTheAMDGPUTarget();
116 Target &getTheGCNTarget();
121 TI_SCRATCH_RSRC_DWORD0,
122 TI_SCRATCH_RSRC_DWORD1,
123 TI_SCRATCH_RSRC_DWORD2,
124 TI_SCRATCH_RSRC_DWORD3
128 } // End namespace llvm
130 /// OpenCL uses address spaces to differentiate between
131 /// various memory regions on the hardware. On the CPU
132 /// all of the address spaces point to the same memory,
133 /// however on the GPU, each address space points to
134 /// a separate piece of memory that is unique from other
135 /// memory locations.
137 enum AddressSpaces : unsigned {
138 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
139 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
140 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2)
141 LOCAL_ADDRESS = 3, ///< Address space for local memory.
142 FLAT_ADDRESS = 4, ///< Address space for flat memory.
143 REGION_ADDRESS = 5, ///< Address space for region memory.
144 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
145 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
147 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
148 // order to be able to dynamically index a constant buffer, for example:
150 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
152 CONSTANT_BUFFER_0 = 8,
153 CONSTANT_BUFFER_1 = 9,
154 CONSTANT_BUFFER_2 = 10,
155 CONSTANT_BUFFER_3 = 11,
156 CONSTANT_BUFFER_4 = 12,
157 CONSTANT_BUFFER_5 = 13,
158 CONSTANT_BUFFER_6 = 14,
159 CONSTANT_BUFFER_7 = 15,
160 CONSTANT_BUFFER_8 = 16,
161 CONSTANT_BUFFER_9 = 17,
162 CONSTANT_BUFFER_10 = 18,
163 CONSTANT_BUFFER_11 = 19,
164 CONSTANT_BUFFER_12 = 20,
165 CONSTANT_BUFFER_13 = 21,
166 CONSTANT_BUFFER_14 = 22,
167 CONSTANT_BUFFER_15 = 23,
169 // Some places use this if the address space can't be determined.
170 UNKNOWN_ADDRESS_SPACE = ~0u
173 } // namespace AMDGPUAS