contrib/llvm/lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===------------------------------------------------------------===//
   9
  10 include "llvm/TableGen/SearchableTable.td"
  11 include "llvm/Target/Target.td"
  12 include "AMDGPUFeatures.td"
  13
  14 //===------------------------------------------------------------===//
  15 // Subtarget Features (device properties)
  16 //===------------------------------------------------------------===//
  17
  18 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  19   "FastFMAF32",
  20   "true",
  21   "Assuming f32 fma is at least as fast as mul + add"
  22 >;
  23
  24 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  25   "MIMG_R128",
  26   "true",
  27   "Support 128-bit texture resources"
  28 >;
  29
  30 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  31   "HalfRate64Ops",
  32   "true",
  33   "Most fp64 instructions are half rate instead of quarter"
  34 >;
  35
  36 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  37   "FlatAddressSpace",
  38   "true",
  39   "Support flat address space"
  40 >;
  41
  42 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  43   "FlatInstOffsets",
  44   "true",
  45   "Flat instructions have immediate offset addressing mode"
  46 >;
  47
  48 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  49   "FlatGlobalInsts",
  50   "true",
  51   "Have global_* flat memory instructions"
  52 >;
  53
  54 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  55   "FlatScratchInsts",
  56   "true",
  57   "Have scratch_* flat memory instructions"
  58 >;
  59
  60 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  61   "AddNoCarryInsts",
  62   "true",
  63   "Have VALU add/sub instructions without carry out"
  64 >;
  65
  66 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  67   "UnalignedBufferAccess",
  68   "true",
  69   "Support unaligned global loads and stores"
  70 >;
  71
  72 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
  73   "TrapHandler",
  74   "true",
  75   "Trap handler support"
  76 >;
  77
  78 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
  79   "UnalignedScratchAccess",
  80   "true",
  81   "Support unaligned scratch loads and stores"
  82 >;
  83
  84 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
  85   "HasApertureRegs",
  86   "true",
  87   "Has Memory Aperture Base and Size Registers"
  88 >;
  89
  90 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
  91   "HasMadMixInsts",
  92   "true",
  93   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
  94 >;
  95
  96 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
  97   "HasFmaMixInsts",
  98   "true",
  99   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 100 >;
 101
 102 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 103 // XNACK. The current default kernel driver setting is:
 104 // - graphics ring: XNACK disabled
 105 // - compute ring: XNACK enabled
 106 //
 107 // If XNACK is enabled, the VMEM latency can be worse.
 108 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 109 def FeatureXNACK : SubtargetFeature<"xnack",
 110   "EnableXNACK",
 111   "true",
 112   "Enable XNACK support"
 113 >;
 114
 115 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 116   "SGPRInitBug",
 117   "true",
 118   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 119 >;
 120
 121 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 122   "ldsbankcount"#Value,
 123   "LDSBankCount",
 124   !cast<string>(Value),
 125   "The number of LDS banks per compute unit."
 126 >;
 127
 128 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 129 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 130
 131 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 132   "GCN3Encoding",
 133   "true",
 134   "Encoding format for VI"
 135 >;
 136
 137 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 138   "CIInsts",
 139   "true",
 140   "Additional instructions for CI+"
 141 >;
 142
 143 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 144   "GFX9Insts",
 145   "true",
 146   "Additional instructions for GFX9+"
 147 >;
 148
 149 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 150   "HasSMemRealTime",
 151   "true",
 152   "Has s_memrealtime instruction"
 153 >;
 154
 155 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 156   "HasInv2PiInlineImm",
 157   "true",
 158   "Has 1 / (2 * pi) as inline immediate"
 159 >;
 160
 161 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 162   "Has16BitInsts",
 163   "true",
 164   "Has i16/f16 instructions"
 165 >;
 166
 167 def FeatureVOP3P : SubtargetFeature<"vop3p",
 168   "HasVOP3PInsts",
 169   "true",
 170   "Has VOP3P packed instructions"
 171 >;
 172
 173 def FeatureMovrel : SubtargetFeature<"movrel",
 174   "HasMovrel",
 175   "true",
 176   "Has v_movrel*_b32 instructions"
 177 >;
 178
 179 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 180   "HasVGPRIndexMode",
 181   "true",
 182   "Has VGPR mode register indexing"
 183 >;
 184
 185 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 186   "HasScalarStores",
 187   "true",
 188   "Has store scalar memory instructions"
 189 >;
 190
 191 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 192   "HasScalarAtomics",
 193   "true",
 194   "Has atomic scalar memory instructions"
 195 >;
 196
 197 def FeatureSDWA : SubtargetFeature<"sdwa",
 198   "HasSDWA",
 199   "true",
 200   "Support SDWA (Sub-DWORD Addressing) extension"
 201 >;
 202
 203 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 204   "HasSDWAOmod",
 205   "true",
 206   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 207 >;
 208
 209 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 210   "HasSDWAScalar",
 211   "true",
 212   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 213 >;
 214
 215 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 216   "HasSDWASdst",
 217   "true",
 218   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 219 >;
 220
 221 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 222   "HasSDWAMac",
 223   "true",
 224   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 225 >;
 226
 227 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 228   "HasSDWAOutModsVOPC",
 229   "true",
 230   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 231 >;
 232
 233 def FeatureDPP : SubtargetFeature<"dpp",
 234   "HasDPP",
 235   "true",
 236   "Support DPP (Data Parallel Primitives) extension"
 237 >;
 238
 239 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 240   "HasIntClamp",
 241   "true",
 242   "Support clamp for integer destination"
 243 >;
 244
 245 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 246   "HasUnpackedD16VMem",
 247   "true",
 248   "Has unpacked d16 vmem instructions"
 249 >;
 250
 251 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 252   "HasDLInsts",
 253   "true",
 254   "Has deep learning instructions"
 255 >;
 256
 257 def FeatureD16PreservesUnusedBits : SubtargetFeature<
 258   "d16-preserves-unused-bits",
 259   "D16PreservesUnusedBits",
 260   "true",
 261   "If present, then instructions defined by HasD16LoadStore predicate preserve "
 262   "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
 263   "zero unused bits."
 264 >;
 265
 266 //===------------------------------------------------------------===//
 267 // Subtarget Features (options and debugging)
 268 //===------------------------------------------------------------===//
 269
 270 // Some instructions do not support denormals despite this flag. Using
 271 // fp32 denormals also causes instructions to run at the double
 272 // precision rate for the device.
 273 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
 274   "FP32Denormals",
 275   "true",
 276   "Enable single precision denormal handling"
 277 >;
 278
 279 // Denormal handling for fp64 and fp16 is controlled by the same
 280 // config register when fp16 supported.
 281 // TODO: Do we need a separate f16 setting when not legal?
 282 def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
 283   "FP64FP16Denormals",
 284   "true",
 285   "Enable double and half precision denormal handling",
 286   [FeatureFP64]
 287 >;
 288
 289 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
 290   "FP64FP16Denormals",
 291   "true",
 292   "Enable double and half precision denormal handling",
 293   [FeatureFP64, FeatureFP64FP16Denormals]
 294 >;
 295
 296 def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
 297   "FP64FP16Denormals",
 298   "true",
 299   "Enable half precision denormal handling",
 300   [FeatureFP64FP16Denormals]
 301 >;
 302
 303 def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
 304   "FPExceptions",
 305   "true",
 306   "Enable floating point exceptions"
 307 >;
 308
 309 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 310   "max-private-element-size-"#size,
 311   "MaxPrivateElementSize",
 312   !cast<string>(size),
 313   "Maximum private access size may be "#size
 314 >;
 315
 316 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 317 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 318 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 319
 320 def FeatureEnableHugePrivateBuffer : SubtargetFeature<
 321   "huge-private-buffer",
 322   "EnableHugePrivateBuffer",
 323   "true",
 324   "Enable private/scratch buffer sizes greater than 128 GB"
 325 >;
 326
 327 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 328   "EnableVGPRSpilling",
 329   "true",
 330   "Enable spilling of VGPRs to scratch memory"
 331 >;
 332
 333 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 334   "DumpCode",
 335   "true",
 336   "Dump MachineInstrs in the CodeEmitter"
 337 >;
 338
 339 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 340   "DumpCode",
 341   "true",
 342   "Dump MachineInstrs in the CodeEmitter"
 343 >;
 344
 345 // XXX - This should probably be removed once enabled by default
 346 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 347   "EnableLoadStoreOpt",
 348   "true",
 349   "Enable SI load/store optimizer pass"
 350 >;
 351
 352 // Performance debugging feature. Allow using DS instruction immediate
 353 // offsets even if the base pointer can't be proven to be base. On SI,
 354 // base pointer values that won't give the same result as a 16-bit add
 355 // are not safe to fold, but this will override the conservative test
 356 // for the base pointer.
 357 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 358   "unsafe-ds-offset-folding",
 359   "EnableUnsafeDSOffsetFolding",
 360   "true",
 361   "Force using DS instruction immediate offsets on SI"
 362 >;
 363
 364 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 365   "EnableSIScheduler",
 366   "true",
 367   "Enable SI Machine Scheduler"
 368 >;
 369
 370 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 371   "EnableDS128",
 372   "true",
 373   "Use ds_{read|write}_b128"
 374 >;
 375
 376 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 377 // all OS-es on VI and newer hardware to avoid assertion failures due
 378 // to missing ADDR64 variants of MUBUF instructions.
 379 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 380 // instructions.
 381
 382 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 383   "FlatForGlobal",
 384   "true",
 385   "Force to generate flat instruction for global"
 386 >;
 387
 388 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 389   "auto-waitcnt-before-barrier",
 390   "AutoWaitcntBeforeBarrier",
 391   "true",
 392   "Hardware automatically inserts waitcnt before barrier"
 393 >;
 394
 395 def FeatureCodeObjectV3 : SubtargetFeature <
 396   "code-object-v3",
 397   "CodeObjectV3",
 398   "true",
 399   "Generate code object version 3"
 400 >;
 401
 402 // Dummy feature used to disable assembler instructions.
 403 def FeatureDisable : SubtargetFeature<"",
 404   "FeatureDisable","true",
 405   "Dummy feature to disable assembler instructions"
 406 >;
 407
 408 def FeatureGCN : SubtargetFeature<"gcn",
 409   "IsGCN",
 410   "true",
 411   "GCN or newer GPU"
 412 >;
 413
 414 class GCNSubtargetFeatureGeneration <string Value,
 415                                   list<SubtargetFeature> Implies> :
 416         SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
 417
 418 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 419   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 420   FeatureWavefrontSize64, FeatureGCN,
 421   FeatureLDSBankCount32, FeatureMovrel]
 422 >;
 423
 424 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 425   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 426   FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 427   FeatureCIInsts, FeatureMovrel]
 428 >;
 429
 430 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 431   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 432    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 433    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 434    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 435    FeatureScalarStores, FeatureInv2PiInlineImm,
 436    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 437    FeatureIntClamp
 438   ]
 439 >;
 440
 441 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 442   [FeatureFP64, FeatureLocalMemorySize65536,
 443    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 444    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 445    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 446    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 447    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 448    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 449    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 450    FeatureAddNoCarryInsts, FeatureScalarAtomics
 451   ]
 452 >;
 453
 454 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
 455                                   list<SubtargetFeature> Implies>
 456                                  : SubtargetFeature <
 457   "isaver"#Major#"."#Minor#"."#Stepping,
 458   "IsaVersion",
 459   "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
 460   "Instruction set version number",
 461   Implies
 462 >;
 463
 464 def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
 465   [FeatureSouthernIslands,
 466    FeatureFastFMAF32,
 467    HalfRate64Ops,
 468    FeatureLDSBankCount32]>;
 469
 470 def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
 471   [FeatureSouthernIslands,
 472    FeatureLDSBankCount32]>;
 473
 474 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
 475   [FeatureSeaIslands,
 476    FeatureLDSBankCount32]>;
 477
 478 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
 479   [FeatureSeaIslands,
 480    HalfRate64Ops,
 481    FeatureLDSBankCount32,
 482    FeatureFastFMAF32]>;
 483
 484 def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
 485   [FeatureSeaIslands,
 486    FeatureLDSBankCount16,
 487    FeatureFastFMAF32]>;
 488
 489 def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
 490   [FeatureSeaIslands,
 491    FeatureLDSBankCount16]>;
 492
 493 def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
 494   [FeatureSeaIslands,
 495    FeatureLDSBankCount32]>;
 496
 497 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
 498   [FeatureVolcanicIslands,
 499    FeatureFastFMAF32,
 500    HalfRate64Ops,
 501    FeatureLDSBankCount32,
 502    FeatureXNACK,
 503    FeatureUnpackedD16VMem]>;
 504
 505 def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
 506   [FeatureVolcanicIslands,
 507    FeatureLDSBankCount32,
 508    FeatureSGPRInitBug,
 509    FeatureUnpackedD16VMem]>;
 510
 511 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
 512   [FeatureVolcanicIslands,
 513    FeatureLDSBankCount32,
 514    FeatureUnpackedD16VMem]>;
 515
 516 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
 517   [FeatureVolcanicIslands,
 518    FeatureLDSBankCount16,
 519    FeatureXNACK]>;
 520
 521 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
 522   [FeatureGFX9,
 523    FeatureMadMixInsts,
 524    FeatureLDSBankCount32,
 525    FeatureD16PreservesUnusedBits]>;
 526
 527 def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
 528   [FeatureGFX9,
 529    FeatureMadMixInsts,
 530    FeatureLDSBankCount32,
 531    FeatureXNACK,
 532    FeatureD16PreservesUnusedBits]>;
 533
 534 def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
 535   [FeatureGFX9,
 536    FeatureLDSBankCount32,
 537    FeatureFmaMixInsts,
 538    FeatureD16PreservesUnusedBits]>;
 539
 540 def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
 541   [FeatureGFX9,
 542    HalfRate64Ops,
 543    FeatureFmaMixInsts,
 544    FeatureLDSBankCount32,
 545    FeatureDLInsts]>;
 546
 547 //===----------------------------------------------------------------------===//
 548 // Debugger related subtarget features.
 549 //===----------------------------------------------------------------------===//
 550
 551 def FeatureDebuggerInsertNops : SubtargetFeature<
 552   "amdgpu-debugger-insert-nops",
 553   "DebuggerInsertNops",
 554   "true",
 555   "Insert one nop instruction for each high level source statement"
 556 >;
 557
 558 def FeatureDebuggerEmitPrologue : SubtargetFeature<
 559   "amdgpu-debugger-emit-prologue",
 560   "DebuggerEmitPrologue",
 561   "true",
 562   "Emit debugger prologue"
 563 >;
 564
 565 //===----------------------------------------------------------------------===//
 566
 567 def AMDGPUInstrInfo : InstrInfo {
 568   let guessInstructionProperties = 1;
 569   let noNamedPositionallyEncodedOperands = 1;
 570 }
 571
 572 def AMDGPUAsmParser : AsmParser {
 573   // Some of the R600 registers have the same name, so this crashes.
 574   // For example T0_XYZW and T0_XY both have the asm name T0.
 575   let ShouldEmitMatchRegisterName = 0;
 576 }
 577
 578 def AMDGPUAsmWriter : AsmWriter {
 579   int PassSubtarget = 1;
 580 }
 581
 582 def AMDGPUAsmVariants {
 583   string Default = "Default";
 584   int Default_ID = 0;
 585   string VOP3 = "VOP3";
 586   int VOP3_ID = 1;
 587   string SDWA = "SDWA";
 588   int SDWA_ID = 2;
 589   string SDWA9 = "SDWA9";
 590   int SDWA9_ID = 3;
 591   string DPP = "DPP";
 592   int DPP_ID = 4;
 593   string Disable = "Disable";
 594   int Disable_ID = 5;
 595 }
 596
 597 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
 598   let Variant = AMDGPUAsmVariants.Default_ID;
 599   let Name = AMDGPUAsmVariants.Default;
 600 }
 601
 602 def VOP3AsmParserVariant : AsmParserVariant {
 603   let Variant = AMDGPUAsmVariants.VOP3_ID;
 604   let Name = AMDGPUAsmVariants.VOP3;
 605 }
 606
 607 def SDWAAsmParserVariant : AsmParserVariant {
 608   let Variant = AMDGPUAsmVariants.SDWA_ID;
 609   let Name = AMDGPUAsmVariants.SDWA;
 610 }
 611
 612 def SDWA9AsmParserVariant : AsmParserVariant {
 613   let Variant = AMDGPUAsmVariants.SDWA9_ID;
 614   let Name = AMDGPUAsmVariants.SDWA9;
 615 }
 616
 617
 618 def DPPAsmParserVariant : AsmParserVariant {
 619   let Variant = AMDGPUAsmVariants.DPP_ID;
 620   let Name = AMDGPUAsmVariants.DPP;
 621 }
 622
 623 def AMDGPU : Target {
 624   // Pull in Instruction Info:
 625   let InstructionSet = AMDGPUInstrInfo;
 626   let AssemblyParsers = [AMDGPUAsmParser];
 627   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
 628                                 VOP3AsmParserVariant,
 629                                 SDWAAsmParserVariant,
 630                                 SDWA9AsmParserVariant,
 631                                 DPPAsmParserVariant];
 632   let AssemblyWriters = [AMDGPUAsmWriter];
 633   let AllowRegisterRenaming = 1;
 634 }
 635
 636 // Dummy Instruction itineraries for pseudo instructions
 637 def ALU_NULL : FuncUnit;
 638 def NullALU : InstrItinClass;
 639
 640 //===----------------------------------------------------------------------===//
 641 // Predicate helper class
 642 //===----------------------------------------------------------------------===//
 643
 644 def isSICI : Predicate<
 645   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 646   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 647 >, AssemblerPredicate<"!FeatureGCN3Encoding">;
 648
 649 def isVI : Predicate <
 650   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
 651   AssemblerPredicate<"FeatureGCN3Encoding">;
 652
 653 def isGFX9 : Predicate <
 654   "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 655   AssemblerPredicate<"FeatureGFX9Insts">;
 656
 657 // TODO: Either the name to be changed or we simply use IsCI!
 658 def isCIVI : Predicate <
 659   "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
 660   AssemblerPredicate<"FeatureCIInsts">;
 661
 662 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
 663   AssemblerPredicate<"FeatureFlatAddressSpace">;
 664
 665 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
 666   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 667 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
 668   AssemblerPredicate<"FeatureFlatScratchInsts">;
 669 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
 670   AssemblerPredicate<"FeatureGFX9Insts">;
 671
 672 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
 673   AssemblerPredicate<"FeatureUnpackedD16VMem">;
 674 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
 675   AssemblerPredicate<"!FeatureUnpackedD16VMem">;
 676
 677 def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
 678   AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
 679
 680 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
 681 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
 682
 683 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 684   AssemblerPredicate<"FeatureGFX9Insts">;
 685
 686 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
 687   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 688
 689 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
 690   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 691
 692 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
 693   AssemblerPredicate<"Feature16BitInsts">;
 694 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
 695   AssemblerPredicate<"FeatureVOP3P">;
 696
 697 def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
 698   AssemblerPredicate<"!FeatureVOP3P">;
 699
 700 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
 701   AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
 702
 703 def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
 704   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 705
 706 def HasDPP : Predicate<"Subtarget->hasDPP()">,
 707   AssemblerPredicate<"FeatureDPP">;
 708
 709 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
 710   AssemblerPredicate<"FeatureIntClamp">;
 711
 712 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
 713   AssemblerPredicate<"FeatureMadMixInsts">;
 714
 715 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
 716   AssemblerPredicate<"FeatureScalarAtomics">;
 717
 718 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
 719 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
 720 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
 721                       AssemblerPredicate<"FeatureVGPRIndexMode">;
 722 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
 723                 AssemblerPredicate<"FeatureMovrel">;
 724
 725 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
 726   AssemblerPredicate<"FeatureFmaMixInsts">;
 727
 728 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
 729   AssemblerPredicate<"FeatureDLInsts">;
 730
 731
 732 def EnableLateCFGStructurize : Predicate<
 733   "EnableLateStructurizeCFG">;
 734
 735 // Include AMDGPU TD files
 736 include "SISchedule.td"
 737 include "GCNProcessors.td"
 738 include "AMDGPUInstrInfo.td"
 739 include "AMDGPUIntrinsics.td"
 740 include "SIIntrinsics.td"
 741 include "AMDGPURegisterInfo.td"
 742 include "AMDGPURegisterBanks.td"
 743 include "AMDGPUInstructions.td"
 744 include "SIInstrInfo.td"
 745 include "AMDGPUCallingConv.td"
 746 include "AMDGPUSearchableTables.td"