contrib/llvm/lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===------------------------------------------------------------===//
   9
  10 include "llvm/TableGen/SearchableTable.td"
  11 include "llvm/Target/Target.td"
  12 include "AMDGPUFeatures.td"
  13
  14 //===------------------------------------------------------------===//
  15 // Subtarget Features (device properties)
  16 //===------------------------------------------------------------===//
  17
  18 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  19   "FastFMAF32",
  20   "true",
  21   "Assuming f32 fma is at least as fast as mul + add"
  22 >;
  23
  24 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  25   "MIMG_R128",
  26   "true",
  27   "Support 128-bit texture resources"
  28 >;
  29
  30 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  31   "HalfRate64Ops",
  32   "true",
  33   "Most fp64 instructions are half rate instead of quarter"
  34 >;
  35
  36 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  37   "FlatAddressSpace",
  38   "true",
  39   "Support flat address space"
  40 >;
  41
  42 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  43   "FlatInstOffsets",
  44   "true",
  45   "Flat instructions have immediate offset addressing mode"
  46 >;
  47
  48 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  49   "FlatGlobalInsts",
  50   "true",
  51   "Have global_* flat memory instructions"
  52 >;
  53
  54 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  55   "FlatScratchInsts",
  56   "true",
  57   "Have scratch_* flat memory instructions"
  58 >;
  59
  60 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  61   "AddNoCarryInsts",
  62   "true",
  63   "Have VALU add/sub instructions without carry out"
  64 >;
  65
  66 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  67   "UnalignedBufferAccess",
  68   "true",
  69   "Support unaligned global loads and stores"
  70 >;
  71
  72 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
  73   "TrapHandler",
  74   "true",
  75   "Trap handler support"
  76 >;
  77
  78 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
  79   "UnalignedScratchAccess",
  80   "true",
  81   "Support unaligned scratch loads and stores"
  82 >;
  83
  84 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
  85   "HasApertureRegs",
  86   "true",
  87   "Has Memory Aperture Base and Size Registers"
  88 >;
  89
  90 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
  91   "HasMadMixInsts",
  92   "true",
  93   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
  94 >;
  95
  96 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
  97   "HasFmaMixInsts",
  98   "true",
  99   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 100 >;
 101
 102 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 103 // XNACK. The current default kernel driver setting is:
 104 // - graphics ring: XNACK disabled
 105 // - compute ring: XNACK enabled
 106 //
 107 // If XNACK is enabled, the VMEM latency can be worse.
 108 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 109 def FeatureXNACK : SubtargetFeature<"xnack",
 110   "EnableXNACK",
 111   "true",
 112   "Enable XNACK support"
 113 >;
 114
 115 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 116   "SGPRInitBug",
 117   "true",
 118   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 119 >;
 120
 121 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 122   "ldsbankcount"#Value,
 123   "LDSBankCount",
 124   !cast<string>(Value),
 125   "The number of LDS banks per compute unit."
 126 >;
 127
 128 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 129 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 130
 131 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 132   "GCN3Encoding",
 133   "true",
 134   "Encoding format for VI"
 135 >;
 136
 137 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 138   "CIInsts",
 139   "true",
 140   "Additional instructions for CI+"
 141 >;
 142
 143 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 144   "GFX9Insts",
 145   "true",
 146   "Additional instructions for GFX9+"
 147 >;
 148
 149 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 150   "HasSMemRealTime",
 151   "true",
 152   "Has s_memrealtime instruction"
 153 >;
 154
 155 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 156   "HasInv2PiInlineImm",
 157   "true",
 158   "Has 1 / (2 * pi) as inline immediate"
 159 >;
 160
 161 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 162   "Has16BitInsts",
 163   "true",
 164   "Has i16/f16 instructions"
 165 >;
 166
 167 def FeatureVOP3P : SubtargetFeature<"vop3p",
 168   "HasVOP3PInsts",
 169   "true",
 170   "Has VOP3P packed instructions"
 171 >;
 172
 173 def FeatureMovrel : SubtargetFeature<"movrel",
 174   "HasMovrel",
 175   "true",
 176   "Has v_movrel*_b32 instructions"
 177 >;
 178
 179 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 180   "HasVGPRIndexMode",
 181   "true",
 182   "Has VGPR mode register indexing"
 183 >;
 184
 185 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 186   "HasScalarStores",
 187   "true",
 188   "Has store scalar memory instructions"
 189 >;
 190
 191 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 192   "HasScalarAtomics",
 193   "true",
 194   "Has atomic scalar memory instructions"
 195 >;
 196
 197 def FeatureSDWA : SubtargetFeature<"sdwa",
 198   "HasSDWA",
 199   "true",
 200   "Support SDWA (Sub-DWORD Addressing) extension"
 201 >;
 202
 203 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 204   "HasSDWAOmod",
 205   "true",
 206   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 207 >;
 208
 209 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 210   "HasSDWAScalar",
 211   "true",
 212   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 213 >;
 214
 215 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 216   "HasSDWASdst",
 217   "true",
 218   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 219 >;
 220
 221 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 222   "HasSDWAMac",
 223   "true",
 224   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 225 >;
 226
 227 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 228   "HasSDWAOutModsVOPC",
 229   "true",
 230   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 231 >;
 232
 233 def FeatureDPP : SubtargetFeature<"dpp",
 234   "HasDPP",
 235   "true",
 236   "Support DPP (Data Parallel Primitives) extension"
 237 >;
 238
 239 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 240   "HasIntClamp",
 241   "true",
 242   "Support clamp for integer destination"
 243 >;
 244
 245 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 246   "HasUnpackedD16VMem",
 247   "true",
 248   "Has unpacked d16 vmem instructions"
 249 >;
 250
 251 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 252   "HasDLInsts",
 253   "true",
 254   "Has deep learning instructions"
 255 >;
 256
 257 def FeatureD16PreservesUnusedBits : SubtargetFeature<
 258   "d16-preserves-unused-bits",
 259   "D16PreservesUnusedBits",
 260   "true",
 261   "If present, then instructions defined by HasD16LoadStore predicate preserve "
 262   "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
 263   "zero unused bits."
 264 >;
 265
 266 //===------------------------------------------------------------===//
 267 // Subtarget Features (options and debugging)
 268 //===------------------------------------------------------------===//
 269
 270 // Denormal handling for fp64 and fp16 is controlled by the same
 271 // config register when fp16 supported.
 272 // TODO: Do we need a separate f16 setting when not legal?
 273 def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
 274   "FP64FP16Denormals",
 275   "true",
 276   "Enable double and half precision denormal handling",
 277   [FeatureFP64]
 278 >;
 279
 280 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
 281   "FP64FP16Denormals",
 282   "true",
 283   "Enable double and half precision denormal handling",
 284   [FeatureFP64, FeatureFP64FP16Denormals]
 285 >;
 286
 287 def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
 288   "FP64FP16Denormals",
 289   "true",
 290   "Enable half precision denormal handling",
 291   [FeatureFP64FP16Denormals]
 292 >;
 293
 294 def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
 295   "FPExceptions",
 296   "true",
 297   "Enable floating point exceptions"
 298 >;
 299
 300 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 301   "max-private-element-size-"#size,
 302   "MaxPrivateElementSize",
 303   !cast<string>(size),
 304   "Maximum private access size may be "#size
 305 >;
 306
 307 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 308 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 309 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 310
 311 def FeatureEnableHugePrivateBuffer : SubtargetFeature<
 312   "huge-private-buffer",
 313   "EnableHugePrivateBuffer",
 314   "true",
 315   "Enable private/scratch buffer sizes greater than 128 GB"
 316 >;
 317
 318 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 319   "EnableVGPRSpilling",
 320   "true",
 321   "Enable spilling of VGPRs to scratch memory"
 322 >;
 323
 324 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 325   "DumpCode",
 326   "true",
 327   "Dump MachineInstrs in the CodeEmitter"
 328 >;
 329
 330 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 331   "DumpCode",
 332   "true",
 333   "Dump MachineInstrs in the CodeEmitter"
 334 >;
 335
 336 // XXX - This should probably be removed once enabled by default
 337 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 338   "EnableLoadStoreOpt",
 339   "true",
 340   "Enable SI load/store optimizer pass"
 341 >;
 342
 343 // Performance debugging feature. Allow using DS instruction immediate
 344 // offsets even if the base pointer can't be proven to be base. On SI,
 345 // base pointer values that won't give the same result as a 16-bit add
 346 // are not safe to fold, but this will override the conservative test
 347 // for the base pointer.
 348 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 349   "unsafe-ds-offset-folding",
 350   "EnableUnsafeDSOffsetFolding",
 351   "true",
 352   "Force using DS instruction immediate offsets on SI"
 353 >;
 354
 355 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 356   "EnableSIScheduler",
 357   "true",
 358   "Enable SI Machine Scheduler"
 359 >;
 360
 361 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 362   "EnableDS128",
 363   "true",
 364   "Use ds_{read|write}_b128"
 365 >;
 366
 367 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 368 // all OS-es on VI and newer hardware to avoid assertion failures due
 369 // to missing ADDR64 variants of MUBUF instructions.
 370 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 371 // instructions.
 372
 373 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 374   "FlatForGlobal",
 375   "true",
 376   "Force to generate flat instruction for global"
 377 >;
 378
 379 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 380   "auto-waitcnt-before-barrier",
 381   "AutoWaitcntBeforeBarrier",
 382   "true",
 383   "Hardware automatically inserts waitcnt before barrier"
 384 >;
 385
 386 def FeatureCodeObjectV3 : SubtargetFeature <
 387   "code-object-v3",
 388   "CodeObjectV3",
 389   "true",
 390   "Generate code object version 3"
 391 >;
 392
 393 // Dummy feature used to disable assembler instructions.
 394 def FeatureDisable : SubtargetFeature<"",
 395   "FeatureDisable","true",
 396   "Dummy feature to disable assembler instructions"
 397 >;
 398
 399 def FeatureGCN : SubtargetFeature<"gcn",
 400   "IsGCN",
 401   "true",
 402   "GCN or newer GPU"
 403 >;
 404
 405 class GCNSubtargetFeatureGeneration <string Value,
 406                                   list<SubtargetFeature> Implies> :
 407         SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
 408
 409 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 410   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 411   FeatureWavefrontSize64, FeatureGCN,
 412   FeatureLDSBankCount32, FeatureMovrel]
 413 >;
 414
 415 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 416   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 417   FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 418   FeatureCIInsts, FeatureMovrel]
 419 >;
 420
 421 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 422   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 423    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 424    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 425    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 426    FeatureScalarStores, FeatureInv2PiInlineImm,
 427    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 428    FeatureIntClamp
 429   ]
 430 >;
 431
 432 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 433   [FeatureFP64, FeatureLocalMemorySize65536,
 434    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 435    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 436    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 437    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 438    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 439    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 440    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 441    FeatureAddNoCarryInsts, FeatureScalarAtomics
 442   ]
 443 >;
 444
 445 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
 446                                   list<SubtargetFeature> Implies>
 447                                  : SubtargetFeature <
 448   "isaver"#Major#"."#Minor#"."#Stepping,
 449   "IsaVersion",
 450   "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
 451   "Instruction set version number",
 452   Implies
 453 >;
 454
 455 def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
 456   [FeatureSouthernIslands,
 457    FeatureFastFMAF32,
 458    HalfRate64Ops,
 459    FeatureLDSBankCount32]>;
 460
 461 def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
 462   [FeatureSouthernIslands,
 463    FeatureLDSBankCount32]>;
 464
 465 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
 466   [FeatureSeaIslands,
 467    FeatureLDSBankCount32]>;
 468
 469 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
 470   [FeatureSeaIslands,
 471    HalfRate64Ops,
 472    FeatureLDSBankCount32,
 473    FeatureFastFMAF32]>;
 474
 475 def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
 476   [FeatureSeaIslands,
 477    FeatureLDSBankCount16,
 478    FeatureFastFMAF32]>;
 479
 480 def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
 481   [FeatureSeaIslands,
 482    FeatureLDSBankCount16]>;
 483
 484 def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
 485   [FeatureSeaIslands,
 486    FeatureLDSBankCount32]>;
 487
 488 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
 489   [FeatureVolcanicIslands,
 490    FeatureFastFMAF32,
 491    HalfRate64Ops,
 492    FeatureLDSBankCount32,
 493    FeatureXNACK,
 494    FeatureUnpackedD16VMem]>;
 495
 496 def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
 497   [FeatureVolcanicIslands,
 498    FeatureLDSBankCount32,
 499    FeatureSGPRInitBug,
 500    FeatureUnpackedD16VMem]>;
 501
 502 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
 503   [FeatureVolcanicIslands,
 504    FeatureLDSBankCount32,
 505    FeatureUnpackedD16VMem]>;
 506
 507 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
 508   [FeatureVolcanicIslands,
 509    FeatureLDSBankCount16,
 510    FeatureXNACK]>;
 511
 512 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
 513   [FeatureGFX9,
 514    FeatureMadMixInsts,
 515    FeatureLDSBankCount32,
 516    FeatureD16PreservesUnusedBits]>;
 517
 518 def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
 519   [FeatureGFX9,
 520    FeatureMadMixInsts,
 521    FeatureLDSBankCount32,
 522    FeatureXNACK,
 523    FeatureD16PreservesUnusedBits]>;
 524
 525 def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
 526   [FeatureGFX9,
 527    FeatureLDSBankCount32,
 528    FeatureFmaMixInsts,
 529    FeatureD16PreservesUnusedBits]>;
 530
 531 def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
 532   [FeatureGFX9,
 533    HalfRate64Ops,
 534    FeatureFmaMixInsts,
 535    FeatureLDSBankCount32,
 536    FeatureDLInsts]>;
 537
 538 //===----------------------------------------------------------------------===//
 539 // Debugger related subtarget features.
 540 //===----------------------------------------------------------------------===//
 541
 542 def FeatureDebuggerInsertNops : SubtargetFeature<
 543   "amdgpu-debugger-insert-nops",
 544   "DebuggerInsertNops",
 545   "true",
 546   "Insert one nop instruction for each high level source statement"
 547 >;
 548
 549 def FeatureDebuggerEmitPrologue : SubtargetFeature<
 550   "amdgpu-debugger-emit-prologue",
 551   "DebuggerEmitPrologue",
 552   "true",
 553   "Emit debugger prologue"
 554 >;
 555
 556 //===----------------------------------------------------------------------===//
 557
 558 def AMDGPUInstrInfo : InstrInfo {
 559   let guessInstructionProperties = 1;
 560   let noNamedPositionallyEncodedOperands = 1;
 561 }
 562
 563 def AMDGPUAsmParser : AsmParser {
 564   // Some of the R600 registers have the same name, so this crashes.
 565   // For example T0_XYZW and T0_XY both have the asm name T0.
 566   let ShouldEmitMatchRegisterName = 0;
 567 }
 568
 569 def AMDGPUAsmWriter : AsmWriter {
 570   int PassSubtarget = 1;
 571 }
 572
 573 def AMDGPUAsmVariants {
 574   string Default = "Default";
 575   int Default_ID = 0;
 576   string VOP3 = "VOP3";
 577   int VOP3_ID = 1;
 578   string SDWA = "SDWA";
 579   int SDWA_ID = 2;
 580   string SDWA9 = "SDWA9";
 581   int SDWA9_ID = 3;
 582   string DPP = "DPP";
 583   int DPP_ID = 4;
 584   string Disable = "Disable";
 585   int Disable_ID = 5;
 586 }
 587
 588 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
 589   let Variant = AMDGPUAsmVariants.Default_ID;
 590   let Name = AMDGPUAsmVariants.Default;
 591 }
 592
 593 def VOP3AsmParserVariant : AsmParserVariant {
 594   let Variant = AMDGPUAsmVariants.VOP3_ID;
 595   let Name = AMDGPUAsmVariants.VOP3;
 596 }
 597
 598 def SDWAAsmParserVariant : AsmParserVariant {
 599   let Variant = AMDGPUAsmVariants.SDWA_ID;
 600   let Name = AMDGPUAsmVariants.SDWA;
 601 }
 602
 603 def SDWA9AsmParserVariant : AsmParserVariant {
 604   let Variant = AMDGPUAsmVariants.SDWA9_ID;
 605   let Name = AMDGPUAsmVariants.SDWA9;
 606 }
 607
 608
 609 def DPPAsmParserVariant : AsmParserVariant {
 610   let Variant = AMDGPUAsmVariants.DPP_ID;
 611   let Name = AMDGPUAsmVariants.DPP;
 612 }
 613
 614 def AMDGPU : Target {
 615   // Pull in Instruction Info:
 616   let InstructionSet = AMDGPUInstrInfo;
 617   let AssemblyParsers = [AMDGPUAsmParser];
 618   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
 619                                 VOP3AsmParserVariant,
 620                                 SDWAAsmParserVariant,
 621                                 SDWA9AsmParserVariant,
 622                                 DPPAsmParserVariant];
 623   let AssemblyWriters = [AMDGPUAsmWriter];
 624   let AllowRegisterRenaming = 1;
 625 }
 626
 627 // Dummy Instruction itineraries for pseudo instructions
 628 def ALU_NULL : FuncUnit;
 629 def NullALU : InstrItinClass;
 630
 631 //===----------------------------------------------------------------------===//
 632 // Predicate helper class
 633 //===----------------------------------------------------------------------===//
 634
 635 def isSICI : Predicate<
 636   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 637   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 638 >, AssemblerPredicate<"!FeatureGCN3Encoding">;
 639
 640 def isVI : Predicate <
 641   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
 642   AssemblerPredicate<"FeatureGCN3Encoding">;
 643
 644 def isGFX9 : Predicate <
 645   "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 646   AssemblerPredicate<"FeatureGFX9Insts">;
 647
 648 // TODO: Either the name to be changed or we simply use IsCI!
 649 def isCIVI : Predicate <
 650   "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
 651   AssemblerPredicate<"FeatureCIInsts">;
 652
 653 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
 654   AssemblerPredicate<"FeatureFlatAddressSpace">;
 655
 656 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
 657   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 658 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
 659   AssemblerPredicate<"FeatureFlatScratchInsts">;
 660 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
 661   AssemblerPredicate<"FeatureGFX9Insts">;
 662
 663 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
 664   AssemblerPredicate<"FeatureUnpackedD16VMem">;
 665 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
 666   AssemblerPredicate<"!FeatureUnpackedD16VMem">;
 667
 668 def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
 669   AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
 670
 671 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
 672 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
 673
 674 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 675   AssemblerPredicate<"FeatureGFX9Insts">;
 676
 677 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
 678   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 679
 680 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
 681   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 682
 683 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
 684   AssemblerPredicate<"Feature16BitInsts">;
 685 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
 686   AssemblerPredicate<"FeatureVOP3P">;
 687
 688 def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
 689   AssemblerPredicate<"!FeatureVOP3P">;
 690
 691 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
 692   AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
 693
 694 def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
 695   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 696
 697 def HasDPP : Predicate<"Subtarget->hasDPP()">,
 698   AssemblerPredicate<"FeatureDPP">;
 699
 700 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
 701   AssemblerPredicate<"FeatureIntClamp">;
 702
 703 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
 704   AssemblerPredicate<"FeatureMadMixInsts">;
 705
 706 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
 707   AssemblerPredicate<"FeatureScalarAtomics">;
 708
 709 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
 710 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
 711 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
 712                       AssemblerPredicate<"FeatureVGPRIndexMode">;
 713 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
 714                 AssemblerPredicate<"FeatureMovrel">;
 715
 716 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
 717   AssemblerPredicate<"FeatureFmaMixInsts">;
 718
 719 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
 720   AssemblerPredicate<"FeatureDLInsts">;
 721
 722
 723 def EnableLateCFGStructurize : Predicate<
 724   "EnableLateStructurizeCFG">;
 725
 726 // Include AMDGPU TD files
 727 include "SISchedule.td"
 728 include "GCNProcessors.td"
 729 include "AMDGPUInstrInfo.td"
 730 include "AMDGPUIntrinsics.td"
 731 include "SIIntrinsics.td"
 732 include "AMDGPURegisterInfo.td"
 733 include "AMDGPURegisterBanks.td"
 734 include "AMDGPUInstructions.td"
 735 include "SIInstrInfo.td"
 736 include "AMDGPUCallingConv.td"
 737 include "AMDGPUSearchableTables.td"