1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===------------------------------------------------------------===//
13 // Subtarget Features (device properties)
14 //===------------------------------------------------------------===//
16 def FeatureFP64 : SubtargetFeature<"fp64",
19 "Enable double precision operations"
22 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
25 "Assuming f32 fma is at least as fast as mul + add"
28 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
31 "Most fp64 instructions are half rate instead of quarter"
34 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
37 "Older version of ALU instructions encoding"
40 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
43 "Specify use of dedicated vertex cache"
46 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
52 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
58 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61 "Support flat address space"
64 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
65 "UnalignedBufferAccess",
67 "Support unaligned global loads and stores"
70 def FeatureXNACK : SubtargetFeature<"xnack",
73 "Enable XNACK support"
76 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
79 "VI SGPR initilization bug requiring a fixed SGPR allocation size"
82 class SubtargetFeatureFetchLimit <string Value> :
83 SubtargetFeature <"fetch"#Value,
86 "Limit the maximum number of fetches in a clause to "#Value
89 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
90 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
92 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
93 "wavefrontsize"#Value,
96 "The number of threads per wavefront"
99 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
100 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
101 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
103 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
104 "ldsbankcount"#Value,
106 !cast<string>(Value),
107 "The number of LDS banks per compute unit."
110 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
111 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
113 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
115 "isaver"#Major#"."#Minor#"."#Stepping,
117 "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
118 "Instruction set version number"
121 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
122 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
123 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
124 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
125 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
127 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
128 "localmemorysize"#Value,
130 !cast<string>(Value),
131 "The size of local memory in bytes"
134 def FeatureGCN : SubtargetFeature<"gcn",
140 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
143 "Encoding format for SI and CI"
146 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
149 "Encoding format for VI"
152 def FeatureCIInsts : SubtargetFeature<"ci-insts",
155 "Additional intstructions for CI+"
158 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
161 "Has s_memrealtime instruction"
164 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
167 "Has i16/f16 instructions"
170 //===------------------------------------------------------------===//
171 // Subtarget Features (options and debugging)
172 //===------------------------------------------------------------===//
174 // Some instructions do not support denormals despite this flag. Using
175 // fp32 denormals also causes instructions to run at the double
176 // precision rate for the device.
177 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
180 "Enable single precision denormal handling"
183 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
186 "Enable double precision denormal handling",
190 def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
193 "Enable floating point exceptions"
196 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
197 "max-private-element-size-"#size,
198 "MaxPrivateElementSize",
200 "Maximum private access size may be "#size
203 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
204 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
205 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
207 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
208 "EnableVGPRSpilling",
210 "Enable spilling of VGPRs to scratch memory"
213 def FeatureDumpCode : SubtargetFeature <"DumpCode",
216 "Dump MachineInstrs in the CodeEmitter"
219 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
222 "Dump MachineInstrs in the CodeEmitter"
225 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
226 "EnablePromoteAlloca",
228 "Enable promote alloca pass"
231 // XXX - This should probably be removed once enabled by default
232 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
233 "EnableLoadStoreOpt",
235 "Enable SI load/store optimizer pass"
238 // Performance debugging feature. Allow using DS instruction immediate
239 // offsets even if the base pointer can't be proven to be base. On SI,
240 // base pointer values that won't give the same result as a 16-bit add
241 // are not safe to fold, but this will override the conservative test
242 // for the base pointer.
243 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
244 "unsafe-ds-offset-folding",
245 "EnableUnsafeDSOffsetFolding",
247 "Force using DS instruction immediate offsets on SI"
250 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
253 "Enable SI Machine Scheduler"
256 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
259 "Force to generate flat instruction for global"
262 // Dummy feature used to disable assembler instructions.
263 def FeatureDisable : SubtargetFeature<"",
264 "FeatureDisable","true",
265 "Dummy feature to disable assembler instructions"
268 class SubtargetFeatureGeneration <string Value,
269 list<SubtargetFeature> Implies> :
270 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
271 Value#" GPU generation", Implies>;
273 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
274 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
275 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
277 def FeatureR600 : SubtargetFeatureGeneration<"R600",
278 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
281 def FeatureR700 : SubtargetFeatureGeneration<"R700",
282 [FeatureFetchLimit16, FeatureLocalMemorySize0]
285 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
286 [FeatureFetchLimit16, FeatureLocalMemorySize32768]
289 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
290 [FeatureFetchLimit16, FeatureWavefrontSize64,
291 FeatureLocalMemorySize32768]
294 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
295 [FeatureFP64, FeatureLocalMemorySize32768,
296 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
297 FeatureLDSBankCount32]
300 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
301 [FeatureFP64, FeatureLocalMemorySize65536,
302 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
303 FeatureGCN1Encoding, FeatureCIInsts]
306 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
307 [FeatureFP64, FeatureLocalMemorySize65536,
308 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
309 FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
314 //===----------------------------------------------------------------------===//
315 // Debugger related subtarget features.
316 //===----------------------------------------------------------------------===//
318 def FeatureDebuggerInsertNops : SubtargetFeature<
319 "amdgpu-debugger-insert-nops",
320 "DebuggerInsertNops",
322 "Insert one nop instruction for each high level source statement"
325 def FeatureDebuggerReserveRegs : SubtargetFeature<
326 "amdgpu-debugger-reserve-regs",
327 "DebuggerReserveRegs",
329 "Reserve registers for debugger usage"
332 def FeatureDebuggerEmitPrologue : SubtargetFeature<
333 "amdgpu-debugger-emit-prologue",
334 "DebuggerEmitPrologue",
336 "Emit debugger prologue"
339 //===----------------------------------------------------------------------===//
341 def AMDGPUInstrInfo : InstrInfo {
342 let guessInstructionProperties = 1;
343 let noNamedPositionallyEncodedOperands = 1;
346 def AMDGPUAsmParser : AsmParser {
347 // Some of the R600 registers have the same name, so this crashes.
348 // For example T0_XYZW and T0_XY both have the asm name T0.
349 let ShouldEmitMatchRegisterName = 0;
352 def AMDGPU : Target {
353 // Pull in Instruction Info:
354 let InstructionSet = AMDGPUInstrInfo;
355 let AssemblyParsers = [AMDGPUAsmParser];
358 // Dummy Instruction itineraries for pseudo instructions
359 def ALU_NULL : FuncUnit;
360 def NullALU : InstrItinClass;
362 //===----------------------------------------------------------------------===//
363 // Predicate helper class
364 //===----------------------------------------------------------------------===//
366 def TruePredicate : Predicate<"true">;
368 def isSICI : Predicate<
369 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
370 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
371 >, AssemblerPredicate<"FeatureGCN1Encoding">;
373 def isVI : Predicate <
374 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
375 AssemblerPredicate<"FeatureGCN3Encoding">;
377 def isCIVI : Predicate <
378 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
379 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
380 >, AssemblerPredicate<"FeatureCIInsts">;
382 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
384 class PredicateControl {
385 Predicate SubtargetPredicate;
386 Predicate SIAssemblerPredicate = isSICI;
387 Predicate VIAssemblerPredicate = isVI;
388 list<Predicate> AssemblerPredicates = [];
389 Predicate AssemblerPredicate = TruePredicate;
390 list<Predicate> OtherPredicates = [];
391 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
396 // Include AMDGPU TD files
397 include "R600Schedule.td"
398 include "SISchedule.td"
399 include "Processors.td"
400 include "AMDGPUInstrInfo.td"
401 include "AMDGPUIntrinsics.td"
402 include "AMDGPURegisterInfo.td"
403 include "AMDGPUInstructions.td"
404 include "AMDGPUCallingConv.td"