1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPUTargetMachine.h"
21 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
22 #include "InstPrinter/AMDGPUInstPrinter.h"
23 #include "Utils/AMDGPUBaseInfo.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66 const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67 // TODO: Is there any real use for the flush in only / flush out only modes?
69 uint32_t FP32Denormals =
70 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 uint32_t FP64Denormals =
73 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
75 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77 FP_DENORM_MODE_SP(FP32Denormals) |
78 FP_DENORM_MODE_DP(FP64Denormals);
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83 std::unique_ptr<MCStreamer> &&Streamer) {
84 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88 TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89 createAMDGPUAsmPrinterPass);
90 TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91 createAMDGPUAsmPrinterPass);
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95 std::unique_ptr<MCStreamer> Streamer)
96 : AsmPrinter(TM, std::move(Streamer)) {
97 AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101 return "AMDGPU Assembly Printer";
104 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
105 return TM.getMCSubtargetInfo();
108 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
109 return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
112 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
113 if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
116 AMDGPU::IsaInfo::IsaVersion ISA =
117 AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
119 getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
120 getTargetStreamer().EmitDirectiveHSACodeObjectISA(
121 ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
122 getTargetStreamer().EmitStartOfCodeObjectMetadata(M);
125 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
126 if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
129 getTargetStreamer().EmitEndOfCodeObjectMetadata();
132 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
133 const MachineBasicBlock *MBB) const {
134 if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
140 // If this is a block implementing a long branch, an expression relative to
141 // the start of the block is needed. to the start of the block.
142 // XXX - Is there a smarter way to check this?
143 return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
146 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
147 const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
148 if (!MFI->isEntryFunction())
151 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
152 amd_kernel_code_t KernelCode;
153 if (STM.isAmdCodeObjectV2(*MF)) {
154 getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
156 OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
157 getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
160 if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
162 getTargetStreamer().EmitKernelCodeObjectMetadata(*MF->getFunction(),
166 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
167 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
168 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
169 if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
170 SmallString<128> SymbolName;
171 getNameWithPrefix(SymbolName, MF->getFunction()),
172 getTargetStreamer().EmitAMDGPUSymbolType(
173 SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
176 AsmPrinter::EmitFunctionEntryLabel();
179 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
181 // Group segment variables aren't emitted in HSA.
182 if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
185 AsmPrinter::EmitGlobalVariable(GV);
188 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
189 CallGraphResourceInfo.clear();
190 return AsmPrinter::doFinalization(M);
193 // Print comments that apply to both callable functions and entry points.
194 void AMDGPUAsmPrinter::emitCommonFunctionComments(
197 uint32_t ScratchSize,
199 OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
200 OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
201 OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
202 OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
205 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
206 CurrentProgramInfo = SIProgramInfo();
208 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
210 // The starting address of all shader programs must be 256 bytes aligned.
211 // Regular functions just need the basic required instruction alignment.
212 MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
214 SetupMachineFunction(MF);
216 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
217 MCContext &Context = getObjFileLowering().getContext();
218 if (!STM.isAmdHsaOS()) {
219 MCSectionELF *ConfigSection =
220 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
221 OutStreamer->SwitchSection(ConfigSection);
224 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
225 if (MFI->isEntryFunction()) {
226 getSIProgramInfo(CurrentProgramInfo, MF);
228 auto I = CallGraphResourceInfo.insert(
229 std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
230 SIFunctionResourceInfo &Info = I.first->second;
231 assert(I.second && "should only be called once per function");
232 Info = analyzeResourceUsage(MF);
235 if (!STM.isAmdHsaOS()) {
236 EmitProgramInfoSI(MF, CurrentProgramInfo);
239 EmitProgramInfoR600(MF);
244 DisasmLineMaxLen = 0;
249 MCSectionELF *CommentSection =
250 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
251 OutStreamer->SwitchSection(CommentSection);
253 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
254 if (!MFI->isEntryFunction()) {
255 OutStreamer->emitRawComment(" Function info:", false);
256 SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
257 emitCommonFunctionComments(
259 Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
260 Info.PrivateSegmentSize,
261 getFunctionCodeSize(MF));
265 OutStreamer->emitRawComment(" Kernel info:", false);
266 emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
267 CurrentProgramInfo.NumSGPR,
268 CurrentProgramInfo.ScratchSize,
269 getFunctionCodeSize(MF));
271 OutStreamer->emitRawComment(" codeLenInByte = " +
272 Twine(getFunctionCodeSize(MF)), false);
273 OutStreamer->emitRawComment(
274 " NumSgprs: " + Twine(CurrentProgramInfo.NumSGPR), false);
275 OutStreamer->emitRawComment(
276 " NumVgprs: " + Twine(CurrentProgramInfo.NumVGPR), false);
278 OutStreamer->emitRawComment(
279 " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
280 OutStreamer->emitRawComment(
281 " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
282 OutStreamer->emitRawComment(
283 " ScratchSize: " + Twine(CurrentProgramInfo.ScratchSize), false);
284 OutStreamer->emitRawComment(
285 " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
286 " bytes/workgroup (compile time only)", false);
288 OutStreamer->emitRawComment(
289 " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
290 OutStreamer->emitRawComment(
291 " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
293 OutStreamer->emitRawComment(
294 " NumSGPRsForWavesPerEU: " +
295 Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
296 OutStreamer->emitRawComment(
297 " NumVGPRsForWavesPerEU: " +
298 Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
300 OutStreamer->emitRawComment(
301 " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
303 OutStreamer->emitRawComment(
304 " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
307 if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
308 OutStreamer->emitRawComment(
309 " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
310 Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
311 OutStreamer->emitRawComment(
312 " DebuggerPrivateSegmentBufferSGPR: s" +
313 Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
316 OutStreamer->emitRawComment(
317 " COMPUTE_PGM_RSRC2:USER_SGPR: " +
318 Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
319 OutStreamer->emitRawComment(
320 " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
321 Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
322 OutStreamer->emitRawComment(
323 " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
324 Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
325 OutStreamer->emitRawComment(
326 " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
327 Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
328 OutStreamer->emitRawComment(
329 " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
330 Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
331 OutStreamer->emitRawComment(
332 " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
333 Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
336 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
337 OutStreamer->emitRawComment(
338 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
342 if (STM.dumpCode()) {
344 OutStreamer->SwitchSection(
345 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
347 for (size_t i = 0; i < DisasmLines.size(); ++i) {
348 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
349 Comment += " ; " + HexLines[i] + "\n";
351 OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
352 OutStreamer->EmitBytes(StringRef(Comment));
359 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
361 bool killPixel = false;
362 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
363 const R600RegisterInfo *RI = STM.getRegisterInfo();
364 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
366 for (const MachineBasicBlock &MBB : MF) {
367 for (const MachineInstr &MI : MBB) {
368 if (MI.getOpcode() == AMDGPU::KILLGT)
370 unsigned numOperands = MI.getNumOperands();
371 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
372 const MachineOperand &MO = MI.getOperand(op_idx);
375 unsigned HWReg = RI->getHWRegIndex(MO.getReg());
377 // Register with value > 127 aren't GPR
380 MaxGPR = std::max(MaxGPR, HWReg);
386 if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
387 // Evergreen / Northern Islands
388 switch (MF.getFunction()->getCallingConv()) {
389 default: LLVM_FALLTHROUGH;
390 case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
391 case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
392 case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
393 case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
397 switch (MF.getFunction()->getCallingConv()) {
398 default: LLVM_FALLTHROUGH;
399 case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
400 case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
401 case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
402 case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
406 OutStreamer->EmitIntValue(RsrcReg, 4);
407 OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
408 S_STACK_SIZE(MFI->CFStackSize), 4);
409 OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
410 OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
412 if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
413 OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
414 OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
418 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
419 const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
420 const SIInstrInfo *TII = STM.getInstrInfo();
422 uint64_t CodeSize = 0;
424 for (const MachineBasicBlock &MBB : MF) {
425 for (const MachineInstr &MI : MBB) {
426 // TODO: CodeSize should account for multiple functions.
428 // TODO: Should we count size of debug info?
429 if (MI.isDebugValue())
432 CodeSize += TII->getInstSizeInBytes(MI);
439 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
440 const SIInstrInfo &TII,
442 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
443 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
450 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
453 unsigned ExtraSGPRs = 0;
457 if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
461 if (ST.isXNACKEnabled())
471 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
472 const SISubtarget &ST) const {
473 return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
476 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
477 const MachineFunction &MF) const {
478 SIFunctionResourceInfo Info;
480 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
481 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
482 const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
483 const MachineRegisterInfo &MRI = MF.getRegInfo();
484 const SIInstrInfo *TII = ST.getInstrInfo();
485 const SIRegisterInfo &TRI = TII->getRegisterInfo();
487 Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
488 MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
490 // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
491 // instructions aren't used to access the scratch buffer. Inline assembly may
494 // If we only have implicit uses of flat_scr on flat instructions, it is not
496 if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
497 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
498 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
499 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
500 Info.UsesFlatScratch = false;
503 Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
504 Info.PrivateSegmentSize = FrameInfo.getStackSize();
506 if (!FrameInfo.hasCalls()) {
507 Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
508 MRI.isPhysRegUsed(AMDGPU::VCC_HI);
510 // If there are no calls, MachineRegisterInfo can tell us the used register
513 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
514 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
515 if (MRI.isPhysRegUsed(Reg)) {
516 HighestVGPRReg = Reg;
521 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
522 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
523 if (MRI.isPhysRegUsed(Reg)) {
524 HighestSGPRReg = Reg;
529 // We found the maximum register index. They start at 0, so add one to get the
530 // number of registers.
531 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
532 TRI.getHWRegIndex(HighestVGPRReg) + 1;
533 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
534 TRI.getHWRegIndex(HighestSGPRReg) + 1;
539 llvm_unreachable("calls not implemented");
542 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
543 const MachineFunction &MF) {
544 SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
546 ProgInfo.NumVGPR = Info.NumVGPR;
547 ProgInfo.NumSGPR = Info.NumExplicitSGPR;
548 ProgInfo.ScratchSize = Info.PrivateSegmentSize;
549 ProgInfo.VCCUsed = Info.UsesVCC;
550 ProgInfo.FlatUsed = Info.UsesFlatScratch;
551 ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
553 const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
554 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
555 const SIInstrInfo *TII = STM.getInstrInfo();
556 const SIRegisterInfo *RI = &TII->getRegisterInfo();
558 unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
561 unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
563 // Check the addressable register limit before we add ExtraSGPRs.
564 if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
565 !STM.hasSGPRInitBug()) {
566 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
567 if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
568 // This can happen due to a compiler bug or when using inline asm.
569 LLVMContext &Ctx = MF.getFunction()->getContext();
570 DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
571 "addressable scalar registers",
572 ProgInfo.NumSGPR, DS_Error,
574 MaxAddressableNumSGPRs);
576 ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
580 // Account for extra SGPRs and VGPRs reserved for debugger use.
581 ProgInfo.NumSGPR += ExtraSGPRs;
582 ProgInfo.NumVGPR += ExtraVGPRs;
584 // Adjust number of registers used to meet default/requested minimum/maximum
585 // number of waves per execution unit request.
586 ProgInfo.NumSGPRsForWavesPerEU = std::max(
587 std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
588 ProgInfo.NumVGPRsForWavesPerEU = std::max(
589 std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
591 if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
592 STM.hasSGPRInitBug()) {
593 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
594 if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
595 // This can happen due to a compiler bug or when using inline asm to use
596 // the registers which are usually reserved for vcc etc.
597 LLVMContext &Ctx = MF.getFunction()->getContext();
598 DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
600 ProgInfo.NumSGPR, DS_Error,
602 MaxAddressableNumSGPRs);
604 ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
605 ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
609 if (STM.hasSGPRInitBug()) {
611 AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
612 ProgInfo.NumSGPRsForWavesPerEU =
613 AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
616 if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
617 LLVMContext &Ctx = MF.getFunction()->getContext();
618 DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
619 MFI->getNumUserSGPRs(), DS_Error);
623 if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
624 LLVMContext &Ctx = MF.getFunction()->getContext();
625 DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
626 MFI->getLDSSize(), DS_Error);
630 // SGPRBlocks is actual number of SGPR blocks minus 1.
631 ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
632 STM.getSGPREncodingGranule());
633 ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
635 // VGPRBlocks is actual number of VGPR blocks minus 1.
636 ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
637 STM.getVGPREncodingGranule());
638 ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
640 // Record first reserved VGPR and number of reserved VGPRs.
641 ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
642 ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
644 // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
645 // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
646 // attribute was requested.
647 if (STM.debuggerEmitPrologue()) {
648 ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
649 RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
650 ProgInfo.DebuggerPrivateSegmentBufferSGPR =
651 RI->getHWRegIndex(MFI->getScratchRSrcReg());
654 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
656 ProgInfo.FloatMode = getFPMode(MF);
658 ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
660 // Make clamp modifier on NaN input returns 0.
661 ProgInfo.DX10Clamp = STM.enableDX10Clamp();
663 unsigned LDSAlignShift;
664 if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
665 // LDS is allocated in 64 dword blocks.
668 // LDS is allocated in 128 dword blocks.
672 unsigned LDSSpillSize =
673 MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
675 ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
677 alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
679 // Scratch is allocated in 256 dword blocks.
680 unsigned ScratchAlignShift = 10;
681 // We need to program the hardware with the amount of scratch memory that
682 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
683 // scratch memory used per thread.
684 ProgInfo.ScratchBlocks =
685 alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
686 1ULL << ScratchAlignShift) >>
689 ProgInfo.ComputePGMRSrc1 =
690 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
691 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
692 S_00B848_PRIORITY(ProgInfo.Priority) |
693 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
694 S_00B848_PRIV(ProgInfo.Priv) |
695 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
696 S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
697 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
699 // 0 = X, 1 = XY, 2 = XYZ
700 unsigned TIDIGCompCnt = 0;
701 if (MFI->hasWorkItemIDZ())
703 else if (MFI->hasWorkItemIDY())
706 ProgInfo.ComputePGMRSrc2 =
707 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
708 S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
709 S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
710 S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
711 S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
712 S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
713 S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
714 S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
715 S_00B84C_EXCP_EN_MSB(0) |
716 // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
717 S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
721 static unsigned getRsrcReg(CallingConv::ID CallConv) {
723 default: LLVM_FALLTHROUGH;
724 case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
725 case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
726 case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
727 case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
728 case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
732 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
733 const SIProgramInfo &CurrentProgramInfo) {
734 const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
735 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
736 unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
738 if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
739 OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
741 OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
743 OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
744 OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
746 OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
747 OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
749 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
750 // 0" comment but I don't see a corresponding field in the register spec.
752 OutStreamer->EmitIntValue(RsrcReg, 4);
753 OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
754 S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
755 if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
756 OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
757 OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
761 if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
762 OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
763 OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
764 OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
765 OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
766 OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
767 OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
770 OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
771 OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
772 OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
773 OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
776 // This is supposed to be log2(Size)
777 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
780 return AMD_ELEMENT_4_BYTES;
782 return AMD_ELEMENT_8_BYTES;
784 return AMD_ELEMENT_16_BYTES;
786 llvm_unreachable("invalid private_element_size");
790 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
791 const SIProgramInfo &CurrentProgramInfo,
792 const MachineFunction &MF) const {
793 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
794 const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
796 AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
798 Out.compute_pgm_resource_registers =
799 CurrentProgramInfo.ComputePGMRSrc1 |
800 (CurrentProgramInfo.ComputePGMRSrc2 << 32);
801 Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
803 if (CurrentProgramInfo.DynamicCallStack)
804 Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
806 AMD_HSA_BITS_SET(Out.code_properties,
807 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
808 getElementByteSizeValue(STM.getMaxPrivateElementSize()));
810 if (MFI->hasPrivateSegmentBuffer()) {
811 Out.code_properties |=
812 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
815 if (MFI->hasDispatchPtr())
816 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
818 if (MFI->hasQueuePtr())
819 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
821 if (MFI->hasKernargSegmentPtr())
822 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
824 if (MFI->hasDispatchID())
825 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
827 if (MFI->hasFlatScratchInit())
828 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
830 if (MFI->hasGridWorkgroupCountX()) {
831 Out.code_properties |=
832 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
835 if (MFI->hasGridWorkgroupCountY()) {
836 Out.code_properties |=
837 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
840 if (MFI->hasGridWorkgroupCountZ()) {
841 Out.code_properties |=
842 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
845 if (MFI->hasDispatchPtr())
846 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
848 if (STM.debuggerSupported())
849 Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
851 if (STM.isXNACKEnabled())
852 Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
854 // FIXME: Should use getKernArgSize
855 Out.kernarg_segment_byte_size =
856 STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
857 Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
858 Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
859 Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
860 Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
861 Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
862 Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
864 // These alignment values are specified in powers of two, so alignment =
865 // 2^n. The minimum alignment is 2^4 = 16.
866 Out.kernarg_segment_alignment = std::max((size_t)4,
867 countTrailingZeros(MFI->getMaxKernArgAlign()));
869 if (STM.debuggerEmitPrologue()) {
870 Out.debug_wavefront_private_segment_offset_sgpr =
871 CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
872 Out.debug_private_segment_buffer_sgpr =
873 CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
877 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
879 const char *ExtraCode, raw_ostream &O) {
880 if (ExtraCode && ExtraCode[0]) {
881 if (ExtraCode[1] != 0)
882 return true; // Unknown modifier.
884 switch (ExtraCode[0]) {
886 // See if this is a generic print operand
887 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
893 AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
894 *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());