1 //===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief AMDGPU Assembly printer class.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
18 #include "AMDGPUMCInstLower.h"
20 #include "llvm/CodeGen/AsmPrinter.h"
26 class AMDGPUAsmPrinter final : public AsmPrinter {
28 struct SIProgramInfo {
46 NumSGPRsForWavesPerEU(0),
47 NumVGPRsForWavesPerEU(0),
50 DebuggerWavefrontPrivateSegmentOffsetSGPR((uint16_t)-1),
51 DebuggerPrivateSegmentBufferSGPR((uint16_t)-1),
55 // Fields set in PGM_RSRC1 pm4 packet.
66 uint64_t ComputePGMRSrc1;
68 // Fields set in PGM_RSRC2 pm4 packet.
70 uint32_t ScratchBlocks;
72 uint64_t ComputePGMRSrc2;
79 // Number of SGPRs that meets number of waves per execution unit request.
80 uint32_t NumSGPRsForWavesPerEU;
82 // Number of VGPRs that meets number of waves per execution unit request.
83 uint32_t NumVGPRsForWavesPerEU;
85 // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first
86 // fixed VGPR number reserved.
87 uint16_t ReservedVGPRFirst;
89 // The number of consecutive VGPRs reserved.
90 uint16_t ReservedVGPRCount;
92 // Fixed SGPR number used to hold wave scratch offset for entire kernel
93 // execution, or uint16_t(-1) if the register is not used or not known.
94 uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR;
96 // Fixed SGPR number of the first 4 SGPRs used to hold scratch V# for entire
97 // kernel execution, or uint16_t(-1) if the register is not used or not
99 uint16_t DebuggerPrivateSegmentBufferSGPR;
101 // Bonus information for debugging.
106 void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF) const;
107 void findNumUsedRegistersSI(const MachineFunction &MF,
109 unsigned &NumVGPR) const;
111 /// \brief Emit register usage information so that the GPU driver
112 /// can correctly setup the GPU state.
113 void EmitProgramInfoR600(const MachineFunction &MF);
114 void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
115 void EmitAmdKernelCodeT(const MachineFunction &MF,
116 const SIProgramInfo &KernelInfo) const;
119 explicit AMDGPUAsmPrinter(TargetMachine &TM,
120 std::unique_ptr<MCStreamer> Streamer);
122 bool runOnMachineFunction(MachineFunction &MF) override;
124 StringRef getPassName() const override;
126 /// \brief Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated
128 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
130 /// \brief tblgen'erated driver function for lowering simple MI->MC pseudo
132 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
133 const MachineInstr *MI);
135 /// Implemented in AMDGPUMCInstLower.cpp
136 void EmitInstruction(const MachineInstr *MI) override;
138 void EmitFunctionBodyStart() override;
140 void EmitFunctionEntryLabel() override;
142 void EmitGlobalVariable(const GlobalVariable *GV) override;
144 void EmitStartOfAsmFile(Module &M) override;
146 bool isBlockOnlyReachableByFallthrough(
147 const MachineBasicBlock *MBB) const override;
149 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
150 unsigned AsmVariant, const char *ExtraCode,
151 raw_ostream &O) override;
154 std::vector<std::string> DisasmLines, HexLines;
155 size_t DisasmLineMaxLen;
158 } // End anonymous llvm