1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h" // For AMDGPUISD
17 #include "AMDGPUInstrInfo.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "SIRegisterInfo.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/Analysis/ValueTracking.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/MachineValueType.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/ValueTypes.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/Instruction.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
56 } // end namespace llvm
58 //===----------------------------------------------------------------------===//
59 // Instruction Selector Implementation
60 //===----------------------------------------------------------------------===//
64 /// AMDGPU specific code to select AMDGPU machine instructions for
65 /// SelectionDAG operations.
66 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
67 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
68 // make the right decision when generating code for different targets.
69 const AMDGPUSubtarget *Subtarget;
73 explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
74 : SelectionDAGISel(TM, OptLevel){
75 AMDGPUASI = AMDGPU::getAMDGPUAS(TM);
77 ~AMDGPUDAGToDAGISel() override = default;
79 bool runOnMachineFunction(MachineFunction &MF) override;
80 void Select(SDNode *N) override;
81 StringRef getPassName() const override;
82 void PostprocessISelDAG() override;
85 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
86 bool isNoNanSrc(SDValue N) const;
87 bool isInlineImmediate(const SDNode *N) const;
88 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
89 const R600InstrInfo *TII);
90 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
91 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
93 bool isConstantLoad(const MemSDNode *N, int cbID) const;
94 bool isUniformBr(const SDNode *N) const;
96 SDNode *glueCopyToM0(SDNode *N) const;
98 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
99 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
100 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
102 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
103 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
104 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
105 unsigned OffsetBits) const;
106 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
107 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
108 SDValue &Offset1) const;
109 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
110 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
111 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
113 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
114 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
115 SDValue &SLC, SDValue &TFE) const;
116 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
117 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
119 bool SelectMUBUFScratchOffen(SDNode *Root,
120 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
121 SDValue &SOffset, SDValue &ImmOffset) const;
122 bool SelectMUBUFScratchOffset(SDNode *Root,
123 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
124 SDValue &Offset) const;
126 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
127 SDValue &Offset, SDValue &GLC, SDValue &SLC,
129 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
130 SDValue &Offset, SDValue &SLC) const;
131 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
132 SDValue &Offset) const;
133 bool SelectMUBUFConstant(SDValue Constant,
135 SDValue &ImmOffset) const;
136 bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
137 SDValue &ImmOffset) const;
138 bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
139 SDValue &ImmOffset, SDValue &VOffset) const;
141 bool SelectFlatAtomic(SDValue Addr, SDValue &VAddr,
142 SDValue &Offset, SDValue &SLC) const;
143 bool SelectFlatOffset(SDValue Addr, SDValue &VAddr,
144 SDValue &Offset, SDValue &SLC) const;
146 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
148 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
150 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
151 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
152 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
153 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
154 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
155 bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
156 bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
158 bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
159 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
160 bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
161 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
162 SDValue &Clamp, SDValue &Omod) const;
163 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
164 SDValue &Clamp, SDValue &Omod) const;
166 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
168 SDValue &Omod) const;
170 bool SelectVOP3OMods(SDValue In, SDValue &Src,
171 SDValue &Clamp, SDValue &Omod) const;
173 bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
174 bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
175 SDValue &Clamp) const;
177 void SelectADD_SUB_I64(SDNode *N);
178 void SelectUADDO_USUBO(SDNode *N);
179 void SelectDIV_SCALE(SDNode *N);
180 void SelectFMA_W_CHAIN(SDNode *N);
181 void SelectFMUL_W_CHAIN(SDNode *N);
183 SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
184 uint32_t Offset, uint32_t Width);
185 void SelectS_BFEFromShifts(SDNode *N);
186 void SelectS_BFE(SDNode *N);
187 bool isCBranchSCC(const SDNode *N) const;
188 void SelectBRCOND(SDNode *N);
189 void SelectATOMIC_CMP_SWAP(SDNode *N);
191 // Include the pieces autogenerated from the target description.
192 #include "AMDGPUGenDAGISel.inc"
195 } // end anonymous namespace
197 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
198 // DAG, ready for instruction scheduling.
199 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
200 CodeGenOpt::Level OptLevel) {
201 return new AMDGPUDAGToDAGISel(TM, OptLevel);
204 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
205 Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
206 return SelectionDAGISel::runOnMachineFunction(MF);
209 bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const {
210 if (TM.Options.NoNaNsFPMath)
213 // TODO: Move into isKnownNeverNaN
214 if (N->getFlags().isDefined())
215 return N->getFlags().hasNoNaNs();
217 return CurDAG->isKnownNeverNaN(N);
220 bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
221 const SIInstrInfo *TII
222 = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
224 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
225 return TII->isInlineConstant(C->getAPIntValue());
227 if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
228 return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
233 /// \brief Determine the register class for \p OpNo
234 /// \returns The register class of the virtual register that will be used for
235 /// the given operand number \OpNo or NULL if the register class cannot be
237 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
238 unsigned OpNo) const {
239 if (!N->isMachineOpcode()) {
240 if (N->getOpcode() == ISD::CopyToReg) {
241 unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
242 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
243 MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
244 return MRI.getRegClass(Reg);
247 const SIRegisterInfo *TRI
248 = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
249 return TRI->getPhysRegClass(Reg);
255 switch (N->getMachineOpcode()) {
257 const MCInstrDesc &Desc =
258 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
259 unsigned OpIdx = Desc.getNumDefs() + OpNo;
260 if (OpIdx >= Desc.getNumOperands())
262 int RegClass = Desc.OpInfo[OpIdx].RegClass;
266 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
268 case AMDGPU::REG_SEQUENCE: {
269 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
270 const TargetRegisterClass *SuperRC =
271 Subtarget->getRegisterInfo()->getRegClass(RCID);
273 SDValue SubRegOp = N->getOperand(OpNo + 1);
274 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
275 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
281 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
282 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
283 cast<MemSDNode>(N)->getAddressSpace() != AMDGPUASI.LOCAL_ADDRESS)
286 const SITargetLowering& Lowering =
287 *static_cast<const SITargetLowering*>(getTargetLowering());
289 // Write max value to m0 before each load operation
291 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
292 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
294 SDValue Glue = M0.getValue(1);
296 SmallVector <SDValue, 8> Ops;
297 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
298 Ops.push_back(N->getOperand(i));
301 CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
306 static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
307 switch (NumVectorElts) {
309 return AMDGPU::SReg_32_XM0RegClassID;
311 return AMDGPU::SReg_64RegClassID;
313 return AMDGPU::SReg_128RegClassID;
315 return AMDGPU::SReg_256RegClassID;
317 return AMDGPU::SReg_512RegClassID;
320 llvm_unreachable("invalid vector size");
323 static bool getConstantValue(SDValue N, uint32_t &Out) {
324 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
325 Out = C->getAPIntValue().getZExtValue();
329 if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) {
330 Out = C->getValueAPF().bitcastToAPInt().getZExtValue();
337 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
338 unsigned int Opc = N->getOpcode();
339 if (N->isMachineOpcode()) {
341 return; // Already selected.
344 if (isa<AtomicSDNode>(N) ||
345 (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC))
350 // We are selecting i64 ADD here instead of custom lower it during
351 // DAG legalization, so we can fold some i64 ADDs used for address
352 // calculation into the LOAD and STORE instructions.
359 if (N->getValueType(0) != MVT::i64 ||
360 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
363 SelectADD_SUB_I64(N);
368 SelectUADDO_USUBO(N);
371 case AMDGPUISD::FMUL_W_CHAIN: {
372 SelectFMUL_W_CHAIN(N);
375 case AMDGPUISD::FMA_W_CHAIN: {
376 SelectFMA_W_CHAIN(N);
380 case ISD::SCALAR_TO_VECTOR:
381 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
382 case ISD::BUILD_VECTOR: {
384 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
385 EVT VT = N->getValueType(0);
386 unsigned NumVectorElts = VT.getVectorNumElements();
387 EVT EltVT = VT.getVectorElementType();
389 if (VT == MVT::v2i16 || VT == MVT::v2f16) {
390 if (Opc == ISD::BUILD_VECTOR) {
391 uint32_t LHSVal, RHSVal;
392 if (getConstantValue(N->getOperand(0), LHSVal) &&
393 getConstantValue(N->getOperand(1), RHSVal)) {
394 uint32_t K = LHSVal | (RHSVal << 16);
395 CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, VT,
396 CurDAG->getTargetConstant(K, SDLoc(N), MVT::i32));
404 assert(EltVT.bitsEq(MVT::i32));
406 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
407 RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
409 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
410 // that adds a 128 bits reg copy when going through TwoAddressInstructions
411 // pass. We want to avoid 128 bits copies as much as possible because they
412 // can't be bundled by our scheduler.
413 switch(NumVectorElts) {
414 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
416 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
417 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
419 RegClassID = AMDGPU::R600_Reg128RegClassID;
421 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
426 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
428 if (NumVectorElts == 1) {
429 CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
434 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
436 // 16 = Max Num Vector Elements
437 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
438 // 1 = Vector Register Class
439 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
441 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
442 bool IsRegSeq = true;
443 unsigned NOps = N->getNumOperands();
444 for (unsigned i = 0; i < NOps; i++) {
445 // XXX: Why is this here?
446 if (isa<RegisterSDNode>(N->getOperand(i))) {
450 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
451 RegSeqArgs[1 + (2 * i) + 1] =
452 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
456 if (NOps != NumVectorElts) {
457 // Fill in the missing undef elements if this was a scalar_to_vector.
458 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
460 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
462 for (unsigned i = NOps; i < NumVectorElts; ++i) {
463 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
464 RegSeqArgs[1 + (2 * i) + 1] =
465 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
471 CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
474 case ISD::BUILD_PAIR: {
475 SDValue RC, SubReg0, SubReg1;
476 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
480 if (N->getValueType(0) == MVT::i128) {
481 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
482 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
483 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
484 } else if (N->getValueType(0) == MVT::i64) {
485 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
486 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
487 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
489 llvm_unreachable("Unhandled value type for BUILD_PAIR");
491 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
492 N->getOperand(1), SubReg1 };
493 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
494 N->getValueType(0), Ops));
499 case ISD::ConstantFP: {
500 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
501 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
505 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
506 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
508 ConstantSDNode *C = cast<ConstantSDNode>(N);
509 Imm = C->getZExtValue();
513 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
514 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
516 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
517 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
518 const SDValue Ops[] = {
519 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
520 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
521 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
524 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
525 N->getValueType(0), Ops));
534 case AMDGPUISD::BFE_I32:
535 case AMDGPUISD::BFE_U32: {
536 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
539 // There is a scalar version available, but unlike the vector version which
540 // has a separate operand for the offset and width, the scalar version packs
541 // the width and offset into a single operand. Try to move to the scalar
542 // version if the offsets are constant, so that we can try to keep extended
543 // loads of kernel arguments in SGPRs.
545 // TODO: Technically we could try to pattern match scalar bitshifts of
546 // dynamic values, but it's probably not useful.
547 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
551 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
555 bool Signed = Opc == AMDGPUISD::BFE_I32;
557 uint32_t OffsetVal = Offset->getZExtValue();
558 uint32_t WidthVal = Width->getZExtValue();
560 ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
561 SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
564 case AMDGPUISD::DIV_SCALE: {
568 case ISD::CopyToReg: {
569 const SITargetLowering& Lowering =
570 *static_cast<const SITargetLowering*>(getTargetLowering());
571 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG);
577 case ISD::SIGN_EXTEND_INREG:
578 if (N->getValueType(0) != MVT::i32 ||
579 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
588 case AMDGPUISD::ATOMIC_CMP_SWAP:
589 SelectATOMIC_CMP_SWAP(N);
596 bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
600 return N->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS;
602 return N->getAddressSpace() == AMDGPUASI.CONSTANT_BUFFER_0 + CbId;
605 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
606 const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
607 const Instruction *Term = BB->getTerminator();
608 return Term->getMetadata("amdgpu.uniform") ||
609 Term->getMetadata("structurizecfg.uniform");
612 StringRef AMDGPUDAGToDAGISel::getPassName() const {
613 return "AMDGPU DAG->DAG Pattern Instruction Selection";
616 //===----------------------------------------------------------------------===//
618 //===----------------------------------------------------------------------===//
620 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
622 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
623 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
630 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
631 SDValue& BaseReg, SDValue &Offset) {
632 if (!isa<ConstantSDNode>(Addr)) {
634 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
640 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
642 ConstantSDNode *IMMOffset;
644 if (Addr.getOpcode() == ISD::ADD
645 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
646 && isInt<16>(IMMOffset->getZExtValue())) {
648 Base = Addr.getOperand(0);
649 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
652 // If the pointer address is constant, we can move it to the offset field.
653 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
654 && isInt<16>(IMMOffset->getZExtValue())) {
655 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
656 SDLoc(CurDAG->getEntryNode()),
657 AMDGPU::ZERO, MVT::i32);
658 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
663 // Default case, no offset
665 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
669 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
674 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
675 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
676 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
677 } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
678 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
679 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
680 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
681 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
682 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
683 Base = Addr.getOperand(0);
684 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
687 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
693 void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
695 SDValue LHS = N->getOperand(0);
696 SDValue RHS = N->getOperand(1);
698 unsigned Opcode = N->getOpcode();
699 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
701 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
703 (Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE);
705 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
706 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
708 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
709 DL, MVT::i32, LHS, Sub0);
710 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
711 DL, MVT::i32, LHS, Sub1);
713 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
714 DL, MVT::i32, RHS, Sub0);
715 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
716 DL, MVT::i32, RHS, Sub1);
718 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
720 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
721 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
725 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
726 AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
728 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
729 AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
731 SDValue AddHiArgs[] = {
736 SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
738 SDValue RegSequenceArgs[] = {
739 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
745 SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
746 MVT::i64, RegSequenceArgs);
749 // Replace the carry-use
750 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1));
753 // Replace the remaining uses.
754 CurDAG->ReplaceAllUsesWith(N, RegSequence);
755 CurDAG->RemoveDeadNode(N);
758 void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
759 // The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
760 // carry out despite the _i32 name. These were renamed in VI to _U32.
761 // FIXME: We should probably rename the opcodes here.
762 unsigned Opc = N->getOpcode() == ISD::UADDO ?
763 AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
765 CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
766 { N->getOperand(0), N->getOperand(1) });
769 void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
771 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
774 SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
775 SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
776 SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
777 Ops[8] = N->getOperand(0);
778 Ops[9] = N->getOperand(4);
780 CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops);
783 void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
785 // src0_modifiers, src0, src1_modifiers, src1, clamp, omod
788 SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
789 SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
790 Ops[6] = N->getOperand(0);
791 Ops[7] = N->getOperand(3);
793 CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
796 // We need to handle this here because tablegen doesn't support matching
797 // instructions with multiple outputs.
798 void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
800 EVT VT = N->getValueType(0);
802 assert(VT == MVT::f32 || VT == MVT::f64);
805 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
807 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
808 CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
811 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
812 unsigned OffsetBits) const {
813 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
814 (OffsetBits == 8 && !isUInt<8>(Offset)))
817 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
818 Subtarget->unsafeDSOffsetFoldingEnabled())
821 // On Southern Islands instruction with a negative base value and an offset
822 // don't seem to work.
823 return CurDAG->SignBitIsZero(Base);
826 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
827 SDValue &Offset) const {
829 if (CurDAG->isBaseWithConstantOffset(Addr)) {
830 SDValue N0 = Addr.getOperand(0);
831 SDValue N1 = Addr.getOperand(1);
832 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
833 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
836 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
839 } else if (Addr.getOpcode() == ISD::SUB) {
840 // sub C, x -> add (sub 0, x), C
841 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
842 int64_t ByteOffset = C->getSExtValue();
843 if (isUInt<16>(ByteOffset)) {
844 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
846 // XXX - This is kind of hacky. Create a dummy sub node so we can check
847 // the known bits in isDSOffsetLegal. We need to emit the selected node
848 // here, so this is thrown away.
849 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
850 Zero, Addr.getOperand(1));
852 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
853 MachineSDNode *MachineSub
854 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
855 Zero, Addr.getOperand(1));
857 Base = SDValue(MachineSub, 0);
858 Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
863 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
864 // If we have a constant address, prefer to put the constant into the
865 // offset. This can save moves to load the constant address since multiple
866 // operations can share the zero base address register, and enables merging
867 // into read2 / write2 instructions.
871 if (isUInt<16>(CAddr->getZExtValue())) {
872 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
873 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
875 Base = SDValue(MovZero, 0);
876 Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
883 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
887 // TODO: If offset is too big, put low 16-bit into offset.
888 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
890 SDValue &Offset1) const {
893 if (CurDAG->isBaseWithConstantOffset(Addr)) {
894 SDValue N0 = Addr.getOperand(0);
895 SDValue N1 = Addr.getOperand(1);
896 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
897 unsigned DWordOffset0 = C1->getZExtValue() / 4;
898 unsigned DWordOffset1 = DWordOffset0 + 1;
900 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
902 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
903 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
906 } else if (Addr.getOpcode() == ISD::SUB) {
907 // sub C, x -> add (sub 0, x), C
908 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
909 unsigned DWordOffset0 = C->getZExtValue() / 4;
910 unsigned DWordOffset1 = DWordOffset0 + 1;
912 if (isUInt<8>(DWordOffset0)) {
914 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
916 // XXX - This is kind of hacky. Create a dummy sub node so we can check
917 // the known bits in isDSOffsetLegal. We need to emit the selected node
918 // here, so this is thrown away.
919 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
920 Zero, Addr.getOperand(1));
922 if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
923 MachineSDNode *MachineSub
924 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
925 Zero, Addr.getOperand(1));
927 Base = SDValue(MachineSub, 0);
928 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
929 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
934 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
935 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
936 unsigned DWordOffset1 = DWordOffset0 + 1;
937 assert(4 * DWordOffset0 == CAddr->getZExtValue());
939 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
940 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
941 MachineSDNode *MovZero
942 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
944 Base = SDValue(MovZero, 0);
945 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
946 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
953 // FIXME: This is broken on SI where we still need to check if the base
954 // pointer is positive here.
956 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
957 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
961 static bool isLegalMUBUFImmOffset(unsigned Imm) {
962 return isUInt<12>(Imm);
965 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
966 return isLegalMUBUFImmOffset(Imm->getZExtValue());
969 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
970 SDValue &VAddr, SDValue &SOffset,
971 SDValue &Offset, SDValue &Offen,
972 SDValue &Idxen, SDValue &Addr64,
973 SDValue &GLC, SDValue &SLC,
974 SDValue &TFE) const {
975 // Subtarget prefers to use flat instruction
976 if (Subtarget->useFlatForGlobal())
982 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
984 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
985 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
987 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
988 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
989 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
990 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
992 if (CurDAG->isBaseWithConstantOffset(Addr)) {
993 SDValue N0 = Addr.getOperand(0);
994 SDValue N1 = Addr.getOperand(1);
995 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
997 if (N0.getOpcode() == ISD::ADD) {
998 // (add (add N2, N3), C1) -> addr64
999 SDValue N2 = N0.getOperand(0);
1000 SDValue N3 = N0.getOperand(1);
1001 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1005 // (add N0, C1) -> offset
1006 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1010 if (isLegalMUBUFImmOffset(C1)) {
1011 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1015 if (isUInt<32>(C1->getZExtValue())) {
1016 // Illegal offset, store it in soffset.
1017 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1018 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1019 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1025 if (Addr.getOpcode() == ISD::ADD) {
1026 // (add N0, N1) -> addr64
1027 SDValue N0 = Addr.getOperand(0);
1028 SDValue N1 = Addr.getOperand(1);
1029 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1032 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1036 // default case -> offset
1037 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1039 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1044 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1045 SDValue &VAddr, SDValue &SOffset,
1046 SDValue &Offset, SDValue &GLC,
1047 SDValue &SLC, SDValue &TFE) const {
1048 SDValue Ptr, Offen, Idxen, Addr64;
1050 // addr64 bit was removed for volcanic islands.
1051 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1054 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1058 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1059 if (C->getSExtValue()) {
1062 const SITargetLowering& Lowering =
1063 *static_cast<const SITargetLowering*>(getTargetLowering());
1065 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1072 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1073 SDValue &VAddr, SDValue &SOffset,
1075 SDValue &SLC) const {
1076 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1079 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1082 static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
1083 auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
1084 return PSV && PSV->isStack();
1087 std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
1088 const MachineFunction &MF = CurDAG->getMachineFunction();
1089 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1091 if (auto FI = dyn_cast<FrameIndexSDNode>(N)) {
1092 SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(),
1093 FI->getValueType(0));
1095 // If we can resolve this to a frame index access, this is relative to the
1096 // frame pointer SGPR.
1097 return std::make_pair(TFI, CurDAG->getRegister(Info->getFrameOffsetReg(),
1101 // If we don't know this private access is a local stack object, it needs to
1102 // be relative to the entry point's scratch wave offset register.
1103 return std::make_pair(N, CurDAG->getRegister(Info->getScratchWaveOffsetReg(),
1107 bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Root,
1108 SDValue Addr, SDValue &Rsrc,
1109 SDValue &VAddr, SDValue &SOffset,
1110 SDValue &ImmOffset) const {
1113 MachineFunction &MF = CurDAG->getMachineFunction();
1114 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1116 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1118 if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
1119 unsigned Imm = CAddr->getZExtValue();
1120 assert(!isLegalMUBUFImmOffset(Imm) &&
1121 "should have been selected by other pattern");
1123 SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
1124 MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1125 DL, MVT::i32, HighBits);
1126 VAddr = SDValue(MovHighBits, 0);
1128 // In a call sequence, stores to the argument stack area are relative to the
1130 const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Root)->getPointerInfo();
1131 unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
1132 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
1134 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
1135 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
1139 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1142 SDValue N0 = Addr.getOperand(0);
1143 SDValue N1 = Addr.getOperand(1);
1145 // Offsets in vaddr must be positive.
1146 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1147 if (isLegalMUBUFImmOffset(C1)) {
1148 std::tie(VAddr, SOffset) = foldFrameIndex(N0);
1149 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1155 std::tie(VAddr, SOffset) = foldFrameIndex(Addr);
1156 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1160 bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Root,
1164 SDValue &Offset) const {
1165 ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr);
1166 if (!CAddr || !isLegalMUBUFImmOffset(CAddr))
1170 MachineFunction &MF = CurDAG->getMachineFunction();
1171 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1173 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1175 const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Root)->getPointerInfo();
1176 unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
1177 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
1179 // FIXME: Get from MachinePointerInfo? We should only be using the frame
1180 // offset if we know this is in a call sequence.
1181 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
1183 Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
1187 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1188 SDValue &SOffset, SDValue &Offset,
1189 SDValue &GLC, SDValue &SLC,
1190 SDValue &TFE) const {
1191 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1192 const SIInstrInfo *TII =
1193 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1195 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1199 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1200 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1201 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1202 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1203 APInt::getAllOnesValue(32).getZExtValue(); // Size
1206 const SITargetLowering& Lowering =
1207 *static_cast<const SITargetLowering*>(getTargetLowering());
1209 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1215 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1216 SDValue &Soffset, SDValue &Offset
1218 SDValue GLC, SLC, TFE;
1220 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1222 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1223 SDValue &Soffset, SDValue &Offset,
1224 SDValue &SLC) const {
1227 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1230 bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
1232 SDValue &ImmOffset) const {
1234 uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
1235 uint32_t Overflow = 0;
1238 if (Imm <= 4095 + 64) {
1239 // Use an SOffset inline constant for 1..64
1240 Overflow = Imm - 4095;
1243 // Try to keep the same value in SOffset for adjacent loads, so that
1244 // the corresponding register contents can be re-used.
1246 // Load values with all low-bits set into SOffset, so that a larger
1247 // range of values can be covered using s_movk_i32
1248 uint32_t High = (Imm + 1) & ~4095;
1249 uint32_t Low = (Imm + 1) & 4095;
1251 Overflow = High - 1;
1255 // There is a hardware bug in SI and CI which prevents address clamping in
1256 // MUBUF instructions from working correctly with SOffsets. The immediate
1257 // offset is unaffected.
1259 Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1262 ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16);
1265 SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32);
1267 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1268 CurDAG->getTargetConstant(Overflow, DL, MVT::i32)),
1274 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
1276 SDValue &ImmOffset) const {
1279 if (!isa<ConstantSDNode>(Offset))
1282 return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
1285 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
1288 SDValue &VOffset) const {
1291 // Don't generate an unnecessary voffset for constant offsets.
1292 if (isa<ConstantSDNode>(Offset)) {
1295 // When necessary, use a voffset in <= CI anyway to work around a hardware
1297 if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS ||
1298 SelectMUBUFConstant(Offset, Tmp1, Tmp2))
1302 if (CurDAG->isBaseWithConstantOffset(Offset)) {
1303 SDValue N0 = Offset.getOperand(0);
1304 SDValue N1 = Offset.getOperand(1);
1305 if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
1306 SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
1312 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1313 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1319 bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDValue Addr,
1322 SDValue &SLC) const {
1323 int64_t OffsetVal = 0;
1325 if (Subtarget->hasFlatInstOffsets() &&
1326 CurDAG->isBaseWithConstantOffset(Addr)) {
1327 SDValue N0 = Addr.getOperand(0);
1328 SDValue N1 = Addr.getOperand(1);
1329 uint64_t COffsetVal = cast<ConstantSDNode>(N1)->getZExtValue();
1330 if (isUInt<12>(COffsetVal)) {
1332 OffsetVal = COffsetVal;
1337 Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
1338 SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
1343 bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDValue Addr,
1346 SDValue &SLC) const {
1347 return SelectFlatOffset(Addr, VAddr, Offset, SLC);
1350 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1351 SDValue &Offset, bool &Imm) const {
1353 // FIXME: Handle non-constant offsets.
1354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1358 SDLoc SL(ByteOffsetNode);
1359 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1360 int64_t ByteOffset = C->getSExtValue();
1361 int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
1363 if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) {
1364 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1369 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1372 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1373 // 32-bit Immediates are supported on Sea Islands.
1374 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1376 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1377 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1384 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1385 SDValue &Offset, bool &Imm) const {
1387 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1388 SDValue N0 = Addr.getOperand(0);
1389 SDValue N1 = Addr.getOperand(1);
1391 if (SelectSMRDOffset(N1, Offset, Imm)) {
1397 Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1402 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1403 SDValue &Offset) const {
1405 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1408 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1409 SDValue &Offset) const {
1411 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1415 if (!SelectSMRD(Addr, SBase, Offset, Imm))
1418 return !Imm && isa<ConstantSDNode>(Offset);
1421 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1422 SDValue &Offset) const {
1424 return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1425 !isa<ConstantSDNode>(Offset);
1428 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1429 SDValue &Offset) const {
1431 return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1434 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1435 SDValue &Offset) const {
1436 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1440 if (!SelectSMRDOffset(Addr, Offset, Imm))
1443 return !Imm && isa<ConstantSDNode>(Offset);
1446 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1447 SDValue &Offset) const {
1449 return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1450 !isa<ConstantSDNode>(Offset);
1453 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1455 SDValue &Offset) const {
1458 if (CurDAG->isBaseWithConstantOffset(Index)) {
1459 SDValue N0 = Index.getOperand(0);
1460 SDValue N1 = Index.getOperand(1);
1461 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1465 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
1469 if (isa<ConstantSDNode>(Index))
1473 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1477 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
1478 SDValue Val, uint32_t Offset,
1480 // Transformation function, pack the offset and width of a BFE into
1481 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1482 // source, bits [5:0] contain the offset and bits [22:16] the width.
1483 uint32_t PackedVal = Offset | (Width << 16);
1484 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1486 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1489 void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1490 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1491 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1492 // Predicate: 0 < b <= c < 32
1494 const SDValue &Shl = N->getOperand(0);
1495 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1499 uint32_t BVal = B->getZExtValue();
1500 uint32_t CVal = C->getZExtValue();
1502 if (0 < BVal && BVal <= CVal && CVal < 32) {
1503 bool Signed = N->getOpcode() == ISD::SRA;
1504 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1506 ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
1514 void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1515 switch (N->getOpcode()) {
1517 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1518 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1519 // Predicate: isMask(mask)
1520 const SDValue &Srl = N->getOperand(0);
1521 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1522 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1524 if (Shift && Mask) {
1525 uint32_t ShiftVal = Shift->getZExtValue();
1526 uint32_t MaskVal = Mask->getZExtValue();
1528 if (isMask_32(MaskVal)) {
1529 uint32_t WidthVal = countPopulation(MaskVal);
1531 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1532 Srl.getOperand(0), ShiftVal, WidthVal));
1539 if (N->getOperand(0).getOpcode() == ISD::AND) {
1540 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1541 // Predicate: isMask(mask >> b)
1542 const SDValue &And = N->getOperand(0);
1543 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1544 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1546 if (Shift && Mask) {
1547 uint32_t ShiftVal = Shift->getZExtValue();
1548 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1550 if (isMask_32(MaskVal)) {
1551 uint32_t WidthVal = countPopulation(MaskVal);
1553 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1554 And.getOperand(0), ShiftVal, WidthVal));
1558 } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1559 SelectS_BFEFromShifts(N);
1564 if (N->getOperand(0).getOpcode() == ISD::SHL) {
1565 SelectS_BFEFromShifts(N);
1570 case ISD::SIGN_EXTEND_INREG: {
1571 // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
1572 SDValue Src = N->getOperand(0);
1573 if (Src.getOpcode() != ISD::SRL)
1576 const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1580 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1581 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
1582 Amt->getZExtValue(), Width));
1590 bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
1591 assert(N->getOpcode() == ISD::BRCOND);
1592 if (!N->hasOneUse())
1595 SDValue Cond = N->getOperand(1);
1596 if (Cond.getOpcode() == ISD::CopyToReg)
1597 Cond = Cond.getOperand(2);
1599 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
1602 MVT VT = Cond.getOperand(0).getSimpleValueType();
1606 if (VT == MVT::i64) {
1607 auto ST = static_cast<const SISubtarget *>(Subtarget);
1609 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
1610 return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
1616 void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
1617 SDValue Cond = N->getOperand(1);
1619 if (Cond.isUndef()) {
1620 CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
1621 N->getOperand(2), N->getOperand(0));
1625 if (isCBranchSCC(N)) {
1626 // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
1633 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
1634 CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
1635 N->getOperand(2), // Basic Block
1639 // This is here because there isn't a way to use the generated sub0_sub1 as the
1640 // subreg index to EXTRACT_SUBREG in tablegen.
1641 void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
1642 MemSDNode *Mem = cast<MemSDNode>(N);
1643 unsigned AS = Mem->getAddressSpace();
1644 if (AS == AMDGPUASI.FLAT_ADDRESS) {
1649 MVT VT = N->getSimpleValueType(0);
1650 bool Is32 = (VT == MVT::i32);
1653 MachineSDNode *CmpSwap = nullptr;
1654 if (Subtarget->hasAddr64()) {
1655 SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC;
1657 if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
1658 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 :
1659 AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64;
1660 SDValue CmpVal = Mem->getOperand(2);
1662 // XXX - Do we care about glue operands?
1665 CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1668 CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1673 SDValue SRsrc, SOffset, Offset, SLC;
1674 if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
1675 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET :
1676 AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET;
1678 SDValue CmpVal = Mem->getOperand(2);
1680 CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1683 CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1692 MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
1693 *MMOs = Mem->getMemOperand();
1694 CmpSwap->setMemRefs(MMOs, MMOs + 1);
1696 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
1698 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
1700 ReplaceUses(SDValue(N, 0), Extract);
1701 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
1702 CurDAG->RemoveDeadNode(N);
1705 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1706 SDValue &SrcMods) const {
1710 if (Src.getOpcode() == ISD::FNEG) {
1711 Mods |= SISrcMods::NEG;
1712 Src = Src.getOperand(0);
1715 if (Src.getOpcode() == ISD::FABS) {
1716 Mods |= SISrcMods::ABS;
1717 Src = Src.getOperand(0);
1720 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1724 bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
1725 SDValue &SrcMods) const {
1726 SelectVOP3Mods(In, Src, SrcMods);
1727 return isNoNanSrc(Src);
1730 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const {
1731 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
1738 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1739 SDValue &SrcMods, SDValue &Clamp,
1740 SDValue &Omod) const {
1742 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
1743 Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
1745 return SelectVOP3Mods(In, Src, SrcMods);
1748 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1751 SDValue &Omod) const {
1752 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1753 return SelectVOP3Mods(In, Src, SrcMods);
1756 bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
1757 SDValue &Clamp, SDValue &Omod) const {
1761 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
1762 Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
1767 static SDValue stripBitcast(SDValue Val) {
1768 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
1771 // Figure out if this is really an extract of the high 16-bits of a dword.
1772 static bool isExtractHiElt(SDValue In, SDValue &Out) {
1773 In = stripBitcast(In);
1774 if (In.getOpcode() != ISD::TRUNCATE)
1777 SDValue Srl = In.getOperand(0);
1778 if (Srl.getOpcode() == ISD::SRL) {
1779 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
1780 if (ShiftAmt->getZExtValue() == 16) {
1781 Out = stripBitcast(Srl.getOperand(0));
1790 // Look through operations that obscure just looking at the low 16-bits of the
1792 static SDValue stripExtractLoElt(SDValue In) {
1793 if (In.getOpcode() == ISD::TRUNCATE) {
1794 SDValue Src = In.getOperand(0);
1795 if (Src.getValueType().getSizeInBits() == 32)
1796 return stripBitcast(Src);
1802 bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
1803 SDValue &SrcMods) const {
1807 if (Src.getOpcode() == ISD::FNEG) {
1808 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
1809 Src = Src.getOperand(0);
1812 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
1813 unsigned VecMods = Mods;
1815 SDValue Lo = stripBitcast(Src.getOperand(0));
1816 SDValue Hi = stripBitcast(Src.getOperand(1));
1818 if (Lo.getOpcode() == ISD::FNEG) {
1819 Lo = stripBitcast(Lo.getOperand(0));
1820 Mods ^= SISrcMods::NEG;
1823 if (Hi.getOpcode() == ISD::FNEG) {
1824 Hi = stripBitcast(Hi.getOperand(0));
1825 Mods ^= SISrcMods::NEG_HI;
1828 if (isExtractHiElt(Lo, Lo))
1829 Mods |= SISrcMods::OP_SEL_0;
1831 if (isExtractHiElt(Hi, Hi))
1832 Mods |= SISrcMods::OP_SEL_1;
1834 Lo = stripExtractLoElt(Lo);
1835 Hi = stripExtractLoElt(Hi);
1837 if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {
1838 // Really a scalar input. Just select from the low half of the register to
1842 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1849 // Packed instructions do not have abs modifiers.
1850 Mods |= SISrcMods::OP_SEL_1;
1852 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1856 bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src,
1858 SDValue &Clamp) const {
1861 // FIXME: Handle clamp and op_sel
1862 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1864 return SelectVOP3PMods(In, Src, SrcMods);
1867 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1868 const AMDGPUTargetLowering& Lowering =
1869 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1870 bool IsModified = false;
1873 // Go over all selected nodes and try to fold them a bit more
1874 for (SDNode &Node : CurDAG->allnodes()) {
1875 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1879 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1880 if (ResNode != &Node) {
1881 ReplaceUses(&Node, ResNode);
1885 CurDAG->RemoveDeadNodes();
1886 } while (IsModified);