1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUISelLowering.h" // For AMDGPUISD
18 #include "AMDGPUInstrInfo.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDGPUTargetMachine.h"
22 #include "SIDefines.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIRegisterInfo.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/Analysis/ValueTracking.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/ISDOpcodes.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/MachineValueType.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/SelectionDAGISel.h"
38 #include "llvm/CodeGen/SelectionDAGNodes.h"
39 #include "llvm/CodeGen/ValueTypes.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/MC/MCInstrDesc.h"
43 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/CodeGen.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/MathExtras.h"
58 } // end namespace llvm
60 //===----------------------------------------------------------------------===//
61 // Instruction Selector Implementation
62 //===----------------------------------------------------------------------===//
66 /// AMDGPU specific code to select AMDGPU machine instructions for
67 /// SelectionDAG operations.
68 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
69 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
70 // make the right decision when generating code for different targets.
71 const AMDGPUSubtarget *Subtarget;
73 bool EnableLateStructurizeCFG;
76 explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
77 CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
78 : SelectionDAGISel(*TM, OptLevel) {
79 AMDGPUASI = AMDGPU::getAMDGPUAS(*TM);
80 EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
82 ~AMDGPUDAGToDAGISel() override = default;
84 void getAnalysisUsage(AnalysisUsage &AU) const override {
85 AU.addRequired<AMDGPUArgumentUsageInfo>();
86 SelectionDAGISel::getAnalysisUsage(AU);
89 bool runOnMachineFunction(MachineFunction &MF) override;
90 void Select(SDNode *N) override;
91 StringRef getPassName() const override;
92 void PostprocessISelDAG() override;
95 void SelectBuildVector(SDNode *N, unsigned RegClassID);
98 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
99 bool isNoNanSrc(SDValue N) const;
100 bool isInlineImmediate(const SDNode *N) const;
101 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
102 const R600InstrInfo *TII);
103 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
104 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
106 bool isConstantLoad(const MemSDNode *N, int cbID) const;
107 bool isUniformBr(const SDNode *N) const;
109 SDNode *glueCopyToM0(SDNode *N) const;
111 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
112 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
113 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
115 virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
116 virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
117 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
118 unsigned OffsetBits) const;
119 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
120 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
121 SDValue &Offset1) const;
122 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
123 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
124 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
126 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
127 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
128 SDValue &SLC, SDValue &TFE) const;
129 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
130 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
132 bool SelectMUBUFScratchOffen(SDNode *Parent,
133 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
134 SDValue &SOffset, SDValue &ImmOffset) const;
135 bool SelectMUBUFScratchOffset(SDNode *Parent,
136 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
137 SDValue &Offset) const;
139 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
140 SDValue &Offset, SDValue &GLC, SDValue &SLC,
142 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
143 SDValue &Offset, SDValue &SLC) const;
144 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
145 SDValue &Offset) const;
146 bool SelectMUBUFConstant(SDValue Constant,
148 SDValue &ImmOffset) const;
149 bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
150 SDValue &ImmOffset) const;
151 bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
152 SDValue &ImmOffset, SDValue &VOffset) const;
154 bool SelectFlatAtomic(SDValue Addr, SDValue &VAddr,
155 SDValue &Offset, SDValue &SLC) const;
156 bool SelectFlatAtomicSigned(SDValue Addr, SDValue &VAddr,
157 SDValue &Offset, SDValue &SLC) const;
159 template <bool IsSigned>
160 bool SelectFlatOffset(SDValue Addr, SDValue &VAddr,
161 SDValue &Offset, SDValue &SLC) const;
163 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
165 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
167 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
168 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
169 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
170 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
171 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
172 bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
174 bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
175 bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const;
176 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
177 bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
178 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
179 SDValue &Clamp, SDValue &Omod) const;
180 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
181 SDValue &Clamp, SDValue &Omod) const;
183 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
185 SDValue &Omod) const;
187 bool SelectVOP3OMods(SDValue In, SDValue &Src,
188 SDValue &Clamp, SDValue &Omod) const;
190 bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
191 bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
192 SDValue &Clamp) const;
194 bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
195 bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods,
196 SDValue &Clamp) const;
198 bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
199 bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
200 SDValue &Clamp) const;
201 bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
202 bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
204 bool SelectHi16Elt(SDValue In, SDValue &Src) const;
206 void SelectADD_SUB_I64(SDNode *N);
207 void SelectUADDO_USUBO(SDNode *N);
208 void SelectDIV_SCALE(SDNode *N);
209 void SelectMAD_64_32(SDNode *N);
210 void SelectFMA_W_CHAIN(SDNode *N);
211 void SelectFMUL_W_CHAIN(SDNode *N);
213 SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
214 uint32_t Offset, uint32_t Width);
215 void SelectS_BFEFromShifts(SDNode *N);
216 void SelectS_BFE(SDNode *N);
217 bool isCBranchSCC(const SDNode *N) const;
218 void SelectBRCOND(SDNode *N);
219 void SelectFMAD(SDNode *N);
220 void SelectATOMIC_CMP_SWAP(SDNode *N);
223 // Include the pieces autogenerated from the target description.
224 #include "AMDGPUGenDAGISel.inc"
227 class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
229 explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) :
230 AMDGPUDAGToDAGISel(TM, OptLevel) {}
232 void Select(SDNode *N) override;
234 bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
235 SDValue &Offset) override;
236 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
237 SDValue &Offset) override;
240 } // end anonymous namespace
242 INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "isel",
243 "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
244 INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
245 INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel",
246 "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
248 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
249 // DAG, ready for instruction scheduling.
250 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
251 CodeGenOpt::Level OptLevel) {
252 return new AMDGPUDAGToDAGISel(TM, OptLevel);
255 /// \brief This pass converts a legalized DAG into a R600-specific
256 // DAG, ready for instruction scheduling.
257 FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
258 CodeGenOpt::Level OptLevel) {
259 return new R600DAGToDAGISel(TM, OptLevel);
262 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
263 Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
264 return SelectionDAGISel::runOnMachineFunction(MF);
267 bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const {
268 if (TM.Options.NoNaNsFPMath)
271 // TODO: Move into isKnownNeverNaN
272 if (N->getFlags().isDefined())
273 return N->getFlags().hasNoNaNs();
275 return CurDAG->isKnownNeverNaN(N);
278 bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
279 const SIInstrInfo *TII
280 = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
282 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
283 return TII->isInlineConstant(C->getAPIntValue());
285 if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
286 return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
291 /// \brief Determine the register class for \p OpNo
292 /// \returns The register class of the virtual register that will be used for
293 /// the given operand number \OpNo or NULL if the register class cannot be
295 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
296 unsigned OpNo) const {
297 if (!N->isMachineOpcode()) {
298 if (N->getOpcode() == ISD::CopyToReg) {
299 unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
300 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
301 MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
302 return MRI.getRegClass(Reg);
305 const SIRegisterInfo *TRI
306 = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
307 return TRI->getPhysRegClass(Reg);
313 switch (N->getMachineOpcode()) {
315 const MCInstrDesc &Desc =
316 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
317 unsigned OpIdx = Desc.getNumDefs() + OpNo;
318 if (OpIdx >= Desc.getNumOperands())
320 int RegClass = Desc.OpInfo[OpIdx].RegClass;
324 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
326 case AMDGPU::REG_SEQUENCE: {
327 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
328 const TargetRegisterClass *SuperRC =
329 Subtarget->getRegisterInfo()->getRegClass(RCID);
331 SDValue SubRegOp = N->getOperand(OpNo + 1);
332 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
333 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
339 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
340 if (cast<MemSDNode>(N)->getAddressSpace() != AMDGPUASI.LOCAL_ADDRESS ||
341 !Subtarget->ldsRequiresM0Init())
344 const SITargetLowering& Lowering =
345 *static_cast<const SITargetLowering*>(getTargetLowering());
347 // Write max value to m0 before each load operation
349 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
350 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
352 SDValue Glue = M0.getValue(1);
354 SmallVector <SDValue, 8> Ops;
355 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
356 Ops.push_back(N->getOperand(i));
359 return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
362 static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
363 switch (NumVectorElts) {
365 return AMDGPU::SReg_32_XM0RegClassID;
367 return AMDGPU::SReg_64RegClassID;
369 return AMDGPU::SReg_128RegClassID;
371 return AMDGPU::SReg_256RegClassID;
373 return AMDGPU::SReg_512RegClassID;
376 llvm_unreachable("invalid vector size");
379 static bool getConstantValue(SDValue N, uint32_t &Out) {
380 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
381 Out = C->getAPIntValue().getZExtValue();
385 if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) {
386 Out = C->getValueAPF().bitcastToAPInt().getZExtValue();
393 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
394 EVT VT = N->getValueType(0);
395 unsigned NumVectorElts = VT.getVectorNumElements();
396 EVT EltVT = VT.getVectorElementType();
397 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
399 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
401 if (NumVectorElts == 1) {
402 CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
407 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
409 // 16 = Max Num Vector Elements
410 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
411 // 1 = Vector Register Class
412 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
414 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
415 bool IsRegSeq = true;
416 unsigned NOps = N->getNumOperands();
417 for (unsigned i = 0; i < NOps; i++) {
418 // XXX: Why is this here?
419 if (isa<RegisterSDNode>(N->getOperand(i))) {
423 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
424 RegSeqArgs[1 + (2 * i) + 1] =
425 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
428 if (NOps != NumVectorElts) {
429 // Fill in the missing undef elements if this was a scalar_to_vector.
430 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
431 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
433 for (unsigned i = NOps; i < NumVectorElts; ++i) {
434 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
435 RegSeqArgs[1 + (2 * i) + 1] =
436 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
442 CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
445 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
446 unsigned int Opc = N->getOpcode();
447 if (N->isMachineOpcode()) {
449 return; // Already selected.
452 if (isa<AtomicSDNode>(N) ||
453 (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC))
459 // We are selecting i64 ADD here instead of custom lower it during
460 // DAG legalization, so we can fold some i64 ADDs used for address
461 // calculation into the LOAD and STORE instructions.
466 if (N->getValueType(0) != MVT::i64)
469 SelectADD_SUB_I64(N);
474 SelectUADDO_USUBO(N);
477 case AMDGPUISD::FMUL_W_CHAIN: {
478 SelectFMUL_W_CHAIN(N);
481 case AMDGPUISD::FMA_W_CHAIN: {
482 SelectFMA_W_CHAIN(N);
486 case ISD::SCALAR_TO_VECTOR:
487 case ISD::BUILD_VECTOR: {
488 EVT VT = N->getValueType(0);
489 unsigned NumVectorElts = VT.getVectorNumElements();
491 if (VT == MVT::v2i16 || VT == MVT::v2f16) {
492 if (Opc == ISD::BUILD_VECTOR) {
493 uint32_t LHSVal, RHSVal;
494 if (getConstantValue(N->getOperand(0), LHSVal) &&
495 getConstantValue(N->getOperand(1), RHSVal)) {
496 uint32_t K = LHSVal | (RHSVal << 16);
497 CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, VT,
498 CurDAG->getTargetConstant(K, SDLoc(N), MVT::i32));
506 assert(VT.getVectorElementType().bitsEq(MVT::i32));
507 unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
508 SelectBuildVector(N, RegClassID);
511 case ISD::BUILD_PAIR: {
512 SDValue RC, SubReg0, SubReg1;
514 if (N->getValueType(0) == MVT::i128) {
515 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
516 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
517 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
518 } else if (N->getValueType(0) == MVT::i64) {
519 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
520 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
521 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
523 llvm_unreachable("Unhandled value type for BUILD_PAIR");
525 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
526 N->getOperand(1), SubReg1 };
527 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
528 N->getValueType(0), Ops));
533 case ISD::ConstantFP: {
534 if (N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
538 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
539 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
541 ConstantSDNode *C = cast<ConstantSDNode>(N);
542 Imm = C->getZExtValue();
546 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
547 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
549 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
550 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
551 const SDValue Ops[] = {
552 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
553 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
554 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
557 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
558 N->getValueType(0), Ops));
567 case AMDGPUISD::BFE_I32:
568 case AMDGPUISD::BFE_U32: {
569 // There is a scalar version available, but unlike the vector version which
570 // has a separate operand for the offset and width, the scalar version packs
571 // the width and offset into a single operand. Try to move to the scalar
572 // version if the offsets are constant, so that we can try to keep extended
573 // loads of kernel arguments in SGPRs.
575 // TODO: Technically we could try to pattern match scalar bitshifts of
576 // dynamic values, but it's probably not useful.
577 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
581 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
585 bool Signed = Opc == AMDGPUISD::BFE_I32;
587 uint32_t OffsetVal = Offset->getZExtValue();
588 uint32_t WidthVal = Width->getZExtValue();
590 ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
591 SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
594 case AMDGPUISD::DIV_SCALE: {
598 case AMDGPUISD::MAD_I64_I32:
599 case AMDGPUISD::MAD_U64_U32: {
603 case ISD::CopyToReg: {
604 const SITargetLowering& Lowering =
605 *static_cast<const SITargetLowering*>(getTargetLowering());
606 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG);
612 case ISD::SIGN_EXTEND_INREG:
613 if (N->getValueType(0) != MVT::i32)
624 case AMDGPUISD::ATOMIC_CMP_SWAP:
625 SelectATOMIC_CMP_SWAP(N);
632 bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
636 return N->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS;
638 return N->getAddressSpace() == AMDGPUASI.CONSTANT_BUFFER_0 + CbId;
641 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
642 const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
643 const Instruction *Term = BB->getTerminator();
644 return Term->getMetadata("amdgpu.uniform") ||
645 Term->getMetadata("structurizecfg.uniform");
648 StringRef AMDGPUDAGToDAGISel::getPassName() const {
649 return "AMDGPU DAG->DAG Pattern Instruction Selection";
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
658 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
659 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
666 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
667 SDValue& BaseReg, SDValue &Offset) {
668 if (!isa<ConstantSDNode>(Addr)) {
670 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
676 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
681 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
686 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
687 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
688 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
689 } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
690 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
691 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
692 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
693 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
694 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
695 Base = Addr.getOperand(0);
696 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
699 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
705 // FIXME: Should only handle addcarry/subcarry
706 void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
708 SDValue LHS = N->getOperand(0);
709 SDValue RHS = N->getOperand(1);
711 unsigned Opcode = N->getOpcode();
712 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
714 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
715 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;
717 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
718 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
720 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
721 DL, MVT::i32, LHS, Sub0);
722 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
723 DL, MVT::i32, LHS, Sub1);
725 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
726 DL, MVT::i32, RHS, Sub0);
727 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
728 DL, MVT::i32, RHS, Sub1);
730 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
732 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
733 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
737 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
738 AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
740 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
741 AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
743 SDValue AddHiArgs[] = {
748 SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
750 SDValue RegSequenceArgs[] = {
751 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
757 SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
758 MVT::i64, RegSequenceArgs);
761 // Replace the carry-use
762 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1));
765 // Replace the remaining uses.
766 CurDAG->ReplaceAllUsesWith(N, RegSequence);
767 CurDAG->RemoveDeadNode(N);
770 void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
771 // The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
772 // carry out despite the _i32 name. These were renamed in VI to _U32.
773 // FIXME: We should probably rename the opcodes here.
774 unsigned Opc = N->getOpcode() == ISD::UADDO ?
775 AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
777 CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
778 { N->getOperand(0), N->getOperand(1) });
781 void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
783 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
786 SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
787 SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
788 SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
789 Ops[8] = N->getOperand(0);
790 Ops[9] = N->getOperand(4);
792 CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops);
795 void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
797 // src0_modifiers, src0, src1_modifiers, src1, clamp, omod
800 SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
801 SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
802 Ops[6] = N->getOperand(0);
803 Ops[7] = N->getOperand(3);
805 CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
808 // We need to handle this here because tablegen doesn't support matching
809 // instructions with multiple outputs.
810 void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
812 EVT VT = N->getValueType(0);
814 assert(VT == MVT::f32 || VT == MVT::f64);
817 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
819 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
820 CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
823 // We need to handle this here because tablegen doesn't support matching
824 // instructions with multiple outputs.
825 void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) {
827 bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32;
828 unsigned Opc = Signed ? AMDGPU::V_MAD_I64_I32 : AMDGPU::V_MAD_U64_U32;
830 SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1);
831 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
833 CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
836 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
837 unsigned OffsetBits) const {
838 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
839 (OffsetBits == 8 && !isUInt<8>(Offset)))
842 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
843 Subtarget->unsafeDSOffsetFoldingEnabled())
846 // On Southern Islands instruction with a negative base value and an offset
847 // don't seem to work.
848 return CurDAG->SignBitIsZero(Base);
851 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
852 SDValue &Offset) const {
854 if (CurDAG->isBaseWithConstantOffset(Addr)) {
855 SDValue N0 = Addr.getOperand(0);
856 SDValue N1 = Addr.getOperand(1);
857 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
858 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
861 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
864 } else if (Addr.getOpcode() == ISD::SUB) {
865 // sub C, x -> add (sub 0, x), C
866 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
867 int64_t ByteOffset = C->getSExtValue();
868 if (isUInt<16>(ByteOffset)) {
869 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
871 // XXX - This is kind of hacky. Create a dummy sub node so we can check
872 // the known bits in isDSOffsetLegal. We need to emit the selected node
873 // here, so this is thrown away.
874 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
875 Zero, Addr.getOperand(1));
877 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
878 // FIXME: Select to VOP3 version for with-carry.
879 unsigned SubOp = Subtarget->hasAddNoCarry() ?
880 AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32;
882 MachineSDNode *MachineSub
883 = CurDAG->getMachineNode(SubOp, DL, MVT::i32,
884 Zero, Addr.getOperand(1));
886 Base = SDValue(MachineSub, 0);
887 Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
892 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
893 // If we have a constant address, prefer to put the constant into the
894 // offset. This can save moves to load the constant address since multiple
895 // operations can share the zero base address register, and enables merging
896 // into read2 / write2 instructions.
900 if (isUInt<16>(CAddr->getZExtValue())) {
901 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
902 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
904 Base = SDValue(MovZero, 0);
905 Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
912 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
916 // TODO: If offset is too big, put low 16-bit into offset.
917 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
919 SDValue &Offset1) const {
922 if (CurDAG->isBaseWithConstantOffset(Addr)) {
923 SDValue N0 = Addr.getOperand(0);
924 SDValue N1 = Addr.getOperand(1);
925 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
926 unsigned DWordOffset0 = C1->getZExtValue() / 4;
927 unsigned DWordOffset1 = DWordOffset0 + 1;
929 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
931 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
932 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
935 } else if (Addr.getOpcode() == ISD::SUB) {
936 // sub C, x -> add (sub 0, x), C
937 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
938 unsigned DWordOffset0 = C->getZExtValue() / 4;
939 unsigned DWordOffset1 = DWordOffset0 + 1;
941 if (isUInt<8>(DWordOffset0)) {
943 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
945 // XXX - This is kind of hacky. Create a dummy sub node so we can check
946 // the known bits in isDSOffsetLegal. We need to emit the selected node
947 // here, so this is thrown away.
948 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
949 Zero, Addr.getOperand(1));
951 if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
952 unsigned SubOp = Subtarget->hasAddNoCarry() ?
953 AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32;
955 MachineSDNode *MachineSub
956 = CurDAG->getMachineNode(SubOp, DL, MVT::i32,
957 Zero, Addr.getOperand(1));
959 Base = SDValue(MachineSub, 0);
960 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
961 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
966 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
967 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
968 unsigned DWordOffset1 = DWordOffset0 + 1;
969 assert(4 * DWordOffset0 == CAddr->getZExtValue());
971 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
972 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
973 MachineSDNode *MovZero
974 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
976 Base = SDValue(MovZero, 0);
977 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
978 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
985 // FIXME: This is broken on SI where we still need to check if the base
986 // pointer is positive here.
988 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
989 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
993 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
994 SDValue &VAddr, SDValue &SOffset,
995 SDValue &Offset, SDValue &Offen,
996 SDValue &Idxen, SDValue &Addr64,
997 SDValue &GLC, SDValue &SLC,
998 SDValue &TFE) const {
999 // Subtarget prefers to use flat instruction
1000 if (Subtarget->useFlatForGlobal())
1006 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1008 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1009 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
1011 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1012 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1013 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
1014 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1016 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1017 SDValue N0 = Addr.getOperand(0);
1018 SDValue N1 = Addr.getOperand(1);
1019 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1021 if (N0.getOpcode() == ISD::ADD) {
1022 // (add (add N2, N3), C1) -> addr64
1023 SDValue N2 = N0.getOperand(0);
1024 SDValue N3 = N0.getOperand(1);
1025 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1029 // (add N0, C1) -> offset
1030 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1034 if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue())) {
1035 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1039 if (isUInt<32>(C1->getZExtValue())) {
1040 // Illegal offset, store it in soffset.
1041 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1042 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1043 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1049 if (Addr.getOpcode() == ISD::ADD) {
1050 // (add N0, N1) -> addr64
1051 SDValue N0 = Addr.getOperand(0);
1052 SDValue N1 = Addr.getOperand(1);
1053 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1056 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1060 // default case -> offset
1061 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1063 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1068 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1069 SDValue &VAddr, SDValue &SOffset,
1070 SDValue &Offset, SDValue &GLC,
1071 SDValue &SLC, SDValue &TFE) const {
1072 SDValue Ptr, Offen, Idxen, Addr64;
1074 // addr64 bit was removed for volcanic islands.
1075 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1078 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1082 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1083 if (C->getSExtValue()) {
1086 const SITargetLowering& Lowering =
1087 *static_cast<const SITargetLowering*>(getTargetLowering());
1089 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1096 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1097 SDValue &VAddr, SDValue &SOffset,
1099 SDValue &SLC) const {
1100 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1103 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1106 static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
1107 auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
1108 return PSV && PSV->isStack();
1111 std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
1112 const MachineFunction &MF = CurDAG->getMachineFunction();
1113 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1115 if (auto FI = dyn_cast<FrameIndexSDNode>(N)) {
1116 SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(),
1117 FI->getValueType(0));
1119 // If we can resolve this to a frame index access, this is relative to the
1120 // frame pointer SGPR.
1121 return std::make_pair(TFI, CurDAG->getRegister(Info->getFrameOffsetReg(),
1125 // If we don't know this private access is a local stack object, it needs to
1126 // be relative to the entry point's scratch wave offset register.
1127 return std::make_pair(N, CurDAG->getRegister(Info->getScratchWaveOffsetReg(),
1131 bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent,
1132 SDValue Addr, SDValue &Rsrc,
1133 SDValue &VAddr, SDValue &SOffset,
1134 SDValue &ImmOffset) const {
1137 MachineFunction &MF = CurDAG->getMachineFunction();
1138 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1140 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1142 if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
1143 unsigned Imm = CAddr->getZExtValue();
1145 SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
1146 MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1147 DL, MVT::i32, HighBits);
1148 VAddr = SDValue(MovHighBits, 0);
1150 // In a call sequence, stores to the argument stack area are relative to the
1152 const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Parent)->getPointerInfo();
1153 unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
1154 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
1156 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
1157 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
1161 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1164 SDValue N0 = Addr.getOperand(0);
1165 SDValue N1 = Addr.getOperand(1);
1167 // Offsets in vaddr must be positive if range checking is enabled.
1169 // The total computation of vaddr + soffset + offset must not overflow. If
1170 // vaddr is negative, even if offset is 0 the sgpr offset add will end up
1173 // Prior to gfx9, MUBUF instructions with the vaddr offset enabled would
1174 // always perform a range check. If a negative vaddr base index was used,
1175 // this would fail the range check. The overall address computation would
1176 // compute a valid address, but this doesn't happen due to the range
1177 // check. For out-of-bounds MUBUF loads, a 0 is returned.
1179 // Therefore it should be safe to fold any VGPR offset on gfx9 into the
1180 // MUBUF vaddr, but not on older subtargets which can only do this if the
1181 // sign bit is known 0.
1182 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1183 if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue()) &&
1184 (!Subtarget->privateMemoryResourceIsRangeChecked() ||
1185 CurDAG->SignBitIsZero(N0))) {
1186 std::tie(VAddr, SOffset) = foldFrameIndex(N0);
1187 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1193 std::tie(VAddr, SOffset) = foldFrameIndex(Addr);
1194 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1198 bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Parent,
1202 SDValue &Offset) const {
1203 ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr);
1204 if (!CAddr || !SIInstrInfo::isLegalMUBUFImmOffset(CAddr->getZExtValue()))
1208 MachineFunction &MF = CurDAG->getMachineFunction();
1209 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1211 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1213 const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Parent)->getPointerInfo();
1214 unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
1215 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
1217 // FIXME: Get from MachinePointerInfo? We should only be using the frame
1218 // offset if we know this is in a call sequence.
1219 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
1221 Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
1225 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1226 SDValue &SOffset, SDValue &Offset,
1227 SDValue &GLC, SDValue &SLC,
1228 SDValue &TFE) const {
1229 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1230 const SIInstrInfo *TII =
1231 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1233 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1237 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1238 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1239 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1240 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1241 APInt::getAllOnesValue(32).getZExtValue(); // Size
1244 const SITargetLowering& Lowering =
1245 *static_cast<const SITargetLowering*>(getTargetLowering());
1247 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1253 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1254 SDValue &Soffset, SDValue &Offset
1256 SDValue GLC, SLC, TFE;
1258 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1260 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1261 SDValue &Soffset, SDValue &Offset,
1262 SDValue &SLC) const {
1265 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1268 bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
1270 SDValue &ImmOffset) const {
1272 const uint32_t Align = 4;
1273 const uint32_t MaxImm = alignDown(4095, Align);
1274 uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
1275 uint32_t Overflow = 0;
1278 if (Imm <= MaxImm + 64) {
1279 // Use an SOffset inline constant for 4..64
1280 Overflow = Imm - MaxImm;
1283 // Try to keep the same value in SOffset for adjacent loads, so that
1284 // the corresponding register contents can be re-used.
1286 // Load values with all low-bits (except for alignment bits) set into
1287 // SOffset, so that a larger range of values can be covered using
1290 // Atomic operations fail to work correctly when individual address
1291 // components are unaligned, even if their sum is aligned.
1292 uint32_t High = (Imm + Align) & ~4095;
1293 uint32_t Low = (Imm + Align) & 4095;
1295 Overflow = High - Align;
1299 // There is a hardware bug in SI and CI which prevents address clamping in
1300 // MUBUF instructions from working correctly with SOffsets. The immediate
1301 // offset is unaffected.
1303 Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1306 ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16);
1309 SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32);
1311 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1312 CurDAG->getTargetConstant(Overflow, DL, MVT::i32)),
1318 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
1320 SDValue &ImmOffset) const {
1323 if (!isa<ConstantSDNode>(Offset))
1326 return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
1329 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
1332 SDValue &VOffset) const {
1335 // Don't generate an unnecessary voffset for constant offsets.
1336 if (isa<ConstantSDNode>(Offset)) {
1339 // When necessary, use a voffset in <= CI anyway to work around a hardware
1341 if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS ||
1342 SelectMUBUFConstant(Offset, Tmp1, Tmp2))
1346 if (CurDAG->isBaseWithConstantOffset(Offset)) {
1347 SDValue N0 = Offset.getOperand(0);
1348 SDValue N1 = Offset.getOperand(1);
1349 if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
1350 SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
1356 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1357 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1363 template <bool IsSigned>
1364 bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDValue Addr,
1367 SDValue &SLC) const {
1368 int64_t OffsetVal = 0;
1370 if (Subtarget->hasFlatInstOffsets() &&
1371 CurDAG->isBaseWithConstantOffset(Addr)) {
1372 SDValue N0 = Addr.getOperand(0);
1373 SDValue N1 = Addr.getOperand(1);
1374 int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
1376 if ((IsSigned && isInt<13>(COffsetVal)) ||
1377 (!IsSigned && isUInt<12>(COffsetVal))) {
1379 OffsetVal = COffsetVal;
1384 Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
1385 SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
1390 bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDValue Addr,
1393 SDValue &SLC) const {
1394 return SelectFlatOffset<false>(Addr, VAddr, Offset, SLC);
1397 bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDValue Addr,
1400 SDValue &SLC) const {
1401 return SelectFlatOffset<true>(Addr, VAddr, Offset, SLC);
1404 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1405 SDValue &Offset, bool &Imm) const {
1407 // FIXME: Handle non-constant offsets.
1408 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1412 SDLoc SL(ByteOffsetNode);
1413 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1414 int64_t ByteOffset = C->getSExtValue();
1415 int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
1417 if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) {
1418 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1423 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1426 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1427 // 32-bit Immediates are supported on Sea Islands.
1428 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1430 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1431 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1438 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1439 SDValue &Offset, bool &Imm) const {
1441 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1442 SDValue N0 = Addr.getOperand(0);
1443 SDValue N1 = Addr.getOperand(1);
1445 if (SelectSMRDOffset(N1, Offset, Imm)) {
1451 Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1456 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1457 SDValue &Offset) const {
1459 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1462 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1463 SDValue &Offset) const {
1465 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1469 if (!SelectSMRD(Addr, SBase, Offset, Imm))
1472 return !Imm && isa<ConstantSDNode>(Offset);
1475 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1476 SDValue &Offset) const {
1478 return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1479 !isa<ConstantSDNode>(Offset);
1482 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1483 SDValue &Offset) const {
1485 return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1488 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1489 SDValue &Offset) const {
1490 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1494 if (!SelectSMRDOffset(Addr, Offset, Imm))
1497 return !Imm && isa<ConstantSDNode>(Offset);
1500 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1502 SDValue &Offset) const {
1505 if (CurDAG->isBaseWithConstantOffset(Index)) {
1506 SDValue N0 = Index.getOperand(0);
1507 SDValue N1 = Index.getOperand(1);
1508 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1512 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
1516 if (isa<ConstantSDNode>(Index))
1520 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1524 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
1525 SDValue Val, uint32_t Offset,
1527 // Transformation function, pack the offset and width of a BFE into
1528 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1529 // source, bits [5:0] contain the offset and bits [22:16] the width.
1530 uint32_t PackedVal = Offset | (Width << 16);
1531 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1533 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1536 void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1537 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1538 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1539 // Predicate: 0 < b <= c < 32
1541 const SDValue &Shl = N->getOperand(0);
1542 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1546 uint32_t BVal = B->getZExtValue();
1547 uint32_t CVal = C->getZExtValue();
1549 if (0 < BVal && BVal <= CVal && CVal < 32) {
1550 bool Signed = N->getOpcode() == ISD::SRA;
1551 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1553 ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
1561 void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1562 switch (N->getOpcode()) {
1564 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1565 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1566 // Predicate: isMask(mask)
1567 const SDValue &Srl = N->getOperand(0);
1568 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1569 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1571 if (Shift && Mask) {
1572 uint32_t ShiftVal = Shift->getZExtValue();
1573 uint32_t MaskVal = Mask->getZExtValue();
1575 if (isMask_32(MaskVal)) {
1576 uint32_t WidthVal = countPopulation(MaskVal);
1578 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1579 Srl.getOperand(0), ShiftVal, WidthVal));
1586 if (N->getOperand(0).getOpcode() == ISD::AND) {
1587 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1588 // Predicate: isMask(mask >> b)
1589 const SDValue &And = N->getOperand(0);
1590 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1591 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1593 if (Shift && Mask) {
1594 uint32_t ShiftVal = Shift->getZExtValue();
1595 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1597 if (isMask_32(MaskVal)) {
1598 uint32_t WidthVal = countPopulation(MaskVal);
1600 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1601 And.getOperand(0), ShiftVal, WidthVal));
1605 } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1606 SelectS_BFEFromShifts(N);
1611 if (N->getOperand(0).getOpcode() == ISD::SHL) {
1612 SelectS_BFEFromShifts(N);
1617 case ISD::SIGN_EXTEND_INREG: {
1618 // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
1619 SDValue Src = N->getOperand(0);
1620 if (Src.getOpcode() != ISD::SRL)
1623 const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1627 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1628 ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
1629 Amt->getZExtValue(), Width));
1637 bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
1638 assert(N->getOpcode() == ISD::BRCOND);
1639 if (!N->hasOneUse())
1642 SDValue Cond = N->getOperand(1);
1643 if (Cond.getOpcode() == ISD::CopyToReg)
1644 Cond = Cond.getOperand(2);
1646 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
1649 MVT VT = Cond.getOperand(0).getSimpleValueType();
1653 if (VT == MVT::i64) {
1654 auto ST = static_cast<const SISubtarget *>(Subtarget);
1656 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
1657 return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
1663 void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
1664 SDValue Cond = N->getOperand(1);
1666 if (Cond.isUndef()) {
1667 CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
1668 N->getOperand(2), N->getOperand(0));
1672 bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N);
1673 unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ;
1674 unsigned CondReg = UseSCCBr ? AMDGPU::SCC : AMDGPU::VCC;
1677 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
1678 CurDAG->SelectNodeTo(N, BrOp, MVT::Other,
1679 N->getOperand(2), // Basic Block
1683 void AMDGPUDAGToDAGISel::SelectFMAD(SDNode *N) {
1684 MVT VT = N->getSimpleValueType(0);
1685 if (VT != MVT::f32 || !Subtarget->hasMadMixInsts()) {
1690 SDValue Src0 = N->getOperand(0);
1691 SDValue Src1 = N->getOperand(1);
1692 SDValue Src2 = N->getOperand(2);
1693 unsigned Src0Mods, Src1Mods, Src2Mods;
1695 // Avoid using v_mad_mix_f32 unless there is actually an operand using the
1696 // conversion from f16.
1697 bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods);
1698 bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods);
1699 bool Sel2 = SelectVOP3PMadMixModsImpl(Src2, Src2, Src2Mods);
1701 assert(!Subtarget->hasFP32Denormals() &&
1702 "fmad selected with denormals enabled");
1703 // TODO: We can select this with f32 denormals enabled if all the sources are
1704 // converted from f16 (in which case fmad isn't legal).
1706 if (Sel0 || Sel1 || Sel2) {
1707 // For dummy operands.
1708 SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
1710 CurDAG->getTargetConstant(Src0Mods, SDLoc(), MVT::i32), Src0,
1711 CurDAG->getTargetConstant(Src1Mods, SDLoc(), MVT::i32), Src1,
1712 CurDAG->getTargetConstant(Src2Mods, SDLoc(), MVT::i32), Src2,
1713 CurDAG->getTargetConstant(0, SDLoc(), MVT::i1),
1717 CurDAG->SelectNodeTo(N, AMDGPU::V_MAD_MIX_F32, MVT::f32, Ops);
1723 // This is here because there isn't a way to use the generated sub0_sub1 as the
1724 // subreg index to EXTRACT_SUBREG in tablegen.
1725 void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
1726 MemSDNode *Mem = cast<MemSDNode>(N);
1727 unsigned AS = Mem->getAddressSpace();
1728 if (AS == AMDGPUASI.FLAT_ADDRESS) {
1733 MVT VT = N->getSimpleValueType(0);
1734 bool Is32 = (VT == MVT::i32);
1737 MachineSDNode *CmpSwap = nullptr;
1738 if (Subtarget->hasAddr64()) {
1739 SDValue SRsrc, VAddr, SOffset, Offset, SLC;
1741 if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
1742 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN :
1743 AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN;
1744 SDValue CmpVal = Mem->getOperand(2);
1746 // XXX - Do we care about glue operands?
1749 CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1752 CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1757 SDValue SRsrc, SOffset, Offset, SLC;
1758 if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
1759 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN :
1760 AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN;
1762 SDValue CmpVal = Mem->getOperand(2);
1764 CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1767 CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1776 MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
1777 *MMOs = Mem->getMemOperand();
1778 CmpSwap->setMemRefs(MMOs, MMOs + 1);
1780 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
1782 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
1784 ReplaceUses(SDValue(N, 0), Extract);
1785 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
1786 CurDAG->RemoveDeadNode(N);
1789 bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
1790 unsigned &Mods) const {
1794 if (Src.getOpcode() == ISD::FNEG) {
1795 Mods |= SISrcMods::NEG;
1796 Src = Src.getOperand(0);
1799 if (Src.getOpcode() == ISD::FABS) {
1800 Mods |= SISrcMods::ABS;
1801 Src = Src.getOperand(0);
1807 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1808 SDValue &SrcMods) const {
1810 if (SelectVOP3ModsImpl(In, Src, Mods)) {
1811 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1818 bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
1819 SDValue &SrcMods) const {
1820 SelectVOP3Mods(In, Src, SrcMods);
1821 return isNoNanSrc(Src);
1824 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const {
1825 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
1832 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1833 SDValue &SrcMods, SDValue &Clamp,
1834 SDValue &Omod) const {
1836 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
1837 Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
1839 return SelectVOP3Mods(In, Src, SrcMods);
1842 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1845 SDValue &Omod) const {
1846 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1847 return SelectVOP3Mods(In, Src, SrcMods);
1850 bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
1851 SDValue &Clamp, SDValue &Omod) const {
1855 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
1856 Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
1861 static SDValue stripBitcast(SDValue Val) {
1862 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
1865 // Figure out if this is really an extract of the high 16-bits of a dword.
1866 static bool isExtractHiElt(SDValue In, SDValue &Out) {
1867 In = stripBitcast(In);
1868 if (In.getOpcode() != ISD::TRUNCATE)
1871 SDValue Srl = In.getOperand(0);
1872 if (Srl.getOpcode() == ISD::SRL) {
1873 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
1874 if (ShiftAmt->getZExtValue() == 16) {
1875 Out = stripBitcast(Srl.getOperand(0));
1884 // Look through operations that obscure just looking at the low 16-bits of the
1886 static SDValue stripExtractLoElt(SDValue In) {
1887 if (In.getOpcode() == ISD::TRUNCATE) {
1888 SDValue Src = In.getOperand(0);
1889 if (Src.getValueType().getSizeInBits() == 32)
1890 return stripBitcast(Src);
1896 bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
1897 SDValue &SrcMods) const {
1901 if (Src.getOpcode() == ISD::FNEG) {
1902 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
1903 Src = Src.getOperand(0);
1906 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
1907 unsigned VecMods = Mods;
1909 SDValue Lo = stripBitcast(Src.getOperand(0));
1910 SDValue Hi = stripBitcast(Src.getOperand(1));
1912 if (Lo.getOpcode() == ISD::FNEG) {
1913 Lo = stripBitcast(Lo.getOperand(0));
1914 Mods ^= SISrcMods::NEG;
1917 if (Hi.getOpcode() == ISD::FNEG) {
1918 Hi = stripBitcast(Hi.getOperand(0));
1919 Mods ^= SISrcMods::NEG_HI;
1922 if (isExtractHiElt(Lo, Lo))
1923 Mods |= SISrcMods::OP_SEL_0;
1925 if (isExtractHiElt(Hi, Hi))
1926 Mods |= SISrcMods::OP_SEL_1;
1928 Lo = stripExtractLoElt(Lo);
1929 Hi = stripExtractLoElt(Hi);
1931 if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {
1932 // Really a scalar input. Just select from the low half of the register to
1936 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1943 // Packed instructions do not have abs modifiers.
1944 Mods |= SISrcMods::OP_SEL_1;
1946 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1950 bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src,
1952 SDValue &Clamp) const {
1955 // FIXME: Handle clamp and op_sel
1956 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1958 return SelectVOP3PMods(In, Src, SrcMods);
1961 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
1962 SDValue &SrcMods) const {
1964 // FIXME: Handle op_sel
1965 SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1969 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src,
1971 SDValue &Clamp) const {
1974 // FIXME: Handle clamp
1975 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1977 return SelectVOP3OpSel(In, Src, SrcMods);
1980 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
1981 SDValue &SrcMods) const {
1982 // FIXME: Handle op_sel
1983 return SelectVOP3Mods(In, Src, SrcMods);
1986 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src,
1988 SDValue &Clamp) const {
1991 // FIXME: Handle clamp
1992 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1994 return SelectVOP3OpSelMods(In, Src, SrcMods);
1997 // The return value is not whether the match is possible (which it always is),
1998 // but whether or not it a conversion is really used.
1999 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
2000 unsigned &Mods) const {
2002 SelectVOP3ModsImpl(In, Src, Mods);
2004 if (Src.getOpcode() == ISD::FP_EXTEND) {
2005 Src = Src.getOperand(0);
2006 assert(Src.getValueType() == MVT::f16);
2007 Src = stripBitcast(Src);
2009 // Be careful about folding modifiers if we already have an abs. fneg is
2010 // applied last, so we don't want to apply an earlier fneg.
2011 if ((Mods & SISrcMods::ABS) == 0) {
2013 SelectVOP3ModsImpl(Src, Src, ModsTmp);
2015 if ((ModsTmp & SISrcMods::NEG) != 0)
2016 Mods ^= SISrcMods::NEG;
2018 if ((ModsTmp & SISrcMods::ABS) != 0)
2019 Mods |= SISrcMods::ABS;
2022 // op_sel/op_sel_hi decide the source type and source.
2023 // If the source's op_sel_hi is set, it indicates to do a conversion from fp16.
2024 // If the sources's op_sel is set, it picks the high half of the source
2027 Mods |= SISrcMods::OP_SEL_1;
2028 if (isExtractHiElt(Src, Src)) {
2029 Mods |= SISrcMods::OP_SEL_0;
2031 // TODO: Should we try to look for neg/abs here?
2040 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src,
2041 SDValue &SrcMods) const {
2043 SelectVOP3PMadMixModsImpl(In, Src, Mods);
2044 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
2048 // TODO: Can we identify things like v_mad_mixhi_f16?
2049 bool AMDGPUDAGToDAGISel::SelectHi16Elt(SDValue In, SDValue &Src) const {
2055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) {
2057 SDValue K = CurDAG->getTargetConstant(C->getZExtValue() << 16, SL, MVT::i32);
2058 MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
2060 Src = SDValue(MovK, 0);
2064 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(In)) {
2066 SDValue K = CurDAG->getTargetConstant(
2067 C->getValueAPF().bitcastToAPInt().getZExtValue() << 16, SL, MVT::i32);
2068 MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
2070 Src = SDValue(MovK, 0);
2074 return isExtractHiElt(In, Src);
2077 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
2078 const AMDGPUTargetLowering& Lowering =
2079 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
2080 bool IsModified = false;
2084 // Go over all selected nodes and try to fold them a bit more
2085 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin();
2086 while (Position != CurDAG->allnodes_end()) {
2087 SDNode *Node = &*Position++;
2088 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(Node);
2092 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
2093 if (ResNode != Node) {
2095 ReplaceUses(Node, ResNode);
2099 CurDAG->RemoveDeadNodes();
2100 } while (IsModified);
2103 void R600DAGToDAGISel::Select(SDNode *N) {
2104 unsigned int Opc = N->getOpcode();
2105 if (N->isMachineOpcode()) {
2107 return; // Already selected.
2112 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
2113 case ISD::SCALAR_TO_VECTOR:
2114 case ISD::BUILD_VECTOR: {
2115 EVT VT = N->getValueType(0);
2116 unsigned NumVectorElts = VT.getVectorNumElements();
2117 unsigned RegClassID;
2118 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
2119 // that adds a 128 bits reg copy when going through TwoAddressInstructions
2120 // pass. We want to avoid 128 bits copies as much as possible because they
2121 // can't be bundled by our scheduler.
2122 switch(NumVectorElts) {
2123 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
2125 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
2126 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
2128 RegClassID = AMDGPU::R600_Reg128RegClassID;
2130 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
2132 SelectBuildVector(N, RegClassID);
2140 bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
2145 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
2146 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
2147 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
2148 } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
2149 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
2150 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
2151 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
2152 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
2153 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
2154 Base = Addr.getOperand(0);
2155 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
2158 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
2164 bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
2166 ConstantSDNode *IMMOffset;
2168 if (Addr.getOpcode() == ISD::ADD
2169 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
2170 && isInt<16>(IMMOffset->getZExtValue())) {
2172 Base = Addr.getOperand(0);
2173 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
2176 // If the pointer address is constant, we can move it to the offset field.
2177 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
2178 && isInt<16>(IMMOffset->getZExtValue())) {
2179 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
2180 SDLoc(CurDAG->getEntryNode()),
2181 AMDGPU::ZERO, MVT::i32);
2182 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
2187 // Default case, no offset
2189 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);