1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "SIInstrInfo.h"
35 static bool allocateKernArg(unsigned ValNo, MVT ValVT, MVT LocVT,
36 CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State) {
38 MachineFunction &MF = State.getMachineFunction();
39 AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
41 uint64_t Offset = MFI->allocateKernArg(LocVT.getStoreSize(),
42 ArgFlags.getOrigAlign());
43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
47 static bool allocateCCRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
48 CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State,
50 const TargetRegisterClass *RC,
52 ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs);
53 unsigned RegResult = State.AllocateReg(RegList);
54 if (RegResult == AMDGPU::NoRegister)
57 State.addLoc(CCValAssign::getReg(ValNo, ValVT, RegResult, LocVT, LocInfo));
61 static bool allocateSGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
62 CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State) {
64 switch (LocVT.SimpleTy) {
70 return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
71 &AMDGPU::SGPR_64RegClass, 20);
78 #include "AMDGPUGenCallingConv.inc"
80 // Find a larger type to do a load / store of a vector with.
81 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
82 unsigned StoreSize = VT.getStoreSizeInBits();
84 return EVT::getIntegerVT(Ctx, StoreSize);
86 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
87 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
90 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
91 const AMDGPUSubtarget &STI)
92 : TargetLowering(TM), Subtarget(&STI) {
93 AMDGPUASI = AMDGPU::getAMDGPUAS(TM);
94 // Lower floating point store/load to integer store/load to reduce the number
95 // of patterns in tablegen.
96 setOperationAction(ISD::LOAD, MVT::f32, Promote);
97 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
99 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
100 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
102 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
103 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
105 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
106 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
108 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
109 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
111 setOperationAction(ISD::LOAD, MVT::i64, Promote);
112 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
114 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
115 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
117 setOperationAction(ISD::LOAD, MVT::f64, Promote);
118 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
120 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
121 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
123 // There are no 64-bit extloads. These should be done as a 32-bit extload and
124 // an extension to 64-bit.
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
128 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
131 for (MVT VT : MVT::integer_valuetypes()) {
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
148 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
151 for (MVT VT : MVT::integer_vector_valuetypes()) {
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
153 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
154 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
155 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
157 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
158 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
160 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
162 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
163 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
167 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
168 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
169 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
171 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
172 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
173 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
174 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
176 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
177 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
178 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
179 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
181 setOperationAction(ISD::STORE, MVT::f32, Promote);
182 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
184 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
185 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
187 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
188 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
190 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
191 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
193 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
194 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
196 setOperationAction(ISD::STORE, MVT::i64, Promote);
197 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
199 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
200 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
202 setOperationAction(ISD::STORE, MVT::f64, Promote);
203 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
205 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
208 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
209 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
210 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
211 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
213 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
214 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
215 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
216 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
218 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
219 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
220 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
221 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
223 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
224 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
226 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
227 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
229 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
230 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
232 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
233 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
236 setOperationAction(ISD::Constant, MVT::i32, Legal);
237 setOperationAction(ISD::Constant, MVT::i64, Legal);
238 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
239 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
241 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
242 setOperationAction(ISD::BRIND, MVT::Other, Expand);
244 // This is totally unsupported, just custom lower to produce an error.
245 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
247 // Library functions. These default to Expand, but we have instructions
249 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
250 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
251 setOperationAction(ISD::FPOW, MVT::f32, Legal);
252 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
253 setOperationAction(ISD::FABS, MVT::f32, Legal);
254 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
255 setOperationAction(ISD::FRINT, MVT::f32, Legal);
256 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
257 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
258 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
260 setOperationAction(ISD::FROUND, MVT::f32, Custom);
261 setOperationAction(ISD::FROUND, MVT::f64, Custom);
263 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
264 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
266 setOperationAction(ISD::FREM, MVT::f32, Custom);
267 setOperationAction(ISD::FREM, MVT::f64, Custom);
269 // v_mad_f32 does not support denormals according to some sources.
270 if (!Subtarget->hasFP32Denormals())
271 setOperationAction(ISD::FMAD, MVT::f32, Legal);
273 // Expand to fneg + fadd.
274 setOperationAction(ISD::FSUB, MVT::f64, Expand);
276 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
277 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
280 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
281 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
282 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
283 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
284 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
285 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
287 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
288 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
289 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
290 setOperationAction(ISD::FRINT, MVT::f64, Custom);
291 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
294 if (!Subtarget->hasBFI()) {
295 // fcopysign can be done in a single instruction with BFI.
296 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
297 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
300 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
301 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
302 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
304 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
305 for (MVT VT : ScalarIntVTs) {
306 // These should use [SU]DIVREM, so set them to expand
307 setOperationAction(ISD::SDIV, VT, Expand);
308 setOperationAction(ISD::UDIV, VT, Expand);
309 setOperationAction(ISD::SREM, VT, Expand);
310 setOperationAction(ISD::UREM, VT, Expand);
312 // GPU does not have divrem function for signed or unsigned.
313 setOperationAction(ISD::SDIVREM, VT, Custom);
314 setOperationAction(ISD::UDIVREM, VT, Custom);
316 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
317 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
318 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
320 setOperationAction(ISD::BSWAP, VT, Expand);
321 setOperationAction(ISD::CTTZ, VT, Expand);
322 setOperationAction(ISD::CTLZ, VT, Expand);
325 if (!Subtarget->hasBCNT(32))
326 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
328 if (!Subtarget->hasBCNT(64))
329 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
331 // The hardware supports 32-bit ROTR, but not ROTL.
332 setOperationAction(ISD::ROTL, MVT::i32, Expand);
333 setOperationAction(ISD::ROTL, MVT::i64, Expand);
334 setOperationAction(ISD::ROTR, MVT::i64, Expand);
336 setOperationAction(ISD::MUL, MVT::i64, Expand);
337 setOperationAction(ISD::MULHU, MVT::i64, Expand);
338 setOperationAction(ISD::MULHS, MVT::i64, Expand);
339 setOperationAction(ISD::UDIV, MVT::i32, Expand);
340 setOperationAction(ISD::UREM, MVT::i32, Expand);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
343 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
344 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
345 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
347 setOperationAction(ISD::SMIN, MVT::i32, Legal);
348 setOperationAction(ISD::UMIN, MVT::i32, Legal);
349 setOperationAction(ISD::SMAX, MVT::i32, Legal);
350 setOperationAction(ISD::UMAX, MVT::i32, Legal);
352 if (Subtarget->hasFFBH())
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
355 if (Subtarget->hasFFBL())
356 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Legal);
358 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
361 // We only really have 32-bit BFE instructions (and 16-bit on VI).
363 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
364 // effort to match them now. We want this to be false for i64 cases when the
365 // extraction isn't restricted to the upper or lower half. Ideally we would
366 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
367 // span the midpoint are probably relatively rare, so don't worry about them
369 if (Subtarget->hasBFE())
370 setHasExtractBitsInsn(true);
372 static const MVT::SimpleValueType VectorIntTypes[] = {
373 MVT::v2i32, MVT::v4i32
376 for (MVT VT : VectorIntTypes) {
377 // Expand the following operations for the current type by default.
378 setOperationAction(ISD::ADD, VT, Expand);
379 setOperationAction(ISD::AND, VT, Expand);
380 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
381 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
382 setOperationAction(ISD::MUL, VT, Expand);
383 setOperationAction(ISD::MULHU, VT, Expand);
384 setOperationAction(ISD::MULHS, VT, Expand);
385 setOperationAction(ISD::OR, VT, Expand);
386 setOperationAction(ISD::SHL, VT, Expand);
387 setOperationAction(ISD::SRA, VT, Expand);
388 setOperationAction(ISD::SRL, VT, Expand);
389 setOperationAction(ISD::ROTL, VT, Expand);
390 setOperationAction(ISD::ROTR, VT, Expand);
391 setOperationAction(ISD::SUB, VT, Expand);
392 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
393 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
394 setOperationAction(ISD::SDIV, VT, Expand);
395 setOperationAction(ISD::UDIV, VT, Expand);
396 setOperationAction(ISD::SREM, VT, Expand);
397 setOperationAction(ISD::UREM, VT, Expand);
398 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
399 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
400 setOperationAction(ISD::SDIVREM, VT, Custom);
401 setOperationAction(ISD::UDIVREM, VT, Expand);
402 setOperationAction(ISD::ADDC, VT, Expand);
403 setOperationAction(ISD::SUBC, VT, Expand);
404 setOperationAction(ISD::ADDE, VT, Expand);
405 setOperationAction(ISD::SUBE, VT, Expand);
406 setOperationAction(ISD::SELECT, VT, Expand);
407 setOperationAction(ISD::VSELECT, VT, Expand);
408 setOperationAction(ISD::SELECT_CC, VT, Expand);
409 setOperationAction(ISD::XOR, VT, Expand);
410 setOperationAction(ISD::BSWAP, VT, Expand);
411 setOperationAction(ISD::CTPOP, VT, Expand);
412 setOperationAction(ISD::CTTZ, VT, Expand);
413 setOperationAction(ISD::CTLZ, VT, Expand);
414 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
417 static const MVT::SimpleValueType FloatVectorTypes[] = {
418 MVT::v2f32, MVT::v4f32
421 for (MVT VT : FloatVectorTypes) {
422 setOperationAction(ISD::FABS, VT, Expand);
423 setOperationAction(ISD::FMINNUM, VT, Expand);
424 setOperationAction(ISD::FMAXNUM, VT, Expand);
425 setOperationAction(ISD::FADD, VT, Expand);
426 setOperationAction(ISD::FCEIL, VT, Expand);
427 setOperationAction(ISD::FCOS, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FEXP2, VT, Expand);
430 setOperationAction(ISD::FLOG2, VT, Expand);
431 setOperationAction(ISD::FREM, VT, Expand);
432 setOperationAction(ISD::FPOW, VT, Expand);
433 setOperationAction(ISD::FFLOOR, VT, Expand);
434 setOperationAction(ISD::FTRUNC, VT, Expand);
435 setOperationAction(ISD::FMUL, VT, Expand);
436 setOperationAction(ISD::FMA, VT, Expand);
437 setOperationAction(ISD::FRINT, VT, Expand);
438 setOperationAction(ISD::FNEARBYINT, VT, Expand);
439 setOperationAction(ISD::FSQRT, VT, Expand);
440 setOperationAction(ISD::FSIN, VT, Expand);
441 setOperationAction(ISD::FSUB, VT, Expand);
442 setOperationAction(ISD::FNEG, VT, Expand);
443 setOperationAction(ISD::VSELECT, VT, Expand);
444 setOperationAction(ISD::SELECT_CC, VT, Expand);
445 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
446 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
449 // This causes using an unrolled select operation rather than expansion with
450 // bit operations. This is in general better, but the alternative using BFI
451 // instructions may be better if the select sources are SGPRs.
452 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
453 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
455 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
456 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
458 // There are no libcalls of any kind.
459 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
460 setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
462 setBooleanContents(ZeroOrNegativeOneBooleanContent);
463 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
465 setSchedulingPreference(Sched::RegPressure);
466 setJumpIsExpensive(true);
468 // FIXME: This is only partially true. If we have to do vector compares, any
469 // SGPR pair can be a condition register. If we have a uniform condition, we
470 // are better off doing SALU operations, where there is only one SCC. For now,
471 // we don't have a way of knowing during instruction selection if a condition
472 // will be uniform and we always use vector compares. Assume we are using
473 // vector compares until that is fixed.
474 setHasMultipleConditionRegisters(true);
476 // SI at least has hardware support for floating point exceptions, but no way
477 // of using or handling them is implemented. They are also optional in OpenCL
479 setHasFloatingPointExceptions(Subtarget->hasFPExceptions());
481 PredictableSelectIsExpensive = false;
483 // We want to find all load dependencies for long chains of stores to enable
484 // merging into very wide vectors. The problem is with vectors with > 4
485 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
486 // vectors are a legal type, even though we have to split the loads
487 // usually. When we can more precisely specify load legality per address
488 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
489 // smarter so that they can figure out what to do in 2 iterations without all
490 // N > 4 stores on the same chain.
491 GatherAllAliasesMaxDepth = 16;
493 // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
494 // about these during lowering.
495 MaxStoresPerMemcpy = 0xffffffff;
496 MaxStoresPerMemmove = 0xffffffff;
497 MaxStoresPerMemset = 0xffffffff;
499 setTargetDAGCombine(ISD::BITCAST);
500 setTargetDAGCombine(ISD::SHL);
501 setTargetDAGCombine(ISD::SRA);
502 setTargetDAGCombine(ISD::SRL);
503 setTargetDAGCombine(ISD::MUL);
504 setTargetDAGCombine(ISD::MULHU);
505 setTargetDAGCombine(ISD::MULHS);
506 setTargetDAGCombine(ISD::SELECT);
507 setTargetDAGCombine(ISD::SELECT_CC);
508 setTargetDAGCombine(ISD::STORE);
509 setTargetDAGCombine(ISD::FADD);
510 setTargetDAGCombine(ISD::FSUB);
511 setTargetDAGCombine(ISD::FNEG);
512 setTargetDAGCombine(ISD::FABS);
515 //===----------------------------------------------------------------------===//
516 // Target Information
517 //===----------------------------------------------------------------------===//
520 static bool fnegFoldsIntoOp(unsigned Opc) {
532 case ISD::FNEARBYINT:
534 case AMDGPUISD::RCP_LEGACY:
535 case AMDGPUISD::SIN_HW:
536 case AMDGPUISD::FMUL_LEGACY:
537 case AMDGPUISD::FMIN_LEGACY:
538 case AMDGPUISD::FMAX_LEGACY:
545 /// \p returns true if the operation will definitely need to use a 64-bit
546 /// encoding, and thus will use a VOP3 encoding regardless of the source
549 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
550 return N->getNumOperands() > 2 || VT == MVT::f64;
553 // Most FP instructions support source modifiers, but this could be refined
556 static bool hasSourceMods(const SDNode *N) {
557 if (isa<MemSDNode>(N))
560 switch (N->getOpcode()) {
566 case AMDGPUISD::INTERP_P1:
567 case AMDGPUISD::INTERP_P2:
568 case AMDGPUISD::DIV_SCALE:
575 static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold = 4) {
576 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
577 // it is truly free to use a source modifier in all cases. If there are
578 // multiple users but for each one will necessitate using VOP3, there will be
579 // a code size increase. Try to avoid increasing code size unless we know it
580 // will save on the instruction count.
581 unsigned NumMayIncreaseSize = 0;
582 MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
584 // XXX - Should this limit number of uses to check?
585 for (const SDNode *U : N->uses()) {
586 if (!hasSourceMods(U))
589 if (!opMustUseVOP3Encoding(U, VT)) {
590 if (++NumMayIncreaseSize > CostThreshold)
598 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
602 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
606 // The backend supports 32 and 64 bit floating point immediates.
607 // FIXME: Why are we reporting vectors of FP immediates as legal?
608 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
609 EVT ScalarVT = VT.getScalarType();
610 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
611 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
614 // We don't want to shrink f64 / f32 constants.
615 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
616 EVT ScalarVT = VT.getScalarType();
617 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
620 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
624 unsigned NewSize = NewVT.getStoreSizeInBits();
626 // If we are reducing to a 32-bit load, this is always better.
630 EVT OldVT = N->getValueType(0);
631 unsigned OldSize = OldVT.getStoreSizeInBits();
633 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
634 // extloads, so doing one requires using a buffer_load. In cases where we
635 // still couldn't use a scalar load, using the wider load shouldn't really
638 // If the old size already had to be an extload, there's no harm in continuing
639 // to reduce the width.
640 return (OldSize < 32);
643 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
646 assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
648 if (LoadTy.getScalarType() == MVT::i32)
651 unsigned LScalarSize = LoadTy.getScalarSizeInBits();
652 unsigned CastScalarSize = CastTy.getScalarSizeInBits();
654 return (LScalarSize < CastScalarSize) ||
655 (CastScalarSize >= 32);
658 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
659 // profitable with the expansion for 64-bit since it's generally good to
661 // FIXME: These should really have the size as a parameter.
662 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
666 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
670 //===---------------------------------------------------------------------===//
672 //===---------------------------------------------------------------------===//
674 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
675 assert(VT.isFloatingPoint());
677 // Packed operations do not have a fabs modifier.
678 return VT == MVT::f32 || VT == MVT::f64 ||
679 (Subtarget->has16BitInsts() && VT == MVT::f16);
682 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
683 assert(VT.isFloatingPoint());
684 return VT == MVT::f32 || VT == MVT::f64 ||
685 (Subtarget->has16BitInsts() && VT == MVT::f16) ||
686 (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
689 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
695 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
696 // There are few operations which truly have vector input operands. Any vector
697 // operation is going to involve operations on each component, and a
698 // build_vector will be a copy per element, so it always makes sense to use a
699 // build_vector input in place of the extracted element to avoid a copy into a
702 // We should probably only do this if all users are extracts only, but this
703 // should be the common case.
707 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
708 // Truncate is just accessing a subregister.
710 unsigned SrcSize = Source.getSizeInBits();
711 unsigned DestSize = Dest.getSizeInBits();
713 return DestSize < SrcSize && DestSize % 32 == 0 ;
716 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
717 // Truncate is just accessing a subregister.
719 unsigned SrcSize = Source->getScalarSizeInBits();
720 unsigned DestSize = Dest->getScalarSizeInBits();
722 if (DestSize== 16 && Subtarget->has16BitInsts())
723 return SrcSize >= 32;
725 return DestSize < SrcSize && DestSize % 32 == 0;
728 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
729 unsigned SrcSize = Src->getScalarSizeInBits();
730 unsigned DestSize = Dest->getScalarSizeInBits();
732 if (SrcSize == 16 && Subtarget->has16BitInsts())
733 return DestSize >= 32;
735 return SrcSize == 32 && DestSize == 64;
738 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
739 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
740 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
741 // this will enable reducing 64-bit operations the 32-bit, which is always
745 return Dest == MVT::i32 ||Dest == MVT::i64 ;
747 return Src == MVT::i32 && Dest == MVT::i64;
750 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
751 return isZExtFree(Val.getValueType(), VT2);
754 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
755 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
756 // limited number of native 64-bit operations. Shrinking an operation to fit
757 // in a single 32-bit register should always be helpful. As currently used,
758 // this is much less general than the name suggests, and is only used in
759 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
760 // not profitable, and may actually be harmful.
761 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
764 //===---------------------------------------------------------------------===//
765 // TargetLowering Callbacks
766 //===---------------------------------------------------------------------===//
768 CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
769 bool IsVarArg) const {
773 /// The SelectionDAGBuilder will automatically promote function arguments
774 /// with illegal types. However, this does not work for the AMDGPU targets
775 /// since the function arguments are stored in memory as these illegal types.
776 /// In order to handle this properly we need to get the original types sizes
777 /// from the LLVM IR Function and fixup the ISD:InputArg values before
778 /// passing them to AnalyzeFormalArguments()
780 /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
781 /// input values across multiple registers. Each item in the Ins array
782 /// represents a single value that will be stored in regsters. Ins[x].VT is
783 /// the value type of the value that will be stored in the register, so
784 /// whatever SDNode we lower the argument to needs to be this type.
786 /// In order to correctly lower the arguments we need to know the size of each
787 /// argument. Since Ins[x].VT gives us the size of the register that will
788 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
789 /// for the orignal function argument so that we can deduce the correct memory
790 /// type to use for Ins[x]. In most cases the correct memory type will be
791 /// Ins[x].ArgVT. However, this will not always be the case. If, for example,
792 /// we have a kernel argument of type v8i8, this argument will be split into
793 /// 8 parts and each part will be represented by its own item in the Ins array.
794 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
795 /// the argument before it was split. From this, we deduce that the memory type
796 /// for each individual part is i8. We pass the memory type as LocVT to the
797 /// calling convention analysis function and the register type (Ins[x].VT) as
799 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(CCState &State,
800 const SmallVectorImpl<ISD::InputArg> &Ins) const {
801 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
802 const ISD::InputArg &In = Ins[i];
805 unsigned NumRegs = getNumRegisters(State.getContext(), In.ArgVT);
807 if (!Subtarget->isAmdHsaOS() &&
808 (In.ArgVT == MVT::i16 || In.ArgVT == MVT::i8 || In.ArgVT == MVT::f16)) {
809 // The ABI says the caller will extend these values to 32-bits.
810 MemVT = In.ArgVT.isInteger() ? MVT::i32 : MVT::f32;
811 } else if (NumRegs == 1) {
812 // This argument is not split, so the IR type is the memory type.
813 assert(!In.Flags.isSplit());
814 if (In.ArgVT.isExtended()) {
815 // We have an extended type, like i24, so we should just use the register type
820 } else if (In.ArgVT.isVector() && In.VT.isVector() &&
821 In.ArgVT.getScalarType() == In.VT.getScalarType()) {
822 assert(In.ArgVT.getVectorNumElements() > In.VT.getVectorNumElements());
823 // We have a vector value which has been split into a vector with
824 // the same scalar type, but fewer elements. This should handle
825 // all the floating-point vector types.
827 } else if (In.ArgVT.isVector() &&
828 In.ArgVT.getVectorNumElements() == NumRegs) {
829 // This arg has been split so that each element is stored in a separate
831 MemVT = In.ArgVT.getScalarType();
832 } else if (In.ArgVT.isExtended()) {
833 // We have an extended type, like i65.
836 unsigned MemoryBits = In.ArgVT.getStoreSizeInBits() / NumRegs;
837 assert(In.ArgVT.getStoreSizeInBits() % NumRegs == 0);
838 if (In.VT.isInteger()) {
839 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
840 } else if (In.VT.isVector()) {
841 assert(!In.VT.getScalarType().isFloatingPoint());
842 unsigned NumElements = In.VT.getVectorNumElements();
843 assert(MemoryBits % NumElements == 0);
844 // This vector type has been split into another vector type with
845 // a different elements size.
846 EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
847 MemoryBits / NumElements);
848 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
850 llvm_unreachable("cannot deduce memory type.");
854 // Convert one element vectors to scalar.
855 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
856 MemVT = MemVT.getScalarType();
858 if (MemVT.isExtended()) {
859 // This should really only happen if we have vec3 arguments
860 assert(MemVT.isVector() && MemVT.getVectorNumElements() == 3);
861 MemVT = MemVT.getPow2VectorType(State.getContext());
864 assert(MemVT.isSimple());
865 allocateKernArg(i, In.VT, MemVT.getSimpleVT(), CCValAssign::Full, In.Flags,
870 void AMDGPUTargetLowering::AnalyzeReturn(CCState &State,
871 const SmallVectorImpl<ISD::OutputArg> &Outs) const {
873 State.AnalyzeReturn(Outs, RetCC_SI);
877 AMDGPUTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
879 const SmallVectorImpl<ISD::OutputArg> &Outs,
880 const SmallVectorImpl<SDValue> &OutVals,
881 const SDLoc &DL, SelectionDAG &DAG) const {
882 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
885 //===---------------------------------------------------------------------===//
886 // Target specific lowering
887 //===---------------------------------------------------------------------===//
889 /// Selects the correct CCAssignFn for a given CallingConvention value.
890 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
894 case CallingConv::AMDGPU_KERNEL:
895 case CallingConv::SPIR_KERNEL:
896 return CC_AMDGPU_Kernel;
897 case CallingConv::AMDGPU_VS:
898 case CallingConv::AMDGPU_GS:
899 case CallingConv::AMDGPU_PS:
900 case CallingConv::AMDGPU_CS:
903 report_fatal_error("Unsupported calling convention.");
907 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
908 SmallVectorImpl<SDValue> &InVals) const {
909 SDValue Callee = CLI.Callee;
910 SelectionDAG &DAG = CLI.DAG;
912 const Function &Fn = *DAG.getMachineFunction().getFunction();
914 StringRef FuncName("<unknown>");
916 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
917 FuncName = G->getSymbol();
918 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
919 FuncName = G->getGlobal()->getName();
921 DiagnosticInfoUnsupported NoCalls(
922 Fn, "unsupported call to function " + FuncName, CLI.DL.getDebugLoc());
923 DAG.getContext()->diagnose(NoCalls);
925 if (!CLI.IsTailCall) {
926 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
927 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
930 return DAG.getEntryNode();
933 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
934 SelectionDAG &DAG) const {
935 const Function &Fn = *DAG.getMachineFunction().getFunction();
937 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
938 SDLoc(Op).getDebugLoc());
939 DAG.getContext()->diagnose(NoDynamicAlloca);
940 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
941 return DAG.getMergeValues(Ops, SDLoc());
944 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
945 SelectionDAG &DAG) const {
946 switch (Op.getOpcode()) {
948 Op->print(errs(), &DAG);
949 llvm_unreachable("Custom lowering code for this"
950 "instruction is not implemented yet!");
952 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
953 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
954 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
955 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
956 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
957 case ISD::FREM: return LowerFREM(Op, DAG);
958 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
959 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
960 case ISD::FRINT: return LowerFRINT(Op, DAG);
961 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
962 case ISD::FROUND: return LowerFROUND(Op, DAG);
963 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
964 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
965 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
966 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
967 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
968 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
970 case ISD::CTLZ_ZERO_UNDEF:
971 return LowerCTLZ(Op, DAG);
972 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
977 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
978 SmallVectorImpl<SDValue> &Results,
979 SelectionDAG &DAG) const {
980 switch (N->getOpcode()) {
981 case ISD::SIGN_EXTEND_INREG:
982 // Different parts of legalization seem to interpret which type of
983 // sign_extend_inreg is the one to check for custom lowering. The extended
984 // from type is what really matters, but some places check for custom
985 // lowering of the result type. This results in trying to use
986 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
987 // nothing here and let the illegal result integer be handled normally.
994 static bool hasDefinedInitializer(const GlobalValue *GV) {
995 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
996 if (!GVar || !GVar->hasInitializer())
999 return !isa<UndefValue>(GVar->getInitializer());
1002 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1004 SelectionDAG &DAG) const {
1006 const DataLayout &DL = DAG.getDataLayout();
1007 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1008 const GlobalValue *GV = G->getGlobal();
1010 if (G->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS) {
1011 // XXX: What does the value of G->getOffset() mean?
1012 assert(G->getOffset() == 0 &&
1013 "Do not know what to do with an non-zero offset");
1015 // TODO: We could emit code to handle the initialization somewhere.
1016 if (!hasDefinedInitializer(GV)) {
1017 unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1018 return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1022 const Function &Fn = *DAG.getMachineFunction().getFunction();
1023 DiagnosticInfoUnsupported BadInit(
1024 Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1025 DAG.getContext()->diagnose(BadInit);
1029 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1030 SelectionDAG &DAG) const {
1031 SmallVector<SDValue, 8> Args;
1033 for (const SDUse &U : Op->ops())
1034 DAG.ExtractVectorElements(U.get(), Args);
1036 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1039 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1040 SelectionDAG &DAG) const {
1042 SmallVector<SDValue, 8> Args;
1043 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1044 EVT VT = Op.getValueType();
1045 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1046 VT.getVectorNumElements());
1048 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1051 /// \brief Generate Min/Max node
1052 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1053 SDValue LHS, SDValue RHS,
1054 SDValue True, SDValue False,
1056 DAGCombinerInfo &DCI) const {
1057 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1060 SelectionDAG &DAG = DCI.DAG;
1061 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1070 case ISD::SETFALSE2:
1079 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1080 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1086 // Ordered. Assume ordered for undefined.
1088 // Only do this after legalization to avoid interfering with other combines
1089 // which might occur.
1090 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1091 !DCI.isCalledByLegalizer())
1094 // We need to permute the operands to get the correct NaN behavior. The
1095 // selected operand is the second one based on the failing compare with NaN,
1096 // so permute it based on the compare type the hardware uses.
1098 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1099 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1104 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1105 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1111 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1112 !DCI.isCalledByLegalizer())
1116 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1117 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1119 case ISD::SETCC_INVALID:
1120 llvm_unreachable("Invalid setcc condcode!");
1125 std::pair<SDValue, SDValue>
1126 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1129 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1131 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1132 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1134 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1135 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1137 return std::make_pair(Lo, Hi);
1140 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1143 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1144 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1145 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1148 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1151 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1152 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1153 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1156 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1157 SelectionDAG &DAG) const {
1158 LoadSDNode *Load = cast<LoadSDNode>(Op);
1159 EVT VT = Op.getValueType();
1162 // If this is a 2 element vector, we really want to scalarize and not create
1163 // weird 1 element vectors.
1164 if (VT.getVectorNumElements() == 2)
1165 return scalarizeVectorLoad(Load, DAG);
1167 SDValue BasePtr = Load->getBasePtr();
1168 EVT PtrVT = BasePtr.getValueType();
1169 EVT MemVT = Load->getMemoryVT();
1172 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1175 EVT LoMemVT, HiMemVT;
1178 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1179 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1180 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1182 unsigned Size = LoMemVT.getStoreSize();
1183 unsigned BaseAlign = Load->getAlignment();
1184 unsigned HiAlign = MinAlign(BaseAlign, Size);
1186 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1187 Load->getChain(), BasePtr, SrcValue, LoMemVT,
1188 BaseAlign, Load->getMemOperand()->getFlags());
1189 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1190 DAG.getConstant(Size, SL, PtrVT));
1192 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1193 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1194 HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1197 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1198 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1199 LoLoad.getValue(1), HiLoad.getValue(1))
1202 return DAG.getMergeValues(Ops, SL);
1205 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1206 SelectionDAG &DAG) const {
1207 StoreSDNode *Store = cast<StoreSDNode>(Op);
1208 SDValue Val = Store->getValue();
1209 EVT VT = Val.getValueType();
1211 // If this is a 2 element vector, we really want to scalarize and not create
1212 // weird 1 element vectors.
1213 if (VT.getVectorNumElements() == 2)
1214 return scalarizeVectorStore(Store, DAG);
1216 EVT MemVT = Store->getMemoryVT();
1217 SDValue Chain = Store->getChain();
1218 SDValue BasePtr = Store->getBasePtr();
1222 EVT LoMemVT, HiMemVT;
1225 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1226 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1227 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1229 EVT PtrVT = BasePtr.getValueType();
1230 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1231 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1234 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1235 unsigned BaseAlign = Store->getAlignment();
1236 unsigned Size = LoMemVT.getStoreSize();
1237 unsigned HiAlign = MinAlign(BaseAlign, Size);
1240 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1241 Store->getMemOperand()->getFlags());
1243 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1244 HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1246 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1249 // This is a shortcut for integer division because we have fast i32<->f32
1250 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1251 // float is enough to accurately represent up to a 24-bit signed integer.
1252 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1255 EVT VT = Op.getValueType();
1256 SDValue LHS = Op.getOperand(0);
1257 SDValue RHS = Op.getOperand(1);
1258 MVT IntVT = MVT::i32;
1259 MVT FltVT = MVT::f32;
1261 unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1262 if (LHSSignBits < 9)
1265 unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1266 if (RHSSignBits < 9)
1269 unsigned BitSize = VT.getSizeInBits();
1270 unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1271 unsigned DivBits = BitSize - SignBits;
1275 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1276 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1278 SDValue jq = DAG.getConstant(1, DL, IntVT);
1281 // char|short jq = ia ^ ib;
1282 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1284 // jq = jq >> (bitsize - 2)
1285 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1286 DAG.getConstant(BitSize - 2, DL, VT));
1289 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1292 // int ia = (int)LHS;
1295 // int ib, (int)RHS;
1298 // float fa = (float)ia;
1299 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1301 // float fb = (float)ib;
1302 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1304 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1305 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1308 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1310 // float fqneg = -fq;
1311 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1313 // float fr = mad(fqneg, fb, fa);
1314 unsigned OpCode = Subtarget->hasFP32Denormals() ?
1315 (unsigned)AMDGPUISD::FMAD_FTZ :
1316 (unsigned)ISD::FMAD;
1317 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1319 // int iq = (int)fq;
1320 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1323 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1326 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1328 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1330 // int cv = fr >= fb;
1331 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1333 // jq = (cv ? jq : 0);
1334 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1337 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1339 // Rem needs compensation, it's easier to recompute it
1340 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1341 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1343 // Truncate to number of bits this divide really is.
1346 = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1347 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1348 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1350 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1351 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1352 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1355 return DAG.getMergeValues({ Div, Rem }, DL);
1358 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1360 SmallVectorImpl<SDValue> &Results) const {
1361 assert(Op.getValueType() == MVT::i64);
1364 EVT VT = Op.getValueType();
1365 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1367 SDValue one = DAG.getConstant(1, DL, HalfVT);
1368 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1371 SDValue LHS = Op.getOperand(0);
1372 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1373 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1375 SDValue RHS = Op.getOperand(1);
1376 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1377 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1379 if (VT == MVT::i64 &&
1380 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1381 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1383 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1386 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), zero});
1387 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), zero});
1389 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1390 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1394 // Get Speculative values
1395 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1396 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1398 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1399 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, zero});
1400 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1402 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1403 SDValue DIV_Lo = zero;
1405 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1407 for (unsigned i = 0; i < halfBitWidth; ++i) {
1408 const unsigned bitPos = halfBitWidth - i - 1;
1409 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1410 // Get value of high bit
1411 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1412 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1413 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1416 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1418 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1420 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1421 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1423 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1426 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1427 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1430 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1431 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1432 Results.push_back(DIV);
1433 Results.push_back(REM);
1436 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1437 SelectionDAG &DAG) const {
1439 EVT VT = Op.getValueType();
1441 if (VT == MVT::i64) {
1442 SmallVector<SDValue, 2> Results;
1443 LowerUDIVREM64(Op, DAG, Results);
1444 return DAG.getMergeValues(Results, DL);
1447 if (VT == MVT::i32) {
1448 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1452 SDValue Num = Op.getOperand(0);
1453 SDValue Den = Op.getOperand(1);
1455 // RCP = URECIP(Den) = 2^32 / Den + e
1456 // e is rounding error.
1457 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1459 // RCP_LO = mul(RCP, Den) */
1460 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1462 // RCP_HI = mulhu (RCP, Den) */
1463 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1465 // NEG_RCP_LO = -RCP_LO
1466 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1469 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1470 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1473 // Calculate the rounding error from the URECIP instruction
1474 // E = mulhu(ABS_RCP_LO, RCP)
1475 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1477 // RCP_A_E = RCP + E
1478 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1480 // RCP_S_E = RCP - E
1481 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1483 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1484 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1487 // Quotient = mulhu(Tmp0, Num)
1488 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1490 // Num_S_Remainder = Quotient * Den
1491 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1493 // Remainder = Num - Num_S_Remainder
1494 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1496 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1497 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1498 DAG.getConstant(-1, DL, VT),
1499 DAG.getConstant(0, DL, VT),
1501 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1502 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1504 DAG.getConstant(-1, DL, VT),
1505 DAG.getConstant(0, DL, VT),
1507 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1508 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1511 // Calculate Division result:
1513 // Quotient_A_One = Quotient + 1
1514 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1515 DAG.getConstant(1, DL, VT));
1517 // Quotient_S_One = Quotient - 1
1518 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1519 DAG.getConstant(1, DL, VT));
1521 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1522 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1523 Quotient, Quotient_A_One, ISD::SETEQ);
1525 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1526 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1527 Quotient_S_One, Div, ISD::SETEQ);
1529 // Calculate Rem result:
1531 // Remainder_S_Den = Remainder - Den
1532 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1534 // Remainder_A_Den = Remainder + Den
1535 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1537 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1538 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1539 Remainder, Remainder_S_Den, ISD::SETEQ);
1541 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1542 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1543 Remainder_A_Den, Rem, ISD::SETEQ);
1548 return DAG.getMergeValues(Ops, DL);
1551 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1552 SelectionDAG &DAG) const {
1554 EVT VT = Op.getValueType();
1556 SDValue LHS = Op.getOperand(0);
1557 SDValue RHS = Op.getOperand(1);
1559 SDValue Zero = DAG.getConstant(0, DL, VT);
1560 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1562 if (VT == MVT::i32) {
1563 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1567 if (VT == MVT::i64 &&
1568 DAG.ComputeNumSignBits(LHS) > 32 &&
1569 DAG.ComputeNumSignBits(RHS) > 32) {
1570 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1573 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1574 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1575 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1578 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1579 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1581 return DAG.getMergeValues(Res, DL);
1584 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1585 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1586 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1587 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1589 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1590 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1592 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1593 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1595 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1596 SDValue Rem = Div.getValue(1);
1598 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1599 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1601 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1602 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1608 return DAG.getMergeValues(Res, DL);
1611 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1612 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1614 EVT VT = Op.getValueType();
1615 SDValue X = Op.getOperand(0);
1616 SDValue Y = Op.getOperand(1);
1618 // TODO: Should this propagate fast-math-flags?
1620 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1621 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1622 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1624 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1627 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1629 SDValue Src = Op.getOperand(0);
1631 // result = trunc(src)
1632 // if (src > 0.0 && src != result)
1635 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1637 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1638 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1641 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1643 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1644 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1645 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1647 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1648 // TODO: Should this propagate fast-math-flags?
1649 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1652 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
1653 SelectionDAG &DAG) {
1654 const unsigned FractBits = 52;
1655 const unsigned ExpBits = 11;
1657 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1659 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1660 DAG.getConstant(ExpBits, SL, MVT::i32));
1661 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1662 DAG.getConstant(1023, SL, MVT::i32));
1667 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1669 SDValue Src = Op.getOperand(0);
1671 assert(Op.getValueType() == MVT::f64);
1673 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1674 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1676 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1678 // Extract the upper half, since this is where we will find the sign and
1680 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1682 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1684 const unsigned FractBits = 52;
1686 // Extract the sign bit.
1687 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1688 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1690 // Extend back to to 64-bits.
1691 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
1692 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1694 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1695 const SDValue FractMask
1696 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1698 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1699 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1700 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1703 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1705 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1707 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1708 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1710 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1711 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1713 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1716 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1718 SDValue Src = Op.getOperand(0);
1720 assert(Op.getValueType() == MVT::f64);
1722 APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
1723 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
1724 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1726 // TODO: Should this propagate fast-math-flags?
1728 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1729 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1731 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1733 APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
1734 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
1737 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1738 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1740 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1743 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1744 // FNEARBYINT and FRINT are the same, except in their handling of FP
1745 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1746 // rint, so just treat them as equivalent.
1747 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1750 // XXX - May require not supporting f32 denormals?
1752 // Don't handle v2f16. The extra instructions to scalarize and repack around the
1753 // compare and vselect end up producing worse code than scalarizing the whole
1755 SDValue AMDGPUTargetLowering::LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const {
1757 SDValue X = Op.getOperand(0);
1758 EVT VT = Op.getValueType();
1760 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
1762 // TODO: Should this propagate fast-math-flags?
1764 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
1766 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
1768 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
1769 const SDValue One = DAG.getConstantFP(1.0, SL, VT);
1770 const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
1772 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
1775 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1777 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
1779 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
1781 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
1784 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
1786 SDValue X = Op.getOperand(0);
1788 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
1790 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1791 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1792 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
1793 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
1795 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1797 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1799 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
1801 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1803 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
1806 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
1807 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
1808 DAG.getConstant(INT64_C(0x0008000000000000), SL,
1812 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
1813 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
1814 DAG.getConstant(0, SL, MVT::i64), Tmp0,
1817 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
1818 D, DAG.getConstant(0, SL, MVT::i64));
1819 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
1821 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
1822 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
1824 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1825 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1826 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
1828 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
1830 DAG.getConstantFP(1.0, SL, MVT::f64),
1831 DAG.getConstantFP(0.0, SL, MVT::f64));
1833 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
1835 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
1836 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
1841 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
1842 EVT VT = Op.getValueType();
1844 if (VT == MVT::f32 || VT == MVT::f16)
1845 return LowerFROUND32_16(Op, DAG);
1848 return LowerFROUND64(Op, DAG);
1850 llvm_unreachable("unhandled type");
1853 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1855 SDValue Src = Op.getOperand(0);
1857 // result = trunc(src);
1858 // if (src < 0.0 && src != result)
1861 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1863 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1864 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
1867 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1869 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1870 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1871 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1873 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1874 // TODO: Should this propagate fast-math-flags?
1875 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1878 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
1880 SDValue Src = Op.getOperand(0);
1881 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
1883 if (ZeroUndef && Src.getValueType() == MVT::i32)
1884 return DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Src);
1886 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1888 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1889 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1891 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1892 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1894 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1895 *DAG.getContext(), MVT::i32);
1897 SDValue Hi0 = DAG.getSetCC(SL, SetCCVT, Hi, Zero, ISD::SETEQ);
1899 SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo);
1900 SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);
1902 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
1903 SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32);
1905 // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
1906 SDValue NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0, Add, CtlzHi);
1909 // Test if the full 64-bit input is zero.
1911 // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
1912 // which we probably don't want.
1913 SDValue Lo0 = DAG.getSetCC(SL, SetCCVT, Lo, Zero, ISD::SETEQ);
1914 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0);
1916 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
1917 // with the same cycles, otherwise it is slower.
1918 // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
1919 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
1921 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
1923 // The instruction returns -1 for 0 input, but the defined intrinsic
1924 // behavior is to return the number of bits.
1925 NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32,
1926 SrcIsZero, Bits32, NewCtlz);
1929 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewCtlz);
1932 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
1933 bool Signed) const {
1937 // uint lz = clz(u);
1938 // uint e = (u != 0) ? 127U + 63U - lz : 0;
1939 // u = (u << lz) & 0x7fffffffffffffffUL;
1940 // ulong t = u & 0xffffffffffUL;
1941 // uint v = (e << 23) | (uint)(u >> 40);
1942 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
1943 // return as_float(v + r);
1948 // long s = l >> 63;
1949 // float r = cul2f((l + s) ^ s);
1950 // return s ? -r : r;
1954 SDValue Src = Op.getOperand(0);
1959 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
1960 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
1962 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
1963 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
1966 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1967 *DAG.getContext(), MVT::f32);
1970 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
1971 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
1972 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
1973 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
1975 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
1976 SDValue E = DAG.getSelect(SL, MVT::i32,
1977 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
1978 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
1981 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
1982 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
1983 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
1985 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
1986 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
1988 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
1989 U, DAG.getConstant(40, SL, MVT::i64));
1991 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
1992 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
1993 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
1995 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
1996 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
1997 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
1999 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2001 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2003 SDValue R = DAG.getSelect(SL, MVT::i32,
2006 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2007 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2008 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2013 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2014 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2017 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2018 bool Signed) const {
2020 SDValue Src = Op.getOperand(0);
2022 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2024 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2025 DAG.getConstant(0, SL, MVT::i32));
2026 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2027 DAG.getConstant(1, SL, MVT::i32));
2029 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2032 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2034 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2035 DAG.getConstant(32, SL, MVT::i32));
2036 // TODO: Should this propagate fast-math-flags?
2037 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2040 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2041 SelectionDAG &DAG) const {
2042 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2043 "operation should be legal");
2045 // TODO: Factor out code common with LowerSINT_TO_FP.
2047 EVT DestVT = Op.getValueType();
2048 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2050 SDValue Src = Op.getOperand(0);
2052 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2053 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2055 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2060 if (DestVT == MVT::f32)
2061 return LowerINT_TO_FP32(Op, DAG, false);
2063 assert(DestVT == MVT::f64);
2064 return LowerINT_TO_FP64(Op, DAG, false);
2067 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2068 SelectionDAG &DAG) const {
2069 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2070 "operation should be legal");
2072 // TODO: Factor out code common with LowerUINT_TO_FP.
2074 EVT DestVT = Op.getValueType();
2075 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2077 SDValue Src = Op.getOperand(0);
2079 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2080 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2082 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2087 if (DestVT == MVT::f32)
2088 return LowerINT_TO_FP32(Op, DAG, true);
2090 assert(DestVT == MVT::f64);
2091 return LowerINT_TO_FP64(Op, DAG, true);
2094 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2095 bool Signed) const {
2098 SDValue Src = Op.getOperand(0);
2100 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2102 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2104 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2106 // TODO: Should this propagate fast-math-flags?
2107 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2109 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2112 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2114 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2115 MVT::i32, FloorMul);
2116 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2118 SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2120 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2123 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2125 SDValue N0 = Op.getOperand(0);
2127 // Convert to target node to get known bits
2128 if (N0.getValueType() == MVT::f32)
2129 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2131 if (getTargetMachine().Options.UnsafeFPMath) {
2132 // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2136 assert(N0.getSimpleValueType() == MVT::f64);
2138 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2139 const unsigned ExpMask = 0x7ff;
2140 const unsigned ExpBiasf64 = 1023;
2141 const unsigned ExpBiasf16 = 15;
2142 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2143 SDValue One = DAG.getConstant(1, DL, MVT::i32);
2144 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2145 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2146 DAG.getConstant(32, DL, MVT::i64));
2147 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2148 U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2149 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2150 DAG.getConstant(20, DL, MVT::i64));
2151 E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2152 DAG.getConstant(ExpMask, DL, MVT::i32));
2153 // Subtract the fp64 exponent bias (1023) to get the real exponent and
2154 // add the f16 bias (15) to get the biased exponent for the f16 format.
2155 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2156 DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2158 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2159 DAG.getConstant(8, DL, MVT::i32));
2160 M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2161 DAG.getConstant(0xffe, DL, MVT::i32));
2163 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2164 DAG.getConstant(0x1ff, DL, MVT::i32));
2165 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2167 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2168 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2170 // (M != 0 ? 0x0200 : 0) | 0x7c00;
2171 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2172 DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2173 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2175 // N = M | (E << 12);
2176 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2177 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2178 DAG.getConstant(12, DL, MVT::i32)));
2180 // B = clamp(1-E, 0, 13);
2181 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2183 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2184 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2185 DAG.getConstant(13, DL, MVT::i32));
2187 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2188 DAG.getConstant(0x1000, DL, MVT::i32));
2190 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2191 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2192 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2193 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2195 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2196 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2197 DAG.getConstant(0x7, DL, MVT::i32));
2198 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2199 DAG.getConstant(2, DL, MVT::i32));
2200 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2201 One, Zero, ISD::SETEQ);
2202 SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2203 One, Zero, ISD::SETGT);
2204 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2205 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2207 V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2208 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2209 V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2212 // Extract the sign bit.
2213 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2214 DAG.getConstant(16, DL, MVT::i32));
2215 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2216 DAG.getConstant(0x8000, DL, MVT::i32));
2218 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2219 return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2222 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2223 SelectionDAG &DAG) const {
2224 SDValue Src = Op.getOperand(0);
2226 // TODO: Factor out code common with LowerFP_TO_UINT.
2228 EVT SrcVT = Src.getValueType();
2229 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2232 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2234 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2239 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2240 return LowerFP64_TO_INT(Op, DAG, true);
2245 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2246 SelectionDAG &DAG) const {
2247 SDValue Src = Op.getOperand(0);
2249 // TODO: Factor out code common with LowerFP_TO_SINT.
2251 EVT SrcVT = Src.getValueType();
2252 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2255 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2257 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2262 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2263 return LowerFP64_TO_INT(Op, DAG, false);
2268 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2269 SelectionDAG &DAG) const {
2270 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2271 MVT VT = Op.getSimpleValueType();
2272 MVT ScalarVT = VT.getScalarType();
2274 assert(VT.isVector());
2276 SDValue Src = Op.getOperand(0);
2279 // TODO: Don't scalarize on Evergreen?
2280 unsigned NElts = VT.getVectorNumElements();
2281 SmallVector<SDValue, 8> Args;
2282 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2284 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2285 for (unsigned I = 0; I < NElts; ++I)
2286 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2288 return DAG.getBuildVector(VT, DL, Args);
2291 //===----------------------------------------------------------------------===//
2292 // Custom DAG optimizations
2293 //===----------------------------------------------------------------------===//
2295 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2296 APInt KnownZero, KnownOne;
2297 EVT VT = Op.getValueType();
2298 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2300 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2303 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2304 EVT VT = Op.getValueType();
2306 // In order for this to be a signed 24-bit value, bit 23, must
2308 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2309 // as unsigned 24-bit values.
2310 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2313 static bool simplifyI24(SDNode *Node24, unsigned OpIdx,
2314 TargetLowering::DAGCombinerInfo &DCI) {
2316 SelectionDAG &DAG = DCI.DAG;
2317 SDValue Op = Node24->getOperand(OpIdx);
2318 EVT VT = Op.getValueType();
2320 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2321 APInt KnownZero, KnownOne;
2322 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2323 if (TLO.SimplifyDemandedBits(Node24, OpIdx, Demanded, DCI))
2329 template <typename IntTy>
2330 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2331 uint32_t Width, const SDLoc &DL) {
2332 if (Width + Offset < 32) {
2333 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2334 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2335 return DAG.getConstant(Result, DL, MVT::i32);
2338 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2341 static bool hasVolatileUser(SDNode *Val) {
2342 for (SDNode *U : Val->uses()) {
2343 if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2344 if (M->isVolatile())
2352 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2353 // i32 vectors are the canonical memory type.
2354 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2357 if (!VT.isByteSized())
2360 unsigned Size = VT.getStoreSize();
2362 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2365 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2371 // Replace load of an illegal type with a store of a bitcast to a friendlier
2373 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2374 DAGCombinerInfo &DCI) const {
2375 if (!DCI.isBeforeLegalize())
2378 LoadSDNode *LN = cast<LoadSDNode>(N);
2379 if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2383 SelectionDAG &DAG = DCI.DAG;
2384 EVT VT = LN->getMemoryVT();
2386 unsigned Size = VT.getStoreSize();
2387 unsigned Align = LN->getAlignment();
2388 if (Align < Size && isTypeLegal(VT)) {
2390 unsigned AS = LN->getAddressSpace();
2392 // Expand unaligned loads earlier than legalization. Due to visitation order
2393 // problems during legalization, the emitted instructions to pack and unpack
2394 // the bytes again are not eliminated in the case of an unaligned copy.
2395 if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2397 return scalarizeVectorLoad(LN, DAG);
2400 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2401 return DAG.getMergeValues(Ops, SDLoc(N));
2408 if (!shouldCombineMemoryType(VT))
2411 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2414 = DAG.getLoad(NewVT, SL, LN->getChain(),
2415 LN->getBasePtr(), LN->getMemOperand());
2417 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2418 DCI.CombineTo(N, BC, NewLoad.getValue(1));
2419 return SDValue(N, 0);
2422 // Replace store of an illegal type with a store of a bitcast to a friendlier
2424 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2425 DAGCombinerInfo &DCI) const {
2426 if (!DCI.isBeforeLegalize())
2429 StoreSDNode *SN = cast<StoreSDNode>(N);
2430 if (SN->isVolatile() || !ISD::isNormalStore(SN))
2433 EVT VT = SN->getMemoryVT();
2434 unsigned Size = VT.getStoreSize();
2437 SelectionDAG &DAG = DCI.DAG;
2438 unsigned Align = SN->getAlignment();
2439 if (Align < Size && isTypeLegal(VT)) {
2441 unsigned AS = SN->getAddressSpace();
2443 // Expand unaligned stores earlier than legalization. Due to visitation
2444 // order problems during legalization, the emitted instructions to pack and
2445 // unpack the bytes again are not eliminated in the case of an unaligned
2447 if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2449 return scalarizeVectorStore(SN, DAG);
2451 return expandUnalignedStore(SN, DAG);
2458 if (!shouldCombineMemoryType(VT))
2461 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2462 SDValue Val = SN->getValue();
2464 //DCI.AddToWorklist(Val.getNode());
2466 bool OtherUses = !Val.hasOneUse();
2467 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2469 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2470 DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2473 return DAG.getStore(SN->getChain(), SL, CastVal,
2474 SN->getBasePtr(), SN->getMemOperand());
2477 SDValue AMDGPUTargetLowering::performClampCombine(SDNode *N,
2478 DAGCombinerInfo &DCI) const {
2479 ConstantFPSDNode *CSrc = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
2483 const APFloat &F = CSrc->getValueAPF();
2484 APFloat Zero = APFloat::getZero(F.getSemantics());
2485 APFloat::cmpResult Cmp0 = F.compare(Zero);
2486 if (Cmp0 == APFloat::cmpLessThan ||
2487 (Cmp0 == APFloat::cmpUnordered && Subtarget->enableDX10Clamp())) {
2488 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0));
2491 APFloat One(F.getSemantics(), "1.0");
2492 APFloat::cmpResult Cmp1 = F.compare(One);
2493 if (Cmp1 == APFloat::cmpGreaterThan)
2494 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
2496 return SDValue(CSrc, 0);
2499 /// Split the 64-bit value \p LHS into two 32-bit components, and perform the
2500 /// binary operation \p Opc to it with the corresponding constant operands.
2501 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
2502 DAGCombinerInfo &DCI, const SDLoc &SL,
2503 unsigned Opc, SDValue LHS,
2504 uint32_t ValLo, uint32_t ValHi) const {
2505 SelectionDAG &DAG = DCI.DAG;
2507 std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
2509 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
2510 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
2512 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
2513 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
2515 // Re-visit the ands. It's possible we eliminated one of them and it could
2516 // simplify the vector.
2517 DCI.AddToWorklist(Lo.getNode());
2518 DCI.AddToWorklist(Hi.getNode());
2520 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
2521 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2524 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2525 DAGCombinerInfo &DCI) const {
2526 if (N->getValueType(0) != MVT::i64)
2529 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
2531 // On some subtargets, 64-bit shift is a quarter rate instruction. In the
2532 // common case, splitting this into a move and a 32-bit shift is faster and
2533 // the same code size.
2534 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2538 unsigned RHSVal = RHS->getZExtValue();
2542 SDValue LHS = N->getOperand(0);
2545 SelectionDAG &DAG = DCI.DAG;
2547 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
2549 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2550 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
2552 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2554 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
2555 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2558 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
2559 DAGCombinerInfo &DCI) const {
2560 if (N->getValueType(0) != MVT::i64)
2563 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2567 SelectionDAG &DAG = DCI.DAG;
2569 unsigned RHSVal = RHS->getZExtValue();
2571 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
2573 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2574 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2575 DAG.getConstant(31, SL, MVT::i32));
2577 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
2578 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2581 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
2583 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2584 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2585 DAG.getConstant(31, SL, MVT::i32));
2586 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
2587 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2593 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
2594 DAGCombinerInfo &DCI) const {
2595 if (N->getValueType(0) != MVT::i64)
2598 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2602 unsigned ShiftAmt = RHS->getZExtValue();
2606 // srl i64:x, C for C >= 32
2608 // build_pair (srl hi_32(x), C - 32), 0
2610 SelectionDAG &DAG = DCI.DAG;
2613 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2614 SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2616 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
2617 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,
2620 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
2621 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
2623 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
2625 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
2628 // We need to specifically handle i64 mul here to avoid unnecessary conversion
2629 // instructions. If we only match on the legalized i64 mul expansion,
2630 // SimplifyDemandedBits will be unable to remove them because there will be
2631 // multiple uses due to the separate mul + mulh[su].
2632 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
2633 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
2635 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
2636 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
2639 // Because we want to eliminate extension instructions before the
2640 // operation, we need to create a single user here (i.e. not the separate
2641 // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
2643 unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
2645 SDValue Mul = DAG.getNode(MulOpc, SL,
2646 DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
2648 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
2649 Mul.getValue(0), Mul.getValue(1));
2652 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2653 DAGCombinerInfo &DCI) const {
2654 EVT VT = N->getValueType(0);
2656 unsigned Size = VT.getSizeInBits();
2657 if (VT.isVector() || Size > 64)
2660 // There are i16 integer mul/mad.
2661 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
2664 SelectionDAG &DAG = DCI.DAG;
2667 SDValue N0 = N->getOperand(0);
2668 SDValue N1 = N->getOperand(1);
2671 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2672 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2673 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2674 Mul = getMul24(DAG, DL, N0, N1, Size, false);
2675 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2676 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2677 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2678 Mul = getMul24(DAG, DL, N0, N1, Size, true);
2683 // We need to use sext even for MUL_U24, because MUL_U24 is used
2684 // for signed multiply of 8 and 16-bit types.
2685 return DAG.getSExtOrTrunc(Mul, DL, VT);
2688 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
2689 DAGCombinerInfo &DCI) const {
2690 EVT VT = N->getValueType(0);
2692 if (!Subtarget->hasMulI24() || VT.isVector())
2695 SelectionDAG &DAG = DCI.DAG;
2698 SDValue N0 = N->getOperand(0);
2699 SDValue N1 = N->getOperand(1);
2701 if (!isI24(N0, DAG) || !isI24(N1, DAG))
2704 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2705 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2707 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
2708 DCI.AddToWorklist(Mulhi.getNode());
2709 return DAG.getSExtOrTrunc(Mulhi, DL, VT);
2712 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
2713 DAGCombinerInfo &DCI) const {
2714 EVT VT = N->getValueType(0);
2716 if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
2719 SelectionDAG &DAG = DCI.DAG;
2722 SDValue N0 = N->getOperand(0);
2723 SDValue N1 = N->getOperand(1);
2725 if (!isU24(N0, DAG) || !isU24(N1, DAG))
2728 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2729 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2731 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
2732 DCI.AddToWorklist(Mulhi.getNode());
2733 return DAG.getZExtOrTrunc(Mulhi, DL, VT);
2736 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
2737 SDNode *N, DAGCombinerInfo &DCI) const {
2738 SelectionDAG &DAG = DCI.DAG;
2740 // Simplify demanded bits before splitting into multiple users.
2741 if (simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI))
2744 SDValue N0 = N->getOperand(0);
2745 SDValue N1 = N->getOperand(1);
2747 bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
2749 unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
2750 unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
2754 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
2755 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
2756 return DAG.getMergeValues({ MulLo, MulHi }, SL);
2759 static bool isNegativeOne(SDValue Val) {
2760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
2761 return C->isAllOnesValue();
2765 static bool isCtlzOpc(unsigned Opc) {
2766 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2769 SDValue AMDGPUTargetLowering::getFFBH_U32(SelectionDAG &DAG,
2771 const SDLoc &DL) const {
2772 EVT VT = Op.getValueType();
2773 EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
2774 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
2775 LegalVT != MVT::i16))
2779 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
2781 SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, DL, MVT::i32, Op);
2783 FFBH = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBH);
2788 // The native instructions return -1 on 0 input. Optimize out a select that
2789 // produces -1 on 0.
2791 // TODO: If zero is not undef, we could also do this if the output is compared
2792 // against the bitwidth.
2794 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
2795 SDValue AMDGPUTargetLowering::performCtlzCombine(const SDLoc &SL, SDValue Cond,
2796 SDValue LHS, SDValue RHS,
2797 DAGCombinerInfo &DCI) const {
2798 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2799 if (!CmpRhs || !CmpRhs->isNullValue())
2802 SelectionDAG &DAG = DCI.DAG;
2803 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
2804 SDValue CmpLHS = Cond.getOperand(0);
2806 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
2807 if (CCOpcode == ISD::SETEQ &&
2808 isCtlzOpc(RHS.getOpcode()) &&
2809 RHS.getOperand(0) == CmpLHS &&
2810 isNegativeOne(LHS)) {
2811 return getFFBH_U32(DAG, CmpLHS, SL);
2814 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
2815 if (CCOpcode == ISD::SETNE &&
2816 isCtlzOpc(LHS.getOpcode()) &&
2817 LHS.getOperand(0) == CmpLHS &&
2818 isNegativeOne(RHS)) {
2819 return getFFBH_U32(DAG, CmpLHS, SL);
2825 static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI,
2831 SelectionDAG &DAG = DCI.DAG;
2832 EVT VT = N1.getValueType();
2834 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
2835 N1.getOperand(0), N2.getOperand(0));
2836 DCI.AddToWorklist(NewSelect.getNode());
2837 return DAG.getNode(Op, SL, VT, NewSelect);
2840 // Pull a free FP operation out of a select so it may fold into uses.
2842 // select c, (fneg x), (fneg y) -> fneg (select c, x, y)
2843 // select c, (fneg x), k -> fneg (select c, x, (fneg k))
2845 // select c, (fabs x), (fabs y) -> fabs (select c, x, y)
2846 // select c, (fabs x), +k -> fabs (select c, x, k)
2847 static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
2849 SelectionDAG &DAG = DCI.DAG;
2850 SDValue Cond = N.getOperand(0);
2851 SDValue LHS = N.getOperand(1);
2852 SDValue RHS = N.getOperand(2);
2854 EVT VT = N.getValueType();
2855 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
2856 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
2857 return distributeOpThroughSelect(DCI, LHS.getOpcode(),
2858 SDLoc(N), Cond, LHS, RHS);
2862 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
2863 std::swap(LHS, RHS);
2867 // TODO: Support vector constants.
2868 ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
2869 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
2871 // If one side is an fneg/fabs and the other is a constant, we can push the
2872 // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
2873 SDValue NewLHS = LHS.getOperand(0);
2874 SDValue NewRHS = RHS;
2876 // Careful: if the neg can be folded up, don't try to pull it back down.
2877 bool ShouldFoldNeg = true;
2879 if (NewLHS.hasOneUse()) {
2880 unsigned Opc = NewLHS.getOpcode();
2881 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
2882 ShouldFoldNeg = false;
2883 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
2884 ShouldFoldNeg = false;
2887 if (ShouldFoldNeg) {
2888 if (LHS.getOpcode() == ISD::FNEG)
2889 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
2890 else if (CRHS->isNegative())
2894 std::swap(NewLHS, NewRHS);
2896 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
2897 Cond, NewLHS, NewRHS);
2898 DCI.AddToWorklist(NewSelect.getNode());
2899 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
2907 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
2908 DAGCombinerInfo &DCI) const {
2909 if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
2912 SDValue Cond = N->getOperand(0);
2913 if (Cond.getOpcode() != ISD::SETCC)
2916 EVT VT = N->getValueType(0);
2917 SDValue LHS = Cond.getOperand(0);
2918 SDValue RHS = Cond.getOperand(1);
2919 SDValue CC = Cond.getOperand(2);
2921 SDValue True = N->getOperand(1);
2922 SDValue False = N->getOperand(2);
2924 if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
2925 SelectionDAG &DAG = DCI.DAG;
2926 if ((DAG.isConstantValueOfAnyType(True) ||
2927 DAG.isConstantValueOfAnyType(True)) &&
2928 (!DAG.isConstantValueOfAnyType(False) &&
2929 !DAG.isConstantValueOfAnyType(False))) {
2930 // Swap cmp + select pair to move constant to false input.
2931 // This will allow using VOPC cndmasks more often.
2932 // select (setcc x, y), k, x -> select (setcc y, x) x, x
2935 ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2936 LHS.getValueType().isInteger());
2938 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
2939 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
2942 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
2944 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
2945 // Revisit this node so we can catch min3/max3/med3 patterns.
2946 //DCI.AddToWorklist(MinMax.getNode());
2951 // There's no reason to not do this if the condition has other uses.
2952 return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
2955 static bool isConstantFPZero(SDValue N) {
2956 if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N))
2957 return C->isZero() && !C->isNegative();
2961 static unsigned inverseMinMax(unsigned Opc) {
2964 return ISD::FMINNUM;
2966 return ISD::FMAXNUM;
2967 case AMDGPUISD::FMAX_LEGACY:
2968 return AMDGPUISD::FMIN_LEGACY;
2969 case AMDGPUISD::FMIN_LEGACY:
2970 return AMDGPUISD::FMAX_LEGACY;
2972 llvm_unreachable("invalid min/max opcode");
2976 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
2977 DAGCombinerInfo &DCI) const {
2978 SelectionDAG &DAG = DCI.DAG;
2979 SDValue N0 = N->getOperand(0);
2980 EVT VT = N->getValueType(0);
2982 unsigned Opc = N0.getOpcode();
2984 // If the input has multiple uses and we can either fold the negate down, or
2985 // the other uses cannot, give up. This both prevents unprofitable
2986 // transformations and infinite loops: we won't repeatedly try to fold around
2987 // a negate that has no 'good' form.
2988 if (N0.hasOneUse()) {
2989 // This may be able to fold into the source, but at a code size cost. Don't
2990 // fold if the fold into the user is free.
2991 if (allUsesHaveSourceMods(N, 0))
2994 if (fnegFoldsIntoOp(Opc) &&
2995 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))
3002 if (!mayIgnoreSignedZero(N0))
3005 // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3006 SDValue LHS = N0.getOperand(0);
3007 SDValue RHS = N0.getOperand(1);
3009 if (LHS.getOpcode() != ISD::FNEG)
3010 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3012 LHS = LHS.getOperand(0);
3014 if (RHS.getOpcode() != ISD::FNEG)
3015 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3017 RHS = RHS.getOperand(0);
3019 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3020 if (!N0.hasOneUse())
3021 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3025 case AMDGPUISD::FMUL_LEGACY: {
3026 // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3027 // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3028 SDValue LHS = N0.getOperand(0);
3029 SDValue RHS = N0.getOperand(1);
3031 if (LHS.getOpcode() == ISD::FNEG)
3032 LHS = LHS.getOperand(0);
3033 else if (RHS.getOpcode() == ISD::FNEG)
3034 RHS = RHS.getOperand(0);
3036 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3038 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3039 if (!N0.hasOneUse())
3040 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3045 if (!mayIgnoreSignedZero(N0))
3048 // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3049 SDValue LHS = N0.getOperand(0);
3050 SDValue MHS = N0.getOperand(1);
3051 SDValue RHS = N0.getOperand(2);
3053 if (LHS.getOpcode() == ISD::FNEG)
3054 LHS = LHS.getOperand(0);
3055 else if (MHS.getOpcode() == ISD::FNEG)
3056 MHS = MHS.getOperand(0);
3058 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3060 if (RHS.getOpcode() != ISD::FNEG)
3061 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3063 RHS = RHS.getOperand(0);
3065 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3066 if (!N0.hasOneUse())
3067 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3072 case AMDGPUISD::FMAX_LEGACY:
3073 case AMDGPUISD::FMIN_LEGACY: {
3074 // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3075 // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3076 // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3077 // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3079 SDValue LHS = N0.getOperand(0);
3080 SDValue RHS = N0.getOperand(1);
3082 // 0 doesn't have a negated inline immediate.
3083 // TODO: Shouldn't fold 1/2pi either, and should be generalized to other
3085 if (isConstantFPZero(RHS))
3088 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3089 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3090 unsigned Opposite = inverseMinMax(Opc);
3092 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3093 if (!N0.hasOneUse())
3094 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3097 case ISD::FP_EXTEND:
3100 case ISD::FNEARBYINT: // XXX - Should fround be handled?
3102 case AMDGPUISD::RCP:
3103 case AMDGPUISD::RCP_LEGACY:
3104 case AMDGPUISD::SIN_HW: {
3105 SDValue CvtSrc = N0.getOperand(0);
3106 if (CvtSrc.getOpcode() == ISD::FNEG) {
3107 // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3108 // (fneg (rcp (fneg x))) -> (rcp x)
3109 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3112 if (!N0.hasOneUse())
3115 // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3116 // (fneg (rcp x)) -> (rcp (fneg x))
3117 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3118 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3120 case ISD::FP_ROUND: {
3121 SDValue CvtSrc = N0.getOperand(0);
3123 if (CvtSrc.getOpcode() == ISD::FNEG) {
3124 // (fneg (fp_round (fneg x))) -> (fp_round x)
3125 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3126 CvtSrc.getOperand(0), N0.getOperand(1));
3129 if (!N0.hasOneUse())
3132 // (fneg (fp_round x)) -> (fp_round (fneg x))
3133 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3134 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3136 case ISD::FP16_TO_FP: {
3137 // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3138 // f16, but legalization of f16 fneg ends up pulling it out of the source.
3139 // Put the fneg back as a legal source operation that can be matched later.
3142 SDValue Src = N0.getOperand(0);
3143 EVT SrcVT = Src.getValueType();
3145 // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3146 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3147 DAG.getConstant(0x8000, SL, SrcVT));
3148 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3155 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3156 DAGCombinerInfo &DCI) const {
3157 SelectionDAG &DAG = DCI.DAG;
3158 SDValue N0 = N->getOperand(0);
3160 if (!N0.hasOneUse())
3163 switch (N0.getOpcode()) {
3164 case ISD::FP16_TO_FP: {
3165 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3167 SDValue Src = N0.getOperand(0);
3168 EVT SrcVT = Src.getValueType();
3170 // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3171 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3172 DAG.getConstant(0x7fff, SL, SrcVT));
3173 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3180 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
3181 DAGCombinerInfo &DCI) const {
3182 SelectionDAG &DAG = DCI.DAG;
3185 switch(N->getOpcode()) {
3188 case ISD::BITCAST: {
3189 EVT DestVT = N->getValueType(0);
3191 // Push casts through vector builds. This helps avoid emitting a large
3192 // number of copies when materializing floating point vector constants.
3194 // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3195 // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3196 if (DestVT.isVector()) {
3197 SDValue Src = N->getOperand(0);
3198 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3199 EVT SrcVT = Src.getValueType();
3200 unsigned NElts = DestVT.getVectorNumElements();
3202 if (SrcVT.getVectorNumElements() == NElts) {
3203 EVT DestEltVT = DestVT.getVectorElementType();
3205 SmallVector<SDValue, 8> CastedElts;
3207 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3208 SDValue Elt = Src.getOperand(I);
3209 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3212 return DAG.getBuildVector(DestVT, SL, CastedElts);
3217 if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
3220 // Fold bitcasts of constants.
3222 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3223 // TODO: Generalize and move to DAGCombiner
3224 SDValue Src = N->getOperand(0);
3225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3226 assert(Src.getValueType() == MVT::i64);
3228 uint64_t CVal = C->getZExtValue();
3229 return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,
3230 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3231 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3234 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3235 const APInt &Val = C->getValueAPF().bitcastToAPInt();
3237 uint64_t CVal = Val.getZExtValue();
3238 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3239 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3240 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3242 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3248 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3251 return performShlCombine(N, DCI);
3254 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3257 return performSrlCombine(N, DCI);
3260 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3263 return performSraCombine(N, DCI);
3266 return performMulCombine(N, DCI);
3268 return performMulhsCombine(N, DCI);
3270 return performMulhuCombine(N, DCI);
3271 case AMDGPUISD::MUL_I24:
3272 case AMDGPUISD::MUL_U24:
3273 case AMDGPUISD::MULHI_I24:
3274 case AMDGPUISD::MULHI_U24: {
3275 // If the first call to simplify is successfull, then N may end up being
3276 // deleted, so we shouldn't call simplifyI24 again.
3277 simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI);
3280 case AMDGPUISD::MUL_LOHI_I24:
3281 case AMDGPUISD::MUL_LOHI_U24:
3282 return performMulLoHi24Combine(N, DCI);
3284 return performSelectCombine(N, DCI);
3286 return performFNegCombine(N, DCI);
3288 return performFAbsCombine(N, DCI);
3289 case AMDGPUISD::BFE_I32:
3290 case AMDGPUISD::BFE_U32: {
3291 assert(!N->getValueType(0).isVector() &&
3292 "Vector handling of BFE not implemented");
3293 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
3297 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
3299 return DAG.getConstant(0, DL, MVT::i32);
3301 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
3305 SDValue BitsFrom = N->getOperand(0);
3306 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
3308 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
3310 if (OffsetVal == 0) {
3311 // This is already sign / zero extended, so try to fold away extra BFEs.
3312 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
3314 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
3315 if (OpSignBits >= SignBits)
3318 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
3320 // This is a sign_extend_inreg. Replace it to take advantage of existing
3321 // DAG Combines. If not eliminated, we will match back to BFE during
3324 // TODO: The sext_inreg of extended types ends, although we can could
3325 // handle them in a single BFE.
3326 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
3327 DAG.getValueType(SmallVT));
3330 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
3333 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
3335 return constantFoldBFE<int32_t>(DAG,
3336 CVal->getSExtValue(),
3342 return constantFoldBFE<uint32_t>(DAG,
3343 CVal->getZExtValue(),
3349 if ((OffsetVal + WidthVal) >= 32) {
3350 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
3351 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
3352 BitsFrom, ShiftVal);
3355 if (BitsFrom.hasOneUse()) {
3356 APInt Demanded = APInt::getBitsSet(32,
3358 OffsetVal + WidthVal);
3360 APInt KnownZero, KnownOne;
3361 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
3362 !DCI.isBeforeLegalizeOps());
3363 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3364 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
3365 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
3366 KnownZero, KnownOne, TLO)) {
3367 DCI.CommitTargetLoweringOpt(TLO);
3374 return performLoadCombine(N, DCI);
3376 return performStoreCombine(N, DCI);
3377 case AMDGPUISD::CLAMP:
3378 return performClampCombine(N, DCI);
3379 case AMDGPUISD::RCP: {
3380 if (const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) {
3381 // XXX - Should this flush denormals?
3382 const APFloat &Val = CFP->getValueAPF();
3383 APFloat One(Val.getSemantics(), "1.0");
3384 return DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3393 //===----------------------------------------------------------------------===//
3395 //===----------------------------------------------------------------------===//
3397 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
3398 const TargetRegisterClass *RC,
3399 unsigned Reg, EVT VT) const {
3400 MachineFunction &MF = DAG.getMachineFunction();
3401 MachineRegisterInfo &MRI = MF.getRegInfo();
3402 unsigned VirtualRegister;
3403 if (!MRI.isLiveIn(Reg)) {
3404 VirtualRegister = MRI.createVirtualRegister(RC);
3405 MRI.addLiveIn(Reg, VirtualRegister);
3407 VirtualRegister = MRI.getLiveInVirtReg(Reg);
3409 return DAG.getRegister(VirtualRegister, VT);
3412 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
3413 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
3414 unsigned Alignment = Subtarget->getAlignmentForImplicitArgPtr();
3415 uint64_t ArgOffset = alignTo(MFI->getABIArgOffset(), Alignment);
3420 return ArgOffset + 4;
3422 llvm_unreachable("unexpected implicit parameter type");
3425 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
3427 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
3428 switch ((AMDGPUISD::NodeType)Opcode) {
3429 case AMDGPUISD::FIRST_NUMBER: break;
3431 NODE_NAME_CASE(UMUL);
3432 NODE_NAME_CASE(BRANCH_COND);
3436 NODE_NAME_CASE(ELSE)
3437 NODE_NAME_CASE(LOOP)
3438 NODE_NAME_CASE(CALL)
3439 NODE_NAME_CASE(RET_FLAG)
3440 NODE_NAME_CASE(RETURN_TO_EPILOG)
3441 NODE_NAME_CASE(ENDPGM)
3442 NODE_NAME_CASE(DWORDADDR)
3443 NODE_NAME_CASE(FRACT)
3444 NODE_NAME_CASE(SETCC)
3445 NODE_NAME_CASE(SETREG)
3446 NODE_NAME_CASE(FMA_W_CHAIN)
3447 NODE_NAME_CASE(FMUL_W_CHAIN)
3448 NODE_NAME_CASE(CLAMP)
3449 NODE_NAME_CASE(COS_HW)
3450 NODE_NAME_CASE(SIN_HW)
3451 NODE_NAME_CASE(FMAX_LEGACY)
3452 NODE_NAME_CASE(FMIN_LEGACY)
3453 NODE_NAME_CASE(FMAX3)
3454 NODE_NAME_CASE(SMAX3)
3455 NODE_NAME_CASE(UMAX3)
3456 NODE_NAME_CASE(FMIN3)
3457 NODE_NAME_CASE(SMIN3)
3458 NODE_NAME_CASE(UMIN3)
3459 NODE_NAME_CASE(FMED3)
3460 NODE_NAME_CASE(SMED3)
3461 NODE_NAME_CASE(UMED3)
3462 NODE_NAME_CASE(URECIP)
3463 NODE_NAME_CASE(DIV_SCALE)
3464 NODE_NAME_CASE(DIV_FMAS)
3465 NODE_NAME_CASE(DIV_FIXUP)
3466 NODE_NAME_CASE(FMAD_FTZ)
3467 NODE_NAME_CASE(TRIG_PREOP)
3470 NODE_NAME_CASE(RCP_LEGACY)
3471 NODE_NAME_CASE(RSQ_LEGACY)
3472 NODE_NAME_CASE(FMUL_LEGACY)
3473 NODE_NAME_CASE(RSQ_CLAMP)
3474 NODE_NAME_CASE(LDEXP)
3475 NODE_NAME_CASE(FP_CLASS)
3476 NODE_NAME_CASE(DOT4)
3477 NODE_NAME_CASE(CARRY)
3478 NODE_NAME_CASE(BORROW)
3479 NODE_NAME_CASE(BFE_U32)
3480 NODE_NAME_CASE(BFE_I32)
3483 NODE_NAME_CASE(FFBH_U32)
3484 NODE_NAME_CASE(FFBH_I32)
3485 NODE_NAME_CASE(MUL_U24)
3486 NODE_NAME_CASE(MUL_I24)
3487 NODE_NAME_CASE(MULHI_U24)
3488 NODE_NAME_CASE(MULHI_I24)
3489 NODE_NAME_CASE(MUL_LOHI_U24)
3490 NODE_NAME_CASE(MUL_LOHI_I24)
3491 NODE_NAME_CASE(MAD_U24)
3492 NODE_NAME_CASE(MAD_I24)
3493 NODE_NAME_CASE(TEXTURE_FETCH)
3494 NODE_NAME_CASE(EXPORT)
3495 NODE_NAME_CASE(EXPORT_DONE)
3496 NODE_NAME_CASE(R600_EXPORT)
3497 NODE_NAME_CASE(CONST_ADDRESS)
3498 NODE_NAME_CASE(REGISTER_LOAD)
3499 NODE_NAME_CASE(REGISTER_STORE)
3500 NODE_NAME_CASE(SAMPLE)
3501 NODE_NAME_CASE(SAMPLEB)
3502 NODE_NAME_CASE(SAMPLED)
3503 NODE_NAME_CASE(SAMPLEL)
3504 NODE_NAME_CASE(CVT_F32_UBYTE0)
3505 NODE_NAME_CASE(CVT_F32_UBYTE1)
3506 NODE_NAME_CASE(CVT_F32_UBYTE2)
3507 NODE_NAME_CASE(CVT_F32_UBYTE3)
3508 NODE_NAME_CASE(CVT_PKRTZ_F16_F32)
3509 NODE_NAME_CASE(FP_TO_FP16)
3510 NODE_NAME_CASE(FP16_ZEXT)
3511 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
3512 NODE_NAME_CASE(CONST_DATA_PTR)
3513 NODE_NAME_CASE(PC_ADD_REL_OFFSET)
3514 NODE_NAME_CASE(KILL)
3515 NODE_NAME_CASE(DUMMY_CHAIN)
3516 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
3517 NODE_NAME_CASE(SENDMSG)
3518 NODE_NAME_CASE(SENDMSGHALT)
3519 NODE_NAME_CASE(INTERP_MOV)
3520 NODE_NAME_CASE(INTERP_P1)
3521 NODE_NAME_CASE(INTERP_P2)
3522 NODE_NAME_CASE(STORE_MSKOR)
3523 NODE_NAME_CASE(LOAD_CONSTANT)
3524 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
3525 NODE_NAME_CASE(ATOMIC_CMP_SWAP)
3526 NODE_NAME_CASE(ATOMIC_INC)
3527 NODE_NAME_CASE(ATOMIC_DEC)
3528 NODE_NAME_CASE(BUFFER_LOAD)
3529 NODE_NAME_CASE(BUFFER_LOAD_FORMAT)
3530 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
3535 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
3536 SelectionDAG &DAG, int Enabled,
3537 int &RefinementSteps,
3538 bool &UseOneConstNR,
3539 bool Reciprocal) const {
3540 EVT VT = Operand.getValueType();
3542 if (VT == MVT::f32) {
3543 RefinementSteps = 0;
3544 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
3547 // TODO: There is also f64 rsq instruction, but the documentation is less
3548 // clear on its precision.
3553 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
3554 SelectionDAG &DAG, int Enabled,
3555 int &RefinementSteps) const {
3556 EVT VT = Operand.getValueType();
3558 if (VT == MVT::f32) {
3559 // Reciprocal, < 1 ulp error.
3561 // This reciprocal approximation converges to < 0.5 ulp error with one
3562 // newton rhapson performed with two fused multiple adds (FMAs).
3564 RefinementSteps = 0;
3565 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
3568 // TODO: There is also f64 rcp instruction, but the documentation is less
3569 // clear on its precision.
3574 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
3575 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
3576 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
3578 unsigned BitWidth = KnownZero.getBitWidth();
3579 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
3583 unsigned Opc = Op.getOpcode();
3588 case AMDGPUISD::CARRY:
3589 case AMDGPUISD::BORROW: {
3590 KnownZero = APInt::getHighBitsSet(32, 31);
3594 case AMDGPUISD::BFE_I32:
3595 case AMDGPUISD::BFE_U32: {
3596 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3600 uint32_t Width = CWidth->getZExtValue() & 0x1f;
3602 if (Opc == AMDGPUISD::BFE_U32)
3603 KnownZero = APInt::getHighBitsSet(32, 32 - Width);
3607 case AMDGPUISD::FP_TO_FP16:
3608 case AMDGPUISD::FP16_ZEXT: {
3609 unsigned BitWidth = KnownZero.getBitWidth();
3611 // High bits are zero.
3612 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
3618 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
3619 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
3620 unsigned Depth) const {
3621 switch (Op.getOpcode()) {
3622 case AMDGPUISD::BFE_I32: {
3623 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3627 unsigned SignBits = 32 - Width->getZExtValue() + 1;
3628 if (!isNullConstant(Op.getOperand(1)))
3631 // TODO: Could probably figure something out with non-0 offsets.
3632 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
3633 return std::max(SignBits, Op0SignBits);
3636 case AMDGPUISD::BFE_U32: {
3637 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3638 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
3641 case AMDGPUISD::CARRY:
3642 case AMDGPUISD::BORROW:
3644 case AMDGPUISD::FP_TO_FP16:
3645 case AMDGPUISD::FP16_ZEXT: