1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "SIInstrInfo.h"
34 static bool allocateKernArg(unsigned ValNo, MVT ValVT, MVT LocVT,
35 CCValAssign::LocInfo LocInfo,
36 ISD::ArgFlagsTy ArgFlags, CCState &State) {
37 MachineFunction &MF = State.getMachineFunction();
38 AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
40 uint64_t Offset = MFI->allocateKernArg(ValVT.getStoreSize(),
41 ArgFlags.getOrigAlign());
42 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
46 #include "AMDGPUGenCallingConv.inc"
48 // Find a larger type to do a load / store of a vector with.
49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
50 unsigned StoreSize = VT.getStoreSizeInBits();
52 return EVT::getIntegerVT(Ctx, StoreSize);
54 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
55 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) {
59 unsigned StoreSize = VT.getStoreSizeInBits();
61 return EVT::getIntegerVT(Ctx, StoreSize);
63 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
66 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
67 const AMDGPUSubtarget &STI)
68 : TargetLowering(TM), Subtarget(&STI) {
69 // Lower floating point store/load to integer store/load to reduce the number
70 // of patterns in tablegen.
71 setOperationAction(ISD::LOAD, MVT::f32, Promote);
72 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
74 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
75 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
77 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
78 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
80 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
81 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
83 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
84 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
86 setOperationAction(ISD::LOAD, MVT::i64, Promote);
87 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
89 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
90 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
92 setOperationAction(ISD::LOAD, MVT::f64, Promote);
93 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
95 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
96 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
98 // There are no 64-bit extloads. These should be done as a 32-bit extload and
99 // an extension to 64-bit.
100 for (MVT VT : MVT::integer_valuetypes()) {
101 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
102 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
103 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
106 for (MVT VT : MVT::integer_valuetypes()) {
110 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
111 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
112 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
113 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
116 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
117 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
118 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
120 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
121 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
122 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
126 for (MVT VT : MVT::integer_vector_valuetypes()) {
127 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
130 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
131 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
133 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
135 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
141 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
142 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
143 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
144 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
146 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
147 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
148 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
149 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
151 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
152 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
154 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
156 setOperationAction(ISD::STORE, MVT::f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
159 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
162 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
163 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
165 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
166 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
168 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
169 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
171 setOperationAction(ISD::STORE, MVT::i64, Promote);
172 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
174 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
175 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
177 setOperationAction(ISD::STORE, MVT::f64, Promote);
178 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
180 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
181 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
183 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
184 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
186 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
187 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
189 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
190 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
191 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
193 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
194 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
195 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
196 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
198 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
199 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
200 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
201 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
203 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
204 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
205 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
206 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
208 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
209 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
211 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
212 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
214 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
215 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
217 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
218 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
221 setOperationAction(ISD::Constant, MVT::i32, Legal);
222 setOperationAction(ISD::Constant, MVT::i64, Legal);
223 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
224 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
226 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
227 setOperationAction(ISD::BRIND, MVT::Other, Expand);
229 // This is totally unsupported, just custom lower to produce an error.
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
232 // We need to custom lower some of the intrinsics
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
234 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
236 // Library functions. These default to Expand, but we have instructions
238 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
239 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
240 setOperationAction(ISD::FPOW, MVT::f32, Legal);
241 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
242 setOperationAction(ISD::FABS, MVT::f32, Legal);
243 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
244 setOperationAction(ISD::FRINT, MVT::f32, Legal);
245 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
246 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
247 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
249 setOperationAction(ISD::FROUND, MVT::f32, Custom);
250 setOperationAction(ISD::FROUND, MVT::f64, Custom);
252 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
253 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
255 setOperationAction(ISD::FREM, MVT::f32, Custom);
256 setOperationAction(ISD::FREM, MVT::f64, Custom);
258 // v_mad_f32 does not support denormals according to some sources.
259 if (!Subtarget->hasFP32Denormals())
260 setOperationAction(ISD::FMAD, MVT::f32, Legal);
262 // Expand to fneg + fadd.
263 setOperationAction(ISD::FSUB, MVT::f64, Expand);
265 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
266 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
267 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
268 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
269 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
270 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
271 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
272 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
273 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
274 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
276 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
277 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
278 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
279 setOperationAction(ISD::FRINT, MVT::f64, Custom);
280 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
283 if (!Subtarget->hasBFI()) {
284 // fcopysign can be done in a single instruction with BFI.
285 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
286 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
289 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
291 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
292 for (MVT VT : ScalarIntVTs) {
293 // These should use [SU]DIVREM, so set them to expand
294 setOperationAction(ISD::SDIV, VT, Expand);
295 setOperationAction(ISD::UDIV, VT, Expand);
296 setOperationAction(ISD::SREM, VT, Expand);
297 setOperationAction(ISD::UREM, VT, Expand);
299 // GPU does not have divrem function for signed or unsigned.
300 setOperationAction(ISD::SDIVREM, VT, Custom);
301 setOperationAction(ISD::UDIVREM, VT, Custom);
303 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
304 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
305 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
307 setOperationAction(ISD::BSWAP, VT, Expand);
308 setOperationAction(ISD::CTTZ, VT, Expand);
309 setOperationAction(ISD::CTLZ, VT, Expand);
312 if (!Subtarget->hasBCNT(32))
313 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
315 if (!Subtarget->hasBCNT(64))
316 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
318 // The hardware supports 32-bit ROTR, but not ROTL.
319 setOperationAction(ISD::ROTL, MVT::i32, Expand);
320 setOperationAction(ISD::ROTL, MVT::i64, Expand);
321 setOperationAction(ISD::ROTR, MVT::i64, Expand);
323 setOperationAction(ISD::MUL, MVT::i64, Expand);
324 setOperationAction(ISD::MULHU, MVT::i64, Expand);
325 setOperationAction(ISD::MULHS, MVT::i64, Expand);
326 setOperationAction(ISD::UDIV, MVT::i32, Expand);
327 setOperationAction(ISD::UREM, MVT::i32, Expand);
328 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
329 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
331 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
332 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
334 setOperationAction(ISD::SMIN, MVT::i32, Legal);
335 setOperationAction(ISD::UMIN, MVT::i32, Legal);
336 setOperationAction(ISD::SMAX, MVT::i32, Legal);
337 setOperationAction(ISD::UMAX, MVT::i32, Legal);
339 if (Subtarget->hasFFBH())
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
342 if (Subtarget->hasFFBL())
343 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Legal);
345 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
348 // We only really have 32-bit BFE instructions (and 16-bit on VI).
350 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
351 // effort to match them now. We want this to be false for i64 cases when the
352 // extraction isn't restricted to the upper or lower half. Ideally we would
353 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
354 // span the midpoint are probably relatively rare, so don't worry about them
356 if (Subtarget->hasBFE())
357 setHasExtractBitsInsn(true);
359 static const MVT::SimpleValueType VectorIntTypes[] = {
360 MVT::v2i32, MVT::v4i32
363 for (MVT VT : VectorIntTypes) {
364 // Expand the following operations for the current type by default.
365 setOperationAction(ISD::ADD, VT, Expand);
366 setOperationAction(ISD::AND, VT, Expand);
367 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
368 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
369 setOperationAction(ISD::MUL, VT, Expand);
370 setOperationAction(ISD::OR, VT, Expand);
371 setOperationAction(ISD::SHL, VT, Expand);
372 setOperationAction(ISD::SRA, VT, Expand);
373 setOperationAction(ISD::SRL, VT, Expand);
374 setOperationAction(ISD::ROTL, VT, Expand);
375 setOperationAction(ISD::ROTR, VT, Expand);
376 setOperationAction(ISD::SUB, VT, Expand);
377 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
378 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
379 setOperationAction(ISD::SDIV, VT, Expand);
380 setOperationAction(ISD::UDIV, VT, Expand);
381 setOperationAction(ISD::SREM, VT, Expand);
382 setOperationAction(ISD::UREM, VT, Expand);
383 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
384 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
385 setOperationAction(ISD::SDIVREM, VT, Custom);
386 setOperationAction(ISD::UDIVREM, VT, Expand);
387 setOperationAction(ISD::ADDC, VT, Expand);
388 setOperationAction(ISD::SUBC, VT, Expand);
389 setOperationAction(ISD::ADDE, VT, Expand);
390 setOperationAction(ISD::SUBE, VT, Expand);
391 setOperationAction(ISD::SELECT, VT, Expand);
392 setOperationAction(ISD::VSELECT, VT, Expand);
393 setOperationAction(ISD::SELECT_CC, VT, Expand);
394 setOperationAction(ISD::XOR, VT, Expand);
395 setOperationAction(ISD::BSWAP, VT, Expand);
396 setOperationAction(ISD::CTPOP, VT, Expand);
397 setOperationAction(ISD::CTTZ, VT, Expand);
398 setOperationAction(ISD::CTLZ, VT, Expand);
399 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
402 static const MVT::SimpleValueType FloatVectorTypes[] = {
403 MVT::v2f32, MVT::v4f32
406 for (MVT VT : FloatVectorTypes) {
407 setOperationAction(ISD::FABS, VT, Expand);
408 setOperationAction(ISD::FMINNUM, VT, Expand);
409 setOperationAction(ISD::FMAXNUM, VT, Expand);
410 setOperationAction(ISD::FADD, VT, Expand);
411 setOperationAction(ISD::FCEIL, VT, Expand);
412 setOperationAction(ISD::FCOS, VT, Expand);
413 setOperationAction(ISD::FDIV, VT, Expand);
414 setOperationAction(ISD::FEXP2, VT, Expand);
415 setOperationAction(ISD::FLOG2, VT, Expand);
416 setOperationAction(ISD::FREM, VT, Expand);
417 setOperationAction(ISD::FPOW, VT, Expand);
418 setOperationAction(ISD::FFLOOR, VT, Expand);
419 setOperationAction(ISD::FTRUNC, VT, Expand);
420 setOperationAction(ISD::FMUL, VT, Expand);
421 setOperationAction(ISD::FMA, VT, Expand);
422 setOperationAction(ISD::FRINT, VT, Expand);
423 setOperationAction(ISD::FNEARBYINT, VT, Expand);
424 setOperationAction(ISD::FSQRT, VT, Expand);
425 setOperationAction(ISD::FSIN, VT, Expand);
426 setOperationAction(ISD::FSUB, VT, Expand);
427 setOperationAction(ISD::FNEG, VT, Expand);
428 setOperationAction(ISD::VSELECT, VT, Expand);
429 setOperationAction(ISD::SELECT_CC, VT, Expand);
430 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
431 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
434 // This causes using an unrolled select operation rather than expansion with
435 // bit operations. This is in general better, but the alternative using BFI
436 // instructions may be better if the select sources are SGPRs.
437 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
438 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
440 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
441 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
443 setBooleanContents(ZeroOrNegativeOneBooleanContent);
444 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
446 setSchedulingPreference(Sched::RegPressure);
447 setJumpIsExpensive(true);
449 // SI at least has hardware support for floating point exceptions, but no way
450 // of using or handling them is implemented. They are also optional in OpenCL
452 setHasFloatingPointExceptions(Subtarget->hasFPExceptions());
454 setSelectIsExpensive(false);
455 PredictableSelectIsExpensive = false;
457 setFsqrtIsCheap(true);
459 // We want to find all load dependencies for long chains of stores to enable
460 // merging into very wide vectors. The problem is with vectors with > 4
461 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
462 // vectors are a legal type, even though we have to split the loads
463 // usually. When we can more precisely specify load legality per address
464 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
465 // smarter so that they can figure out what to do in 2 iterations without all
466 // N > 4 stores on the same chain.
467 GatherAllAliasesMaxDepth = 16;
469 // FIXME: Need to really handle these.
470 MaxStoresPerMemcpy = 4096;
471 MaxStoresPerMemmove = 4096;
472 MaxStoresPerMemset = 4096;
474 setTargetDAGCombine(ISD::BITCAST);
475 setTargetDAGCombine(ISD::AND);
476 setTargetDAGCombine(ISD::SHL);
477 setTargetDAGCombine(ISD::SRA);
478 setTargetDAGCombine(ISD::SRL);
479 setTargetDAGCombine(ISD::MUL);
480 setTargetDAGCombine(ISD::SELECT);
481 setTargetDAGCombine(ISD::SELECT_CC);
482 setTargetDAGCombine(ISD::STORE);
483 setTargetDAGCombine(ISD::FADD);
484 setTargetDAGCombine(ISD::FSUB);
487 //===----------------------------------------------------------------------===//
488 // Target Information
489 //===----------------------------------------------------------------------===//
491 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
495 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
499 // The backend supports 32 and 64 bit floating point immediates.
500 // FIXME: Why are we reporting vectors of FP immediates as legal?
501 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
502 EVT ScalarVT = VT.getScalarType();
503 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
506 // We don't want to shrink f64 / f32 constants.
507 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
508 EVT ScalarVT = VT.getScalarType();
509 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
512 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
516 unsigned NewSize = NewVT.getStoreSizeInBits();
518 // If we are reducing to a 32-bit load, this is always better.
522 EVT OldVT = N->getValueType(0);
523 unsigned OldSize = OldVT.getStoreSizeInBits();
525 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
526 // extloads, so doing one requires using a buffer_load. In cases where we
527 // still couldn't use a scalar load, using the wider load shouldn't really
530 // If the old size already had to be an extload, there's no harm in continuing
531 // to reduce the width.
532 return (OldSize < 32);
535 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
538 assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
540 if (LoadTy.getScalarType() == MVT::i32)
543 unsigned LScalarSize = LoadTy.getScalarSizeInBits();
544 unsigned CastScalarSize = CastTy.getScalarSizeInBits();
546 return (LScalarSize < CastScalarSize) ||
547 (CastScalarSize >= 32);
550 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
551 // profitable with the expansion for 64-bit since it's generally good to
553 // FIXME: These should really have the size as a parameter.
554 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
558 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
562 //===---------------------------------------------------------------------===//
564 //===---------------------------------------------------------------------===//
566 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
567 assert(VT.isFloatingPoint());
568 return VT == MVT::f32 || VT == MVT::f64;
571 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
572 assert(VT.isFloatingPoint());
573 return VT == MVT::f32 || VT == MVT::f64;
576 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
582 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
583 // There are few operations which truly have vector input operands. Any vector
584 // operation is going to involve operations on each component, and a
585 // build_vector will be a copy per element, so it always makes sense to use a
586 // build_vector input in place of the extracted element to avoid a copy into a
589 // We should probably only do this if all users are extracts only, but this
590 // should be the common case.
594 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
595 // Truncate is just accessing a subregister.
596 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
599 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
600 // Truncate is just accessing a subregister.
601 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
602 (Dest->getPrimitiveSizeInBits() % 32 == 0);
605 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
606 unsigned SrcSize = Src->getScalarSizeInBits();
607 unsigned DestSize = Dest->getScalarSizeInBits();
609 return SrcSize == 32 && DestSize == 64;
612 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
613 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
614 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
615 // this will enable reducing 64-bit operations the 32-bit, which is always
617 return Src == MVT::i32 && Dest == MVT::i64;
620 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
621 return isZExtFree(Val.getValueType(), VT2);
624 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
625 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
626 // limited number of native 64-bit operations. Shrinking an operation to fit
627 // in a single 32-bit register should always be helpful. As currently used,
628 // this is much less general than the name suggests, and is only used in
629 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
630 // not profitable, and may actually be harmful.
631 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
634 //===---------------------------------------------------------------------===//
635 // TargetLowering Callbacks
636 //===---------------------------------------------------------------------===//
638 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
639 const SmallVectorImpl<ISD::InputArg> &Ins) const {
641 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
644 void AMDGPUTargetLowering::AnalyzeReturn(CCState &State,
645 const SmallVectorImpl<ISD::OutputArg> &Outs) const {
647 State.AnalyzeReturn(Outs, RetCC_SI);
651 AMDGPUTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
653 const SmallVectorImpl<ISD::OutputArg> &Outs,
654 const SmallVectorImpl<SDValue> &OutVals,
655 const SDLoc &DL, SelectionDAG &DAG) const {
656 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
659 //===---------------------------------------------------------------------===//
660 // Target specific lowering
661 //===---------------------------------------------------------------------===//
663 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
664 SmallVectorImpl<SDValue> &InVals) const {
665 SDValue Callee = CLI.Callee;
666 SelectionDAG &DAG = CLI.DAG;
668 const Function &Fn = *DAG.getMachineFunction().getFunction();
670 StringRef FuncName("<unknown>");
672 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
673 FuncName = G->getSymbol();
674 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
675 FuncName = G->getGlobal()->getName();
677 DiagnosticInfoUnsupported NoCalls(
678 Fn, "unsupported call to function " + FuncName, CLI.DL.getDebugLoc());
679 DAG.getContext()->diagnose(NoCalls);
681 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
682 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
684 return DAG.getEntryNode();
687 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
688 SelectionDAG &DAG) const {
689 const Function &Fn = *DAG.getMachineFunction().getFunction();
691 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
692 SDLoc(Op).getDebugLoc());
693 DAG.getContext()->diagnose(NoDynamicAlloca);
694 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
695 return DAG.getMergeValues(Ops, SDLoc());
698 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
699 SelectionDAG &DAG) const {
700 switch (Op.getOpcode()) {
703 llvm_unreachable("Custom lowering code for this"
704 "instruction is not implemented yet!");
706 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
707 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
708 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
709 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
710 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
711 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
712 case ISD::FREM: return LowerFREM(Op, DAG);
713 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
714 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
715 case ISD::FRINT: return LowerFRINT(Op, DAG);
716 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
717 case ISD::FROUND: return LowerFROUND(Op, DAG);
718 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
719 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
720 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
721 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
722 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
724 case ISD::CTLZ_ZERO_UNDEF:
725 return LowerCTLZ(Op, DAG);
726 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
731 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
732 SmallVectorImpl<SDValue> &Results,
733 SelectionDAG &DAG) const {
734 switch (N->getOpcode()) {
735 case ISD::SIGN_EXTEND_INREG:
736 // Different parts of legalization seem to interpret which type of
737 // sign_extend_inreg is the one to check for custom lowering. The extended
738 // from type is what really matters, but some places check for custom
739 // lowering of the result type. This results in trying to use
740 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
741 // nothing here and let the illegal result integer be handled normally.
748 // FIXME: This implements accesses to initialized globals in the constant
749 // address space by copying them to private and accessing that. It does not
750 // properly handle illegal types or vectors. The private vector loads are not
751 // scalarized, and the illegal scalars hit an assertion. This technique will not
752 // work well with large initializers, and this should eventually be
753 // removed. Initialized globals should be placed into a data section that the
754 // runtime will load into a buffer before the kernel is executed. Uses of the
755 // global need to be replaced with a pointer loaded from an implicit kernel
756 // argument into this buffer holding the copy of the data, which will remove the
757 // need for any of this.
758 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
759 const GlobalValue *GV,
760 const SDValue &InitPtr,
762 SelectionDAG &DAG) const {
763 const DataLayout &TD = DAG.getDataLayout();
765 Type *InitTy = Init->getType();
767 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
768 EVT VT = EVT::getEVT(InitTy);
769 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
770 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
771 MachinePointerInfo(UndefValue::get(PtrTy)),
772 TD.getPrefTypeAlignment(InitTy));
775 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
776 EVT VT = EVT::getEVT(CFP->getType());
777 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
778 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
779 MachinePointerInfo(UndefValue::get(PtrTy)),
780 TD.getPrefTypeAlignment(CFP->getType()));
783 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
784 const StructLayout *SL = TD.getStructLayout(ST);
786 EVT PtrVT = InitPtr.getValueType();
787 SmallVector<SDValue, 8> Chains;
789 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
790 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
791 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
793 Constant *Elt = Init->getAggregateElement(I);
794 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
797 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
800 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
801 EVT PtrVT = InitPtr.getValueType();
803 unsigned NumElements;
804 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
805 NumElements = AT->getNumElements();
806 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
807 NumElements = VT->getNumElements();
809 llvm_unreachable("Unexpected type");
811 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
812 SmallVector<SDValue, 8> Chains;
813 for (unsigned i = 0; i < NumElements; ++i) {
814 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
815 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
817 Constant *Elt = Init->getAggregateElement(i);
818 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
821 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
824 if (isa<UndefValue>(Init)) {
825 EVT VT = EVT::getEVT(InitTy);
826 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
827 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
828 MachinePointerInfo(UndefValue::get(PtrTy)),
829 TD.getPrefTypeAlignment(InitTy));
833 llvm_unreachable("Unhandled constant initializer");
836 static bool hasDefinedInitializer(const GlobalValue *GV) {
837 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
838 if (!GVar || !GVar->hasInitializer())
841 return !isa<UndefValue>(GVar->getInitializer());
844 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
846 SelectionDAG &DAG) const {
848 const DataLayout &DL = DAG.getDataLayout();
849 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
850 const GlobalValue *GV = G->getGlobal();
852 switch (G->getAddressSpace()) {
853 case AMDGPUAS::CONSTANT_ADDRESS: {
854 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
855 SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(G), ConstPtrVT);
856 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(G), ConstPtrVT, GA);
858 case AMDGPUAS::LOCAL_ADDRESS: {
859 // XXX: What does the value of G->getOffset() mean?
860 assert(G->getOffset() == 0 &&
861 "Do not know what to do with an non-zero offset");
863 // TODO: We could emit code to handle the initialization somewhere.
864 if (hasDefinedInitializer(GV))
868 if (MFI->LocalMemoryObjects.count(GV) == 0) {
869 unsigned Align = GV->getAlignment();
871 Align = DL.getABITypeAlignment(GV->getValueType());
873 /// TODO: We should sort these to minimize wasted space due to alignment
874 /// padding. Currently the padding is decided by the first encountered use
876 Offset = MFI->LDSSize = alignTo(MFI->LDSSize, Align);
877 MFI->LocalMemoryObjects[GV] = Offset;
878 MFI->LDSSize += DL.getTypeAllocSize(GV->getValueType());
880 Offset = MFI->LocalMemoryObjects[GV];
883 return DAG.getConstant(Offset, SDLoc(Op),
884 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
888 const Function &Fn = *DAG.getMachineFunction().getFunction();
889 DiagnosticInfoUnsupported BadInit(
890 Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
891 DAG.getContext()->diagnose(BadInit);
895 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
896 SelectionDAG &DAG) const {
897 SmallVector<SDValue, 8> Args;
899 for (const SDUse &U : Op->ops())
900 DAG.ExtractVectorElements(U.get(), Args);
902 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
905 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
906 SelectionDAG &DAG) const {
908 SmallVector<SDValue, 8> Args;
909 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
910 EVT VT = Op.getValueType();
911 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
912 VT.getVectorNumElements());
914 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
917 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
918 SelectionDAG &DAG) const {
919 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
921 EVT VT = Op.getValueType();
923 switch (IntrinsicID) {
925 case AMDGPUIntrinsic::AMDGPU_clamp: // Legacy name.
926 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
927 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
929 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
930 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
935 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
936 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
943 /// \brief Generate Min/Max node
944 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(const SDLoc &DL, EVT VT,
945 SDValue LHS, SDValue RHS,
946 SDValue True, SDValue False,
948 DAGCombinerInfo &DCI) const {
949 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
952 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
955 SelectionDAG &DAG = DCI.DAG;
956 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
974 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
975 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
981 // Ordered. Assume ordered for undefined.
983 // Only do this after legalization to avoid interfering with other combines
984 // which might occur.
985 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
986 !DCI.isCalledByLegalizer())
989 // We need to permute the operands to get the correct NaN behavior. The
990 // selected operand is the second one based on the failing compare with NaN,
991 // so permute it based on the compare type the hardware uses.
993 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
994 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
999 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1000 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1006 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1007 !DCI.isCalledByLegalizer())
1011 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1012 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1014 case ISD::SETCC_INVALID:
1015 llvm_unreachable("Invalid setcc condcode!");
1020 std::pair<SDValue, SDValue>
1021 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1024 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1026 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1027 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1029 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1030 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1032 return std::make_pair(Lo, Hi);
1035 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1038 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1039 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1040 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1043 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1046 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1047 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1048 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1051 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1052 SelectionDAG &DAG) const {
1053 LoadSDNode *Load = cast<LoadSDNode>(Op);
1054 EVT VT = Op.getValueType();
1057 // If this is a 2 element vector, we really want to scalarize and not create
1058 // weird 1 element vectors.
1059 if (VT.getVectorNumElements() == 2)
1060 return scalarizeVectorLoad(Load, DAG);
1062 SDValue BasePtr = Load->getBasePtr();
1063 EVT PtrVT = BasePtr.getValueType();
1064 EVT MemVT = Load->getMemoryVT();
1067 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1070 EVT LoMemVT, HiMemVT;
1073 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1074 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1075 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1077 unsigned Size = LoMemVT.getStoreSize();
1078 unsigned BaseAlign = Load->getAlignment();
1079 unsigned HiAlign = MinAlign(BaseAlign, Size);
1081 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1082 Load->getChain(), BasePtr, SrcValue, LoMemVT,
1083 BaseAlign, Load->getMemOperand()->getFlags());
1084 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1085 DAG.getConstant(Size, SL, PtrVT));
1087 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1088 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1089 HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1092 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1093 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1094 LoLoad.getValue(1), HiLoad.getValue(1))
1097 return DAG.getMergeValues(Ops, SL);
1100 // FIXME: This isn't doing anything for SI. This should be used in a target
1101 // combine during type legalization.
1102 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1103 SelectionDAG &DAG) const {
1104 StoreSDNode *Store = cast<StoreSDNode>(Op);
1105 EVT MemVT = Store->getMemoryVT();
1106 unsigned MemBits = MemVT.getSizeInBits();
1108 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1109 // truncating store into an i32 store.
1110 // XXX: We could also handle optimize other vector bitwidths.
1111 if (!MemVT.isVector() || MemBits > 32) {
1116 SDValue Value = Store->getValue();
1117 EVT VT = Value.getValueType();
1118 EVT ElemVT = VT.getVectorElementType();
1119 SDValue Ptr = Store->getBasePtr();
1120 EVT MemEltVT = MemVT.getVectorElementType();
1121 unsigned MemEltBits = MemEltVT.getSizeInBits();
1122 unsigned MemNumElements = MemVT.getVectorNumElements();
1123 unsigned PackedSize = MemVT.getStoreSizeInBits();
1124 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1126 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1128 SDValue PackedValue;
1129 for (unsigned i = 0; i < MemNumElements; ++i) {
1130 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1131 DAG.getConstant(i, DL, MVT::i32));
1132 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1133 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1135 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1136 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1141 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1145 if (PackedSize < 32) {
1146 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1147 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1148 Store->getMemOperand()->getPointerInfo(), PackedVT,
1149 Store->getAlignment(),
1150 Store->getMemOperand()->getFlags());
1153 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1154 Store->getMemOperand()->getPointerInfo(),
1155 Store->getAlignment(),
1156 Store->getMemOperand()->getFlags());
1159 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1160 SelectionDAG &DAG) const {
1161 StoreSDNode *Store = cast<StoreSDNode>(Op);
1162 SDValue Val = Store->getValue();
1163 EVT VT = Val.getValueType();
1165 // If this is a 2 element vector, we really want to scalarize and not create
1166 // weird 1 element vectors.
1167 if (VT.getVectorNumElements() == 2)
1168 return scalarizeVectorStore(Store, DAG);
1170 EVT MemVT = Store->getMemoryVT();
1171 SDValue Chain = Store->getChain();
1172 SDValue BasePtr = Store->getBasePtr();
1176 EVT LoMemVT, HiMemVT;
1179 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1180 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1181 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1183 EVT PtrVT = BasePtr.getValueType();
1184 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1185 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1188 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1189 unsigned BaseAlign = Store->getAlignment();
1190 unsigned Size = LoMemVT.getStoreSize();
1191 unsigned HiAlign = MinAlign(BaseAlign, Size);
1194 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1195 Store->getMemOperand()->getFlags());
1197 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1198 HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1200 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1203 // This is a shortcut for integer division because we have fast i32<->f32
1204 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1205 // float is enough to accurately represent up to a 24-bit signed integer.
1206 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1209 EVT VT = Op.getValueType();
1210 SDValue LHS = Op.getOperand(0);
1211 SDValue RHS = Op.getOperand(1);
1212 MVT IntVT = MVT::i32;
1213 MVT FltVT = MVT::f32;
1215 unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1216 if (LHSSignBits < 9)
1219 unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1220 if (RHSSignBits < 9)
1223 unsigned BitSize = VT.getSizeInBits();
1224 unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1225 unsigned DivBits = BitSize - SignBits;
1229 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1230 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1232 SDValue jq = DAG.getConstant(1, DL, IntVT);
1235 // char|short jq = ia ^ ib;
1236 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1238 // jq = jq >> (bitsize - 2)
1239 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1240 DAG.getConstant(BitSize - 2, DL, VT));
1243 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1246 // int ia = (int)LHS;
1249 // int ib, (int)RHS;
1252 // float fa = (float)ia;
1253 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1255 // float fb = (float)ib;
1256 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1258 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1259 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1262 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1264 // float fqneg = -fq;
1265 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1267 // float fr = mad(fqneg, fb, fa);
1268 SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa);
1270 // int iq = (int)fq;
1271 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1274 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1277 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1279 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1281 // int cv = fr >= fb;
1282 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1284 // jq = (cv ? jq : 0);
1285 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1288 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1290 // Rem needs compensation, it's easier to recompute it
1291 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1292 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1294 // Truncate to number of bits this divide really is.
1297 = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1298 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1299 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1301 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1302 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1303 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1306 return DAG.getMergeValues({ Div, Rem }, DL);
1309 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1311 SmallVectorImpl<SDValue> &Results) const {
1312 assert(Op.getValueType() == MVT::i64);
1315 EVT VT = Op.getValueType();
1316 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1318 SDValue one = DAG.getConstant(1, DL, HalfVT);
1319 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1322 SDValue LHS = Op.getOperand(0);
1323 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1324 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1326 SDValue RHS = Op.getOperand(1);
1327 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1328 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1330 if (VT == MVT::i64 &&
1331 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1332 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1334 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1337 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), zero});
1338 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), zero});
1340 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1341 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1345 // Get Speculative values
1346 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1347 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1349 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1350 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, zero});
1351 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1353 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1354 SDValue DIV_Lo = zero;
1356 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1358 for (unsigned i = 0; i < halfBitWidth; ++i) {
1359 const unsigned bitPos = halfBitWidth - i - 1;
1360 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1361 // Get value of high bit
1362 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1363 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1364 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1367 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1369 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1371 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1372 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1374 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1377 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1378 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1381 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1382 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1383 Results.push_back(DIV);
1384 Results.push_back(REM);
1387 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1388 SelectionDAG &DAG) const {
1390 EVT VT = Op.getValueType();
1392 if (VT == MVT::i64) {
1393 SmallVector<SDValue, 2> Results;
1394 LowerUDIVREM64(Op, DAG, Results);
1395 return DAG.getMergeValues(Results, DL);
1398 if (VT == MVT::i32) {
1399 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1403 SDValue Num = Op.getOperand(0);
1404 SDValue Den = Op.getOperand(1);
1406 // RCP = URECIP(Den) = 2^32 / Den + e
1407 // e is rounding error.
1408 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1410 // RCP_LO = mul(RCP, Den) */
1411 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1413 // RCP_HI = mulhu (RCP, Den) */
1414 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1416 // NEG_RCP_LO = -RCP_LO
1417 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1420 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1421 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1424 // Calculate the rounding error from the URECIP instruction
1425 // E = mulhu(ABS_RCP_LO, RCP)
1426 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1428 // RCP_A_E = RCP + E
1429 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1431 // RCP_S_E = RCP - E
1432 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1434 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1435 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1438 // Quotient = mulhu(Tmp0, Num)
1439 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1441 // Num_S_Remainder = Quotient * Den
1442 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1444 // Remainder = Num - Num_S_Remainder
1445 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1447 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1448 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1449 DAG.getConstant(-1, DL, VT),
1450 DAG.getConstant(0, DL, VT),
1452 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1453 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1455 DAG.getConstant(-1, DL, VT),
1456 DAG.getConstant(0, DL, VT),
1458 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1459 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1462 // Calculate Division result:
1464 // Quotient_A_One = Quotient + 1
1465 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1466 DAG.getConstant(1, DL, VT));
1468 // Quotient_S_One = Quotient - 1
1469 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1470 DAG.getConstant(1, DL, VT));
1472 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1473 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1474 Quotient, Quotient_A_One, ISD::SETEQ);
1476 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1477 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1478 Quotient_S_One, Div, ISD::SETEQ);
1480 // Calculate Rem result:
1482 // Remainder_S_Den = Remainder - Den
1483 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1485 // Remainder_A_Den = Remainder + Den
1486 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1488 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1489 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1490 Remainder, Remainder_S_Den, ISD::SETEQ);
1492 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1493 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1494 Remainder_A_Den, Rem, ISD::SETEQ);
1499 return DAG.getMergeValues(Ops, DL);
1502 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1503 SelectionDAG &DAG) const {
1505 EVT VT = Op.getValueType();
1507 SDValue LHS = Op.getOperand(0);
1508 SDValue RHS = Op.getOperand(1);
1510 SDValue Zero = DAG.getConstant(0, DL, VT);
1511 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1513 if (VT == MVT::i32) {
1514 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1518 if (VT == MVT::i64 &&
1519 DAG.ComputeNumSignBits(LHS) > 32 &&
1520 DAG.ComputeNumSignBits(RHS) > 32) {
1521 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1524 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1525 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1526 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1529 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1530 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1532 return DAG.getMergeValues(Res, DL);
1535 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1536 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1537 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1538 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1540 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1541 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1543 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1544 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1546 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1547 SDValue Rem = Div.getValue(1);
1549 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1550 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1552 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1553 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1559 return DAG.getMergeValues(Res, DL);
1562 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1563 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1565 EVT VT = Op.getValueType();
1566 SDValue X = Op.getOperand(0);
1567 SDValue Y = Op.getOperand(1);
1569 // TODO: Should this propagate fast-math-flags?
1571 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1572 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1573 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1575 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1578 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1580 SDValue Src = Op.getOperand(0);
1582 // result = trunc(src)
1583 // if (src > 0.0 && src != result)
1586 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1588 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1589 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1592 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1594 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1595 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1596 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1598 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1599 // TODO: Should this propagate fast-math-flags?
1600 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1603 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
1604 SelectionDAG &DAG) {
1605 const unsigned FractBits = 52;
1606 const unsigned ExpBits = 11;
1608 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1610 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1611 DAG.getConstant(ExpBits, SL, MVT::i32));
1612 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1613 DAG.getConstant(1023, SL, MVT::i32));
1618 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1620 SDValue Src = Op.getOperand(0);
1622 assert(Op.getValueType() == MVT::f64);
1624 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1625 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1627 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1629 // Extract the upper half, since this is where we will find the sign and
1631 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1633 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1635 const unsigned FractBits = 52;
1637 // Extract the sign bit.
1638 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1639 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1641 // Extend back to to 64-bits.
1642 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
1643 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1645 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1646 const SDValue FractMask
1647 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1649 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1650 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1651 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1654 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1656 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1658 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1659 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1661 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1662 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1664 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1667 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1669 SDValue Src = Op.getOperand(0);
1671 assert(Op.getValueType() == MVT::f64);
1673 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1674 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
1675 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1677 // TODO: Should this propagate fast-math-flags?
1679 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1680 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1682 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1684 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1685 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
1688 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1689 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1691 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1694 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1695 // FNEARBYINT and FRINT are the same, except in their handling of FP
1696 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1697 // rint, so just treat them as equivalent.
1698 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1701 // XXX - May require not supporting f32 denormals?
1702 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
1704 SDValue X = Op.getOperand(0);
1706 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
1708 // TODO: Should this propagate fast-math-flags?
1710 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
1712 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
1714 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
1715 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1716 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
1718 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
1721 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1723 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
1725 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
1727 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
1730 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
1732 SDValue X = Op.getOperand(0);
1734 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
1736 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1737 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1738 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
1739 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
1741 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1743 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1745 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
1747 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1749 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
1752 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
1753 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
1754 DAG.getConstant(INT64_C(0x0008000000000000), SL,
1758 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
1759 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
1760 DAG.getConstant(0, SL, MVT::i64), Tmp0,
1763 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
1764 D, DAG.getConstant(0, SL, MVT::i64));
1765 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
1767 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
1768 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
1770 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1771 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1772 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
1774 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
1776 DAG.getConstantFP(1.0, SL, MVT::f64),
1777 DAG.getConstantFP(0.0, SL, MVT::f64));
1779 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
1781 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
1782 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
1787 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
1788 EVT VT = Op.getValueType();
1791 return LowerFROUND32(Op, DAG);
1794 return LowerFROUND64(Op, DAG);
1796 llvm_unreachable("unhandled type");
1799 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1801 SDValue Src = Op.getOperand(0);
1803 // result = trunc(src);
1804 // if (src < 0.0 && src != result)
1807 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1809 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1810 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
1813 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1815 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1816 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1817 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1819 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1820 // TODO: Should this propagate fast-math-flags?
1821 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1824 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
1826 SDValue Src = Op.getOperand(0);
1827 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
1829 if (ZeroUndef && Src.getValueType() == MVT::i32)
1830 return DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Src);
1832 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1834 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1835 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1837 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1838 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1840 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1841 *DAG.getContext(), MVT::i32);
1843 SDValue Hi0 = DAG.getSetCC(SL, SetCCVT, Hi, Zero, ISD::SETEQ);
1845 SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo);
1846 SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);
1848 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
1849 SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32);
1851 // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
1852 SDValue NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0, Add, CtlzHi);
1855 // Test if the full 64-bit input is zero.
1857 // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
1858 // which we probably don't want.
1859 SDValue Lo0 = DAG.getSetCC(SL, SetCCVT, Lo, Zero, ISD::SETEQ);
1860 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0);
1862 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
1863 // with the same cycles, otherwise it is slower.
1864 // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
1865 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
1867 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
1869 // The instruction returns -1 for 0 input, but the defined intrinsic
1870 // behavior is to return the number of bits.
1871 NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32,
1872 SrcIsZero, Bits32, NewCtlz);
1875 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewCtlz);
1878 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
1879 bool Signed) const {
1883 // uint lz = clz(u);
1884 // uint e = (u != 0) ? 127U + 63U - lz : 0;
1885 // u = (u << lz) & 0x7fffffffffffffffUL;
1886 // ulong t = u & 0xffffffffffUL;
1887 // uint v = (e << 23) | (uint)(u >> 40);
1888 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
1889 // return as_float(v + r);
1894 // long s = l >> 63;
1895 // float r = cul2f((l + s) ^ s);
1896 // return s ? -r : r;
1900 SDValue Src = Op.getOperand(0);
1905 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
1906 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
1908 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
1909 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
1912 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1913 *DAG.getContext(), MVT::f32);
1916 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
1917 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
1918 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
1919 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
1921 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
1922 SDValue E = DAG.getSelect(SL, MVT::i32,
1923 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
1924 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
1927 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
1928 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
1929 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
1931 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
1932 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
1934 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
1935 U, DAG.getConstant(40, SL, MVT::i64));
1937 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
1938 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
1939 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
1941 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
1942 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
1943 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
1945 SDValue One = DAG.getConstant(1, SL, MVT::i32);
1947 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
1949 SDValue R = DAG.getSelect(SL, MVT::i32,
1952 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
1953 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
1954 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
1959 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
1960 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
1963 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1964 bool Signed) const {
1966 SDValue Src = Op.getOperand(0);
1968 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1970 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1971 DAG.getConstant(0, SL, MVT::i32));
1972 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1973 DAG.getConstant(1, SL, MVT::i32));
1975 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
1978 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
1980 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
1981 DAG.getConstant(32, SL, MVT::i32));
1982 // TODO: Should this propagate fast-math-flags?
1983 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
1986 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1987 SelectionDAG &DAG) const {
1988 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
1989 "operation should be legal");
1991 EVT DestVT = Op.getValueType();
1992 if (DestVT == MVT::f64)
1993 return LowerINT_TO_FP64(Op, DAG, false);
1995 if (DestVT == MVT::f32)
1996 return LowerINT_TO_FP32(Op, DAG, false);
2001 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2002 SelectionDAG &DAG) const {
2003 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2004 "operation should be legal");
2006 EVT DestVT = Op.getValueType();
2007 if (DestVT == MVT::f32)
2008 return LowerINT_TO_FP32(Op, DAG, true);
2010 if (DestVT == MVT::f64)
2011 return LowerINT_TO_FP64(Op, DAG, true);
2016 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2017 bool Signed) const {
2020 SDValue Src = Op.getOperand(0);
2022 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2024 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2026 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2028 // TODO: Should this propagate fast-math-flags?
2029 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2031 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2034 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2036 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2037 MVT::i32, FloorMul);
2038 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2040 SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2042 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2045 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2046 SelectionDAG &DAG) const {
2047 SDValue Src = Op.getOperand(0);
2049 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2050 return LowerFP64_TO_INT(Op, DAG, true);
2055 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2056 SelectionDAG &DAG) const {
2057 SDValue Src = Op.getOperand(0);
2059 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2060 return LowerFP64_TO_INT(Op, DAG, false);
2065 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2066 SelectionDAG &DAG) const {
2067 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2068 MVT VT = Op.getSimpleValueType();
2069 MVT ScalarVT = VT.getScalarType();
2074 SDValue Src = Op.getOperand(0);
2077 // TODO: Don't scalarize on Evergreen?
2078 unsigned NElts = VT.getVectorNumElements();
2079 SmallVector<SDValue, 8> Args;
2080 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2082 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2083 for (unsigned I = 0; I < NElts; ++I)
2084 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2086 return DAG.getBuildVector(VT, DL, Args);
2089 //===----------------------------------------------------------------------===//
2090 // Custom DAG optimizations
2091 //===----------------------------------------------------------------------===//
2093 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2094 APInt KnownZero, KnownOne;
2095 EVT VT = Op.getValueType();
2096 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2098 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2101 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2102 EVT VT = Op.getValueType();
2104 // In order for this to be a signed 24-bit value, bit 23, must
2106 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2107 // as unsigned 24-bit values.
2108 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2111 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2113 SelectionDAG &DAG = DCI.DAG;
2114 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2115 EVT VT = Op.getValueType();
2117 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2118 APInt KnownZero, KnownOne;
2119 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2120 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2121 DCI.CommitTargetLoweringOpt(TLO);
2124 template <typename IntTy>
2125 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2126 uint32_t Width, const SDLoc &DL) {
2127 if (Width + Offset < 32) {
2128 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2129 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2130 return DAG.getConstant(Result, DL, MVT::i32);
2133 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2136 static bool hasVolatileUser(SDNode *Val) {
2137 for (SDNode *U : Val->uses()) {
2138 if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2139 if (M->isVolatile())
2147 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2148 // i32 vectors are the canonical memory type.
2149 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2152 if (!VT.isByteSized())
2155 unsigned Size = VT.getStoreSize();
2157 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2160 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2166 // Replace load of an illegal type with a store of a bitcast to a friendlier
2168 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2169 DAGCombinerInfo &DCI) const {
2170 if (!DCI.isBeforeLegalize())
2173 LoadSDNode *LN = cast<LoadSDNode>(N);
2174 if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2178 SelectionDAG &DAG = DCI.DAG;
2179 EVT VT = LN->getMemoryVT();
2181 unsigned Size = VT.getStoreSize();
2182 unsigned Align = LN->getAlignment();
2183 if (Align < Size && isTypeLegal(VT)) {
2185 unsigned AS = LN->getAddressSpace();
2187 // Expand unaligned loads earlier than legalization. Due to visitation order
2188 // problems during legalization, the emitted instructions to pack and unpack
2189 // the bytes again are not eliminated in the case of an unaligned copy.
2190 if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2192 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2193 return DAG.getMergeValues(Ops, SDLoc(N));
2200 if (!shouldCombineMemoryType(VT))
2203 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2206 = DAG.getLoad(NewVT, SL, LN->getChain(),
2207 LN->getBasePtr(), LN->getMemOperand());
2209 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2210 DCI.CombineTo(N, BC, NewLoad.getValue(1));
2211 return SDValue(N, 0);
2214 // Replace store of an illegal type with a store of a bitcast to a friendlier
2216 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2217 DAGCombinerInfo &DCI) const {
2218 if (!DCI.isBeforeLegalize())
2221 StoreSDNode *SN = cast<StoreSDNode>(N);
2222 if (SN->isVolatile() || !ISD::isNormalStore(SN))
2225 EVT VT = SN->getMemoryVT();
2226 unsigned Size = VT.getStoreSize();
2229 SelectionDAG &DAG = DCI.DAG;
2230 unsigned Align = SN->getAlignment();
2231 if (Align < Size && isTypeLegal(VT)) {
2233 unsigned AS = SN->getAddressSpace();
2235 // Expand unaligned stores earlier than legalization. Due to visitation
2236 // order problems during legalization, the emitted instructions to pack and
2237 // unpack the bytes again are not eliminated in the case of an unaligned
2239 if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast))
2240 return expandUnalignedStore(SN, DAG);
2246 if (!shouldCombineMemoryType(VT))
2249 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2250 SDValue Val = SN->getValue();
2252 //DCI.AddToWorklist(Val.getNode());
2254 bool OtherUses = !Val.hasOneUse();
2255 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2257 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2258 DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2261 return DAG.getStore(SN->getChain(), SL, CastVal,
2262 SN->getBasePtr(), SN->getMemOperand());
2265 // TODO: Should repeat for other bit ops.
2266 SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N,
2267 DAGCombinerInfo &DCI) const {
2268 if (N->getValueType(0) != MVT::i64)
2271 // Break up 64-bit and of a constant into two 32-bit ands. This will typically
2272 // happen anyway for a VALU 64-bit and. This exposes other 32-bit integer
2273 // combine opportunities since most 64-bit operations are decomposed this way.
2274 // TODO: We won't want this for SALU especially if it is an inline immediate.
2275 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2279 uint64_t Val = RHS->getZExtValue();
2280 if (Lo_32(Val) != 0 && Hi_32(Val) != 0 && !RHS->hasOneUse()) {
2281 // If either half of the constant is 0, this is really a 32-bit and, so
2282 // split it. If we can re-use the full materialized constant, keep it.
2287 SelectionDAG &DAG = DCI.DAG;
2290 std::tie(Lo, Hi) = split64BitValue(N->getOperand(0), DAG);
2292 SDValue LoRHS = DAG.getConstant(Lo_32(Val), SL, MVT::i32);
2293 SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
2295 SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);
2296 SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);
2298 // Re-visit the ands. It's possible we eliminated one of them and it could
2299 // simplify the vector.
2300 DCI.AddToWorklist(Lo.getNode());
2301 DCI.AddToWorklist(Hi.getNode());
2303 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
2304 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2307 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2308 DAGCombinerInfo &DCI) const {
2309 if (N->getValueType(0) != MVT::i64)
2312 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
2314 // On some subtargets, 64-bit shift is a quarter rate instruction. In the
2315 // common case, splitting this into a move and a 32-bit shift is faster and
2316 // the same code size.
2317 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2321 unsigned RHSVal = RHS->getZExtValue();
2325 SDValue LHS = N->getOperand(0);
2328 SelectionDAG &DAG = DCI.DAG;
2330 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
2332 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2333 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
2335 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2337 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
2338 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2341 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
2342 DAGCombinerInfo &DCI) const {
2343 if (N->getValueType(0) != MVT::i64)
2346 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2350 SelectionDAG &DAG = DCI.DAG;
2352 unsigned RHSVal = RHS->getZExtValue();
2354 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
2356 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2357 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2358 DAG.getConstant(31, SL, MVT::i32));
2360 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
2361 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2364 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
2366 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2367 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2368 DAG.getConstant(31, SL, MVT::i32));
2369 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
2370 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2376 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
2377 DAGCombinerInfo &DCI) const {
2378 if (N->getValueType(0) != MVT::i64)
2381 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2385 unsigned ShiftAmt = RHS->getZExtValue();
2389 // srl i64:x, C for C >= 32
2391 // build_pair (srl hi_32(x), C - 32), 0
2393 SelectionDAG &DAG = DCI.DAG;
2396 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2397 SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2399 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
2400 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,
2403 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
2404 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
2406 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
2408 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
2411 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2412 DAGCombinerInfo &DCI) const {
2413 EVT VT = N->getValueType(0);
2415 if (VT.isVector() || VT.getSizeInBits() > 32)
2418 SelectionDAG &DAG = DCI.DAG;
2421 SDValue N0 = N->getOperand(0);
2422 SDValue N1 = N->getOperand(1);
2425 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2426 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2427 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2428 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2429 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2430 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2431 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2432 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2437 // We need to use sext even for MUL_U24, because MUL_U24 is used
2438 // for signed multiply of 8 and 16-bit types.
2439 return DAG.getSExtOrTrunc(Mul, DL, VT);
2442 static bool isNegativeOne(SDValue Val) {
2443 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
2444 return C->isAllOnesValue();
2448 static bool isCtlzOpc(unsigned Opc) {
2449 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2452 // Get FFBH node if the incoming op may have been type legalized from a smaller
2454 // Need to match pre-legalized type because the generic legalization inserts the
2455 // add/sub between the select and compare.
2456 static SDValue getFFBH_U32(const TargetLowering &TLI, SelectionDAG &DAG,
2457 const SDLoc &SL, SDValue Op) {
2458 EVT VT = Op.getValueType();
2459 EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2460 if (LegalVT != MVT::i32)
2464 Op = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Op);
2466 SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op);
2468 FFBH = DAG.getNode(ISD::TRUNCATE, SL, VT, FFBH);
2473 // The native instructions return -1 on 0 input. Optimize out a select that
2474 // produces -1 on 0.
2476 // TODO: If zero is not undef, we could also do this if the output is compared
2477 // against the bitwidth.
2479 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
2480 SDValue AMDGPUTargetLowering::performCtlzCombine(const SDLoc &SL, SDValue Cond,
2481 SDValue LHS, SDValue RHS,
2482 DAGCombinerInfo &DCI) const {
2483 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2484 if (!CmpRhs || !CmpRhs->isNullValue())
2487 SelectionDAG &DAG = DCI.DAG;
2488 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
2489 SDValue CmpLHS = Cond.getOperand(0);
2491 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
2492 if (CCOpcode == ISD::SETEQ &&
2493 isCtlzOpc(RHS.getOpcode()) &&
2494 RHS.getOperand(0) == CmpLHS &&
2495 isNegativeOne(LHS)) {
2496 return getFFBH_U32(*this, DAG, SL, CmpLHS);
2499 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
2500 if (CCOpcode == ISD::SETNE &&
2501 isCtlzOpc(LHS.getOpcode()) &&
2502 LHS.getOperand(0) == CmpLHS &&
2503 isNegativeOne(RHS)) {
2504 return getFFBH_U32(*this, DAG, SL, CmpLHS);
2510 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
2511 DAGCombinerInfo &DCI) const {
2512 SDValue Cond = N->getOperand(0);
2513 if (Cond.getOpcode() != ISD::SETCC)
2516 EVT VT = N->getValueType(0);
2517 SDValue LHS = Cond.getOperand(0);
2518 SDValue RHS = Cond.getOperand(1);
2519 SDValue CC = Cond.getOperand(2);
2521 SDValue True = N->getOperand(1);
2522 SDValue False = N->getOperand(2);
2524 if (VT == MVT::f32 && Cond.hasOneUse()) {
2526 = CombineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
2527 // Revisit this node so we can catch min3/max3/med3 patterns.
2528 //DCI.AddToWorklist(MinMax.getNode());
2532 // There's no reason to not do this if the condition has other uses.
2533 return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
2536 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2537 DAGCombinerInfo &DCI) const {
2538 SelectionDAG &DAG = DCI.DAG;
2541 switch(N->getOpcode()) {
2544 case ISD::BITCAST: {
2545 EVT DestVT = N->getValueType(0);
2546 if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
2549 // Fold bitcasts of constants.
2551 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
2552 // TODO: Generalize and move to DAGCombiner
2553 SDValue Src = N->getOperand(0);
2554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
2555 assert(Src.getValueType() == MVT::i64);
2557 uint64_t CVal = C->getZExtValue();
2558 return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,
2559 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
2560 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
2563 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
2564 const APInt &Val = C->getValueAPF().bitcastToAPInt();
2566 uint64_t CVal = Val.getZExtValue();
2567 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2568 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
2569 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
2571 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
2577 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2580 return performShlCombine(N, DCI);
2583 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2586 return performSrlCombine(N, DCI);
2589 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2592 return performSraCombine(N, DCI);
2595 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2598 return performAndCombine(N, DCI);
2601 return performMulCombine(N, DCI);
2602 case AMDGPUISD::MUL_I24:
2603 case AMDGPUISD::MUL_U24: {
2604 SDValue N0 = N->getOperand(0);
2605 SDValue N1 = N->getOperand(1);
2606 simplifyI24(N0, DCI);
2607 simplifyI24(N1, DCI);
2611 return performSelectCombine(N, DCI);
2612 case AMDGPUISD::BFE_I32:
2613 case AMDGPUISD::BFE_U32: {
2614 assert(!N->getValueType(0).isVector() &&
2615 "Vector handling of BFE not implemented");
2616 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2620 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2622 return DAG.getConstant(0, DL, MVT::i32);
2624 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2628 SDValue BitsFrom = N->getOperand(0);
2629 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2631 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2633 if (OffsetVal == 0) {
2634 // This is already sign / zero extended, so try to fold away extra BFEs.
2635 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2637 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2638 if (OpSignBits >= SignBits)
2641 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2643 // This is a sign_extend_inreg. Replace it to take advantage of existing
2644 // DAG Combines. If not eliminated, we will match back to BFE during
2647 // TODO: The sext_inreg of extended types ends, although we can could
2648 // handle them in a single BFE.
2649 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2650 DAG.getValueType(SmallVT));
2653 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2656 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2658 return constantFoldBFE<int32_t>(DAG,
2659 CVal->getSExtValue(),
2665 return constantFoldBFE<uint32_t>(DAG,
2666 CVal->getZExtValue(),
2672 if ((OffsetVal + WidthVal) >= 32) {
2673 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2674 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2675 BitsFrom, ShiftVal);
2678 if (BitsFrom.hasOneUse()) {
2679 APInt Demanded = APInt::getBitsSet(32,
2681 OffsetVal + WidthVal);
2683 APInt KnownZero, KnownOne;
2684 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2685 !DCI.isBeforeLegalizeOps());
2686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2687 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2688 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2689 KnownZero, KnownOne, TLO)) {
2690 DCI.CommitTargetLoweringOpt(TLO);
2697 return performLoadCombine(N, DCI);
2699 return performStoreCombine(N, DCI);
2704 //===----------------------------------------------------------------------===//
2706 //===----------------------------------------------------------------------===//
2708 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2711 const SmallVectorImpl<ISD::InputArg> &Ins,
2712 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2714 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2715 if (Ins[i].ArgVT == Ins[i].VT) {
2716 OrigIns.push_back(Ins[i]);
2721 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2722 // Vector has been split into scalars.
2723 VT = Ins[i].ArgVT.getVectorElementType();
2724 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2725 Ins[i].ArgVT.getVectorElementType() !=
2726 Ins[i].VT.getVectorElementType()) {
2727 // Vector elements have been promoted
2730 // Vector has been spilt into smaller vectors.
2734 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2735 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2736 OrigIns.push_back(Arg);
2740 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2741 const TargetRegisterClass *RC,
2742 unsigned Reg, EVT VT) const {
2743 MachineFunction &MF = DAG.getMachineFunction();
2744 MachineRegisterInfo &MRI = MF.getRegInfo();
2745 unsigned VirtualRegister;
2746 if (!MRI.isLiveIn(Reg)) {
2747 VirtualRegister = MRI.createVirtualRegister(RC);
2748 MRI.addLiveIn(Reg, VirtualRegister);
2750 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2752 return DAG.getRegister(VirtualRegister, VT);
2755 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2756 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2757 uint64_t ArgOffset = MFI->ABIArgOffset;
2762 return ArgOffset + 4;
2764 llvm_unreachable("unexpected implicit parameter type");
2767 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2769 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2770 switch ((AMDGPUISD::NodeType)Opcode) {
2771 case AMDGPUISD::FIRST_NUMBER: break;
2773 NODE_NAME_CASE(CALL);
2774 NODE_NAME_CASE(UMUL);
2775 NODE_NAME_CASE(BRANCH_COND);
2778 NODE_NAME_CASE(ENDPGM)
2779 NODE_NAME_CASE(RETURN)
2780 NODE_NAME_CASE(DWORDADDR)
2781 NODE_NAME_CASE(FRACT)
2782 NODE_NAME_CASE(CLAMP)
2783 NODE_NAME_CASE(COS_HW)
2784 NODE_NAME_CASE(SIN_HW)
2785 NODE_NAME_CASE(FMAX_LEGACY)
2786 NODE_NAME_CASE(FMIN_LEGACY)
2787 NODE_NAME_CASE(FMAX3)
2788 NODE_NAME_CASE(SMAX3)
2789 NODE_NAME_CASE(UMAX3)
2790 NODE_NAME_CASE(FMIN3)
2791 NODE_NAME_CASE(SMIN3)
2792 NODE_NAME_CASE(UMIN3)
2793 NODE_NAME_CASE(FMED3)
2794 NODE_NAME_CASE(SMED3)
2795 NODE_NAME_CASE(UMED3)
2796 NODE_NAME_CASE(URECIP)
2797 NODE_NAME_CASE(DIV_SCALE)
2798 NODE_NAME_CASE(DIV_FMAS)
2799 NODE_NAME_CASE(DIV_FIXUP)
2800 NODE_NAME_CASE(TRIG_PREOP)
2803 NODE_NAME_CASE(RSQ_LEGACY)
2804 NODE_NAME_CASE(RSQ_CLAMP)
2805 NODE_NAME_CASE(LDEXP)
2806 NODE_NAME_CASE(FP_CLASS)
2807 NODE_NAME_CASE(DOT4)
2808 NODE_NAME_CASE(CARRY)
2809 NODE_NAME_CASE(BORROW)
2810 NODE_NAME_CASE(BFE_U32)
2811 NODE_NAME_CASE(BFE_I32)
2814 NODE_NAME_CASE(FFBH_U32)
2815 NODE_NAME_CASE(MUL_U24)
2816 NODE_NAME_CASE(MUL_I24)
2817 NODE_NAME_CASE(MAD_U24)
2818 NODE_NAME_CASE(MAD_I24)
2819 NODE_NAME_CASE(TEXTURE_FETCH)
2820 NODE_NAME_CASE(EXPORT)
2821 NODE_NAME_CASE(CONST_ADDRESS)
2822 NODE_NAME_CASE(REGISTER_LOAD)
2823 NODE_NAME_CASE(REGISTER_STORE)
2824 NODE_NAME_CASE(LOAD_INPUT)
2825 NODE_NAME_CASE(SAMPLE)
2826 NODE_NAME_CASE(SAMPLEB)
2827 NODE_NAME_CASE(SAMPLED)
2828 NODE_NAME_CASE(SAMPLEL)
2829 NODE_NAME_CASE(CVT_F32_UBYTE0)
2830 NODE_NAME_CASE(CVT_F32_UBYTE1)
2831 NODE_NAME_CASE(CVT_F32_UBYTE2)
2832 NODE_NAME_CASE(CVT_F32_UBYTE3)
2833 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2834 NODE_NAME_CASE(CONST_DATA_PTR)
2835 NODE_NAME_CASE(PC_ADD_REL_OFFSET)
2836 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2837 NODE_NAME_CASE(SENDMSG)
2838 NODE_NAME_CASE(INTERP_MOV)
2839 NODE_NAME_CASE(INTERP_P1)
2840 NODE_NAME_CASE(INTERP_P2)
2841 NODE_NAME_CASE(STORE_MSKOR)
2842 NODE_NAME_CASE(LOAD_CONSTANT)
2843 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2844 NODE_NAME_CASE(ATOMIC_CMP_SWAP)
2845 NODE_NAME_CASE(ATOMIC_INC)
2846 NODE_NAME_CASE(ATOMIC_DEC)
2847 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2852 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2853 DAGCombinerInfo &DCI,
2854 unsigned &RefinementSteps,
2855 bool &UseOneConstNR) const {
2856 SelectionDAG &DAG = DCI.DAG;
2857 EVT VT = Operand.getValueType();
2859 if (VT == MVT::f32) {
2860 RefinementSteps = 0;
2861 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2864 // TODO: There is also f64 rsq instruction, but the documentation is less
2865 // clear on its precision.
2870 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2871 DAGCombinerInfo &DCI,
2872 unsigned &RefinementSteps) const {
2873 SelectionDAG &DAG = DCI.DAG;
2874 EVT VT = Operand.getValueType();
2876 if (VT == MVT::f32) {
2877 // Reciprocal, < 1 ulp error.
2879 // This reciprocal approximation converges to < 0.5 ulp error with one
2880 // newton rhapson performed with two fused multiple adds (FMAs).
2882 RefinementSteps = 0;
2883 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2886 // TODO: There is also f64 rcp instruction, but the documentation is less
2887 // clear on its precision.
2892 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2896 const SelectionDAG &DAG,
2897 unsigned Depth) const {
2899 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2903 unsigned Opc = Op.getOpcode();
2908 case AMDGPUISD::CARRY:
2909 case AMDGPUISD::BORROW: {
2910 KnownZero = APInt::getHighBitsSet(32, 31);
2914 case AMDGPUISD::BFE_I32:
2915 case AMDGPUISD::BFE_U32: {
2916 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2920 unsigned BitWidth = 32;
2921 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2923 if (Opc == AMDGPUISD::BFE_U32)
2924 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2931 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2933 const SelectionDAG &DAG,
2934 unsigned Depth) const {
2935 switch (Op.getOpcode()) {
2936 case AMDGPUISD::BFE_I32: {
2937 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2941 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2942 if (!isNullConstant(Op.getOperand(1)))
2945 // TODO: Could probably figure something out with non-0 offsets.
2946 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2947 return std::max(SignBits, Op0SignBits);
2950 case AMDGPUISD::BFE_U32: {
2951 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2952 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2955 case AMDGPUISD::CARRY:
2956 case AMDGPUISD::BORROW: