1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
30 /// legalized from a smaller type VT. Need to match pre-legalized type because
31 /// the generic legalization inserts the add/sub between the select and
33 SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
36 const AMDGPUSubtarget *Subtarget;
38 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
41 /// \brief Split a vector store into multiple scalar stores.
42 /// \returns The resulting chain.
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
67 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
70 bool shouldCombineMemoryType(EVT VT) const;
71 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
75 unsigned Opc, SDValue LHS,
76 uint32_t ValLo, uint32_t ValHi) const;
77 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83 SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
84 SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
85 SDValue RHS, DAGCombinerInfo &DCI) const;
86 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
91 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
92 SelectionDAG &DAG) const;
94 /// Return 64-bit value Op as two 32-bit integers.
95 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
96 SelectionDAG &DAG) const;
97 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
98 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
100 /// \brief Split a vector load into 2 loads of half the vector.
101 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
103 /// \brief Split a vector store into 2 stores of half the vector.
104 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
110 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
111 SmallVectorImpl<SDValue> &Results) const;
112 void analyzeFormalArgumentsCompute(CCState &State,
113 const SmallVectorImpl<ISD::InputArg> &Ins) const;
114 void AnalyzeFormalArguments(CCState &State,
115 const SmallVectorImpl<ISD::InputArg> &Ins) const;
116 void AnalyzeReturn(CCState &State,
117 const SmallVectorImpl<ISD::OutputArg> &Outs) const;
120 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
122 bool mayIgnoreSignedZero(SDValue Op) const {
123 if (getTargetMachine().Options.UnsafeFPMath) // FIXME: nsz only
126 if (const auto *BO = dyn_cast<BinaryWithFlagsSDNode>(Op))
127 return BO->Flags.hasNoSignedZeros();
132 bool isFAbsFree(EVT VT) const override;
133 bool isFNegFree(EVT VT) const override;
134 bool isTruncateFree(EVT Src, EVT Dest) const override;
135 bool isTruncateFree(Type *Src, Type *Dest) const override;
137 bool isZExtFree(Type *Src, Type *Dest) const override;
138 bool isZExtFree(EVT Src, EVT Dest) const override;
139 bool isZExtFree(SDValue Val, EVT VT2) const override;
141 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
143 MVT getVectorIdxTy(const DataLayout &) const override;
144 bool isSelectSupported(SelectSupportKind) const override;
146 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
147 bool ShouldShrinkFPConstant(EVT VT) const override;
148 bool shouldReduceLoadWidth(SDNode *Load,
149 ISD::LoadExtType ExtType,
150 EVT ExtVT) const override;
152 bool isLoadBitCastBeneficial(EVT, EVT) const final;
154 bool storeOfVectorConstantIsCheap(EVT MemVT,
156 unsigned AS) const override;
157 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
158 bool isCheapToSpeculateCttz() const override;
159 bool isCheapToSpeculateCtlz() const override;
161 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
164 SelectionDAG &DAG) const override;
165 SDValue LowerCall(CallLoweringInfo &CLI,
166 SmallVectorImpl<SDValue> &InVals) const override;
168 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
169 SelectionDAG &DAG) const;
171 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
172 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
173 void ReplaceNodeResults(SDNode * N,
174 SmallVectorImpl<SDValue> &Results,
175 SelectionDAG &DAG) const override;
177 SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
178 SDValue RHS, SDValue True, SDValue False,
179 SDValue CC, DAGCombinerInfo &DCI) const;
181 const char* getTargetNodeName(unsigned Opcode) const override;
183 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
186 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
187 int &RefinementSteps, bool &UseOneConstNR,
188 bool Reciprocal) const override;
189 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
190 int &RefinementSteps) const override;
192 virtual SDNode *PostISelFolding(MachineSDNode *N,
193 SelectionDAG &DAG) const = 0;
195 /// \brief Determine which of the bits specified in \p Mask are known to be
196 /// either zero or one and return them in the \p KnownZero and \p KnownOne
198 void computeKnownBitsForTargetNode(const SDValue Op,
201 const SelectionDAG &DAG,
202 unsigned Depth = 0) const override;
204 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
205 unsigned Depth = 0) const override;
207 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
210 /// \returns a RegisterSDNode representing Reg.
211 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
212 const TargetRegisterClass *RC,
213 unsigned Reg, EVT VT) const;
215 enum ImplicitParameter {
217 GRID_DIM = FIRST_IMPLICIT,
221 /// \brief Helper function that returns the byte offset of the given
222 /// type of implicit parameter.
223 uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
224 const ImplicitParameter Param) const;
227 namespace AMDGPUISD {
229 enum NodeType : unsigned {
231 FIRST_NUMBER = ISD::BUILTIN_OP_END,
232 CALL, // Function call based on a single integer
233 UMUL, // 32bit unsigned multiplication
235 // End AMDIL ISD Opcodes
241 // This is SETCC with the full mask result which is used for a compare with a
242 // result bit per item in the wavefront.
245 // FP ops with input and output chain.
249 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
250 // Denormals handled on some parts.
268 TRIG_PREOP, // 1 ULP max error for f64
270 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
271 // For f64, max error 2^29 ULP, handles denormals.
283 BFE_U32, // Extract range of bits with zero extension to 32-bits.
284 BFE_I32, // Extract range of bits with sign extension to 32-bits.
285 BFI, // (src0 & src1) | (~src0 & src2)
286 BFM, // Insert a range of bits into a 32-bit word.
287 FFBH_U32, // ctlz with -1 if input is zero.
298 EXPORT, // exp on SI+
299 EXPORT_DONE, // exp on SI+ with done bit set
310 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
315 /// This node is for VLIW targets and it is used to represent a vector
316 /// that is stored in consecutive registers with the same channel.
323 BUILD_VERTICAL_VECTOR,
324 /// Pointer to the start of the shader's constant data.
334 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
337 TBUFFER_STORE_FORMAT,
343 LAST_AMDGPU_ISD_NUMBER
347 } // End namespace AMDGPUISD
349 } // End namespace llvm