1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/Target/TargetLowering.h"
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 class MachineRegisterInfo;
29 class AMDGPUTargetLowering : public TargetLowering {
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
35 SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
38 const AMDGPUSubtarget *Subtarget;
41 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
60 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
61 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
67 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
69 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
72 bool shouldCombineMemoryType(EVT VT) const;
73 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
77 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
78 unsigned Opc, SDValue LHS,
79 uint32_t ValLo, uint32_t ValHi) const;
80 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
85 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86 SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
87 SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
88 SDValue RHS, DAGCombinerInfo &DCI) const;
89 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
95 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
96 SelectionDAG &DAG) const;
98 /// Return 64-bit value Op as two 32-bit integers.
99 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
100 SelectionDAG &DAG) const;
101 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
102 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
104 /// \brief Split a vector load into 2 loads of half the vector.
105 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
107 /// \brief Split a vector store into 2 stores of half the vector.
108 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
114 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
115 SmallVectorImpl<SDValue> &Results) const;
116 void analyzeFormalArgumentsCompute(CCState &State,
117 const SmallVectorImpl<ISD::InputArg> &Ins) const;
118 void AnalyzeReturn(CCState &State,
119 const SmallVectorImpl<ISD::OutputArg> &Outs) const;
122 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
124 bool mayIgnoreSignedZero(SDValue Op) const {
125 if (getTargetMachine().Options.NoSignedZerosFPMath)
128 const auto Flags = Op.getNode()->getFlags();
129 if (Flags.isDefined())
130 return Flags.hasNoSignedZeros();
135 bool isFAbsFree(EVT VT) const override;
136 bool isFNegFree(EVT VT) const override;
137 bool isTruncateFree(EVT Src, EVT Dest) const override;
138 bool isTruncateFree(Type *Src, Type *Dest) const override;
140 bool isZExtFree(Type *Src, Type *Dest) const override;
141 bool isZExtFree(EVT Src, EVT Dest) const override;
142 bool isZExtFree(SDValue Val, EVT VT2) const override;
144 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
146 MVT getVectorIdxTy(const DataLayout &) const override;
147 bool isSelectSupported(SelectSupportKind) const override;
149 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
150 bool ShouldShrinkFPConstant(EVT VT) const override;
151 bool shouldReduceLoadWidth(SDNode *Load,
152 ISD::LoadExtType ExtType,
153 EVT ExtVT) const override;
155 bool isLoadBitCastBeneficial(EVT, EVT) const final;
157 bool storeOfVectorConstantIsCheap(EVT MemVT,
159 unsigned AS) const override;
160 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
161 bool isCheapToSpeculateCttz() const override;
162 bool isCheapToSpeculateCtlz() const override;
164 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
165 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
168 SelectionDAG &DAG) const override;
169 SDValue LowerCall(CallLoweringInfo &CLI,
170 SmallVectorImpl<SDValue> &InVals) const override;
172 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
173 SelectionDAG &DAG) const;
175 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
176 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
177 void ReplaceNodeResults(SDNode * N,
178 SmallVectorImpl<SDValue> &Results,
179 SelectionDAG &DAG) const override;
181 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
182 SDValue RHS, SDValue True, SDValue False,
183 SDValue CC, DAGCombinerInfo &DCI) const;
185 const char* getTargetNodeName(unsigned Opcode) const override;
187 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
190 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
191 int &RefinementSteps, bool &UseOneConstNR,
192 bool Reciprocal) const override;
193 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
194 int &RefinementSteps) const override;
196 virtual SDNode *PostISelFolding(MachineSDNode *N,
197 SelectionDAG &DAG) const = 0;
199 /// \brief Determine which of the bits specified in \p Mask are known to be
200 /// either zero or one and return them in the \p KnownZero and \p KnownOne
202 void computeKnownBitsForTargetNode(const SDValue Op,
204 const APInt &DemandedElts,
205 const SelectionDAG &DAG,
206 unsigned Depth = 0) const override;
208 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
209 const SelectionDAG &DAG,
210 unsigned Depth = 0) const override;
212 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
215 /// \returns a RegisterSDNode representing Reg.
216 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
217 const TargetRegisterClass *RC,
218 unsigned Reg, EVT VT) const;
220 enum ImplicitParameter {
222 GRID_DIM = FIRST_IMPLICIT,
226 /// \brief Helper function that returns the byte offset of the given
227 /// type of implicit parameter.
228 uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
229 const ImplicitParameter Param) const;
231 AMDGPUAS getAMDGPUAS() const {
235 MVT getFenceOperandTy(const DataLayout &DL) const override {
240 namespace AMDGPUISD {
242 enum NodeType : unsigned {
244 FIRST_NUMBER = ISD::BUILTIN_OP_END,
245 UMUL, // 32bit unsigned multiplication
247 // End AMDIL ISD Opcodes
253 // Masked control flow nodes.
258 // A uniform kernel return that terminates the wavefront.
261 // Return to a shader part's epilog code.
264 // Return with values from a non-entry function.
270 /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
271 /// modifier behavior with dx10_enable.
274 // This is SETCC with the full mask result which is used for a compare with a
275 // result bit per item in the wavefront.
278 // FP ops with input and output chain.
282 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
283 // Denormals handled on some parts.
301 // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
302 // treated as an illegal operation.
304 TRIG_PREOP, // 1 ULP max error for f64
306 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
307 // For f64, max error 2^29 ULP, handles denormals.
319 BFE_U32, // Extract range of bits with zero extension to 32-bits.
320 BFE_I32, // Extract range of bits with sign extension to 32-bits.
321 BFI, // (src0 & src1) | (~src0 & src2)
322 BFM, // Insert a range of bits into a 32-bit word.
323 FFBH_U32, // ctlz with -1 if input is zero.
334 EXPORT, // exp on SI+
335 EXPORT_DONE, // exp on SI+ with done bit set
345 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
351 // Convert two float 32 numbers into a single register holding two packed f16
352 // with round to zero.
355 // Same as the standard node, except the high bits of the resulting integer
359 // Wrapper around fp16 results that are known to zero the high bits.
362 /// This node is for VLIW targets and it is used to represent a vector
363 /// that is stored in consecutive registers with the same channel.
370 BUILD_VERTICAL_VECTOR,
371 /// Pointer to the start of the shader's constant data.
374 INIT_EXEC_FROM_INPUT,
383 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
386 TBUFFER_STORE_FORMAT,
392 LAST_AMDGPU_ISD_NUMBER
396 } // End namespace AMDGPUISD
398 } // End namespace llvm