1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #define GET_INSTRINFO_ENUM
24 #include "AMDGPUGenInstrInfo.inc"
28 class AMDGPUSubtarget;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
35 const AMDGPUSubtarget &ST;
37 virtual void anchor();
40 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
42 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
43 int64_t Offset1, int64_t Offset2,
44 unsigned NumLoads) const override;
46 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
47 /// Return -1 if the target-specific opcode for the pseudo instruction does
48 /// not exist. If Opcode is not a pseudo instruction, this is identity.
49 int pseudoToMCOpcode(int Opcode) const;
51 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
52 /// equivalent opcode that writes \p Channels Channels.
53 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
55 } // End llvm namespace