1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
34 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
38 // float, float, float, vcc
39 def AMDGPUFmasOp : SDTypeProfile<1, 4,
40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
43 //===----------------------------------------------------------------------===//
47 def AMDGPUconstdata_ptr : SDNode<
48 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
52 // This argument to this node is a dword address.
53 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
55 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
56 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
59 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
62 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
64 // out = 1.0 / sqrt(a)
65 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
67 // out = 1.0 / sqrt(a)
68 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
70 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
71 def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
73 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
75 def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
77 // out = max(a, b) a and b are floats, where a nan comparison fails.
78 // This is not commutative because this gives the second operand:
79 // x < nan ? x : nan -> nan
80 // nan < x ? nan : x -> x
81 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
85 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
87 // out = max(a, b) a and b are signed ints
88 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
89 [SDNPCommutative, SDNPAssociative]
92 // out = max(a, b) a and b are unsigned ints
93 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
94 [SDNPCommutative, SDNPAssociative]
97 // out = min(a, b) a and b are floats, where a nan comparison fails.
98 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
102 // FIXME: TableGen doesn't like commutative instructions with more
104 // out = max(a, b, c) a, b and c are floats
105 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
106 [/*SDNPCommutative, SDNPAssociative*/]
109 // out = max(a, b, c) a, b, and c are signed ints
110 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
111 [/*SDNPCommutative, SDNPAssociative*/]
114 // out = max(a, b, c) a, b and c are unsigned ints
115 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
116 [/*SDNPCommutative, SDNPAssociative*/]
119 // out = min(a, b, c) a, b and c are floats
120 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
121 [/*SDNPCommutative, SDNPAssociative*/]
124 // out = min(a, b, c) a, b and c are signed ints
125 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
126 [/*SDNPCommutative, SDNPAssociative*/]
129 // out = min(a, b) a and b are unsigned ints
130 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
131 [/*SDNPCommutative, SDNPAssociative*/]
134 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
135 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
137 // out = (src1 > src0) ? 1 : 0
138 def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
141 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
143 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
145 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
147 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
151 // urecip - This operation is a helper for integer division, it returns the
152 // result of 1 / a as a fractional unsigned integer.
153 // out = (2^32 / a) + e
154 // e is rounding error
155 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
157 // Special case divide preop and flags.
158 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
160 // Special case divide FMA with scale and flags (src0 = Quotient,
161 // src1 = Denominator, src2 = Numerator).
162 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
164 // Single or double precision division fixup.
165 // Special case divide fixup and flags(src0 = Quotient, src1 =
166 // Denominator, src2 = Numerator).
167 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
169 // Look Up 2.0 / pi src0 with segment select src1[4:0]
170 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
172 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
173 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
174 [SDNPHasChain, SDNPMayLoad]>;
176 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
177 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
178 [SDNPHasChain, SDNPMayStore]>;
180 // MSKOR instructions are atomic memory instructions used mainly for storing
181 // 8-bit and 16-bit values. The definition is:
183 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
185 // src0: vec4(src, 0, 0, mask)
186 // src1: dst - rat offset (aka pointer) in dwords
187 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
188 SDTypeProfile<0, 2, []>,
189 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
191 def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
192 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
193 [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
196 def AMDGPUround : SDNode<"ISD::FROUND",
197 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
199 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
200 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
201 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
202 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
204 def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
206 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
207 // performing the mulitply. The result is a 32-bit value.
208 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
211 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
215 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
218 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
222 def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
226 def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
230 def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
232 def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
233 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
234 [SDNPHasChain, SDNPInGlue]>;
236 def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
237 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
240 def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
241 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
242 [SDNPInGlue, SDNPOutGlue]>;
244 def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
245 SDTypeProfile<1, 4, [SDTCisFP<0>]>,
248 //===----------------------------------------------------------------------===//
249 // Flow Control Profile Types
250 //===----------------------------------------------------------------------===//
251 // Branch instruction where second and third are basic blocks
252 def SDTIL_BRCond : SDTypeProfile<0, 2, [
256 //===----------------------------------------------------------------------===//
257 // Flow Control DAG Nodes
258 //===----------------------------------------------------------------------===//
259 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
261 //===----------------------------------------------------------------------===//
262 // Call/Return DAG Nodes
263 //===----------------------------------------------------------------------===//
264 def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
265 [SDNPHasChain, SDNPOptInGlue]>;
267 def AMDGPUreturn : SDNode<"AMDGPUISD::RETURN", SDTNone,
268 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;