1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
34 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
38 // float, float, float, vcc
39 def AMDGPUFmasOp : SDTypeProfile<1, 4,
40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
43 def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
45 //===----------------------------------------------------------------------===//
49 def AMDGPUconstdata_ptr : SDNode<
50 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
54 // This argument to this node is a dword address.
55 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
57 // Force dependencies for vector trunc stores
58 def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
60 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
61 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
64 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
67 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
69 // out = 1.0 / sqrt(a)
70 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
72 // out = 1.0 / sqrt(a)
73 def AMDGPUrcp_legacy : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
74 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
76 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
77 def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
79 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
81 def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
83 // out = max(a, b) a and b are floats, where a nan comparison fails.
84 // This is not commutative because this gives the second operand:
85 // x < nan ? x : nan -> nan
86 // nan < x ? nan : x -> x
87 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
91 def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
92 [SDNPCommutative, SDNPAssociative]
95 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
97 // out = max(a, b) a and b are signed ints
98 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
99 [SDNPCommutative, SDNPAssociative]
102 // out = max(a, b) a and b are unsigned ints
103 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
104 [SDNPCommutative, SDNPAssociative]
107 // out = min(a, b) a and b are floats, where a nan comparison fails.
108 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
112 // FIXME: TableGen doesn't like commutative instructions with more
114 // out = max(a, b, c) a, b and c are floats
115 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
116 [/*SDNPCommutative, SDNPAssociative*/]
119 // out = max(a, b, c) a, b, and c are signed ints
120 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
121 [/*SDNPCommutative, SDNPAssociative*/]
124 // out = max(a, b, c) a, b and c are unsigned ints
125 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
126 [/*SDNPCommutative, SDNPAssociative*/]
129 // out = min(a, b, c) a, b and c are floats
130 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
131 [/*SDNPCommutative, SDNPAssociative*/]
134 // out = min(a, b, c) a, b and c are signed ints
135 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
136 [/*SDNPCommutative, SDNPAssociative*/]
139 // out = min(a, b) a and b are unsigned ints
140 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
141 [/*SDNPCommutative, SDNPAssociative*/]
144 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
145 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
147 // out = (src1 > src0) ? 1 : 0
148 def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
150 def AMDGPUSetCCOp : SDTypeProfile<1, 3, [ // setcc
151 SDTCisVT<0, i64>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
154 def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
156 def AMDGPUSetRegOp : SDTypeProfile<0, 2, [
157 SDTCisInt<0>, SDTCisInt<1>
160 def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
161 SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
163 def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
164 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
166 def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
167 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
171 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
173 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
175 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
179 // urecip - This operation is a helper for integer division, it returns the
180 // result of 1 / a as a fractional unsigned integer.
181 // out = (2^32 / a) + e
182 // e is rounding error
183 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
185 // Special case divide preop and flags.
186 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
188 // Special case divide FMA with scale and flags (src0 = Quotient,
189 // src1 = Denominator, src2 = Numerator).
190 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
192 // Single or double precision division fixup.
193 // Special case divide fixup and flags(src0 = Quotient, src1 =
194 // Denominator, src2 = Numerator).
195 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
197 // Look Up 2.0 / pi src0 with segment select src1[4:0]
198 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
200 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
201 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
202 [SDNPHasChain, SDNPMayLoad]>;
204 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
205 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
206 [SDNPHasChain, SDNPMayStore]>;
208 // MSKOR instructions are atomic memory instructions used mainly for storing
209 // 8-bit and 16-bit values. The definition is:
211 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
213 // src0: vec4(src, 0, 0, mask)
214 // src1: dst - rat offset (aka pointer) in dwords
215 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
216 SDTypeProfile<0, 2, []>,
217 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
219 def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
220 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
221 [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
224 def AMDGPUround : SDNode<"ISD::FROUND",
225 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
227 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
228 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
229 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
230 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
232 def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
233 def AMDGPUffbh_i32 : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
235 // Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
236 // when performing the mulitply. The result is a 32-bit value.
237 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
238 [SDNPCommutative, SDNPAssociative]
240 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
241 [SDNPCommutative, SDNPAssociative]
244 def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
245 [SDNPCommutative, SDNPAssociative]
247 def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
248 [SDNPCommutative, SDNPAssociative]
251 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
254 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
258 def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
262 def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
266 def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
268 def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
269 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
270 [SDNPHasChain, SDNPInGlue]>;
272 def AMDGPUsendmsghalt : SDNode<"AMDGPUISD::SENDMSGHALT",
273 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
274 [SDNPHasChain, SDNPInGlue]>;
276 def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
277 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
280 def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
281 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
282 [SDNPInGlue, SDNPOutGlue]>;
284 def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
285 SDTypeProfile<1, 4, [SDTCisFP<0>]>,
289 def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
290 [SDNPHasChain, SDNPSideEffect]>;
293 def AMDGPUExportOp : SDTypeProfile<0, 8, [
294 SDTCisInt<0>, // i8 en
295 SDTCisInt<1>, // i1 vm
297 SDTCisInt<2>, // i8 tgt
298 SDTCisSameAs<3, 1>, // i1 compr
299 SDTCisFP<4>, // f32 src0
300 SDTCisSameAs<5, 4>, // f32 src1
301 SDTCisSameAs<6, 4>, // f32 src2
302 SDTCisSameAs<7, 4> // f32 src3
305 def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
306 [SDNPHasChain, SDNPMayStore]>;
308 def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
309 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
312 def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
314 def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
315 [SDNPHasChain, SDNPSideEffect]>;
317 //===----------------------------------------------------------------------===//
318 // Flow Control Profile Types
319 //===----------------------------------------------------------------------===//
320 // Branch instruction where second and third are basic blocks
321 def SDTIL_BRCond : SDTypeProfile<0, 2, [
325 //===----------------------------------------------------------------------===//
326 // Flow Control DAG Nodes
327 //===----------------------------------------------------------------------===//
328 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
330 //===----------------------------------------------------------------------===//
331 // Call/Return DAG Nodes
332 //===----------------------------------------------------------------------===//
333 def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
334 [SDNPHasChain, SDNPOptInGlue]>;
336 def AMDGPUreturn : SDNode<"AMDGPUISD::RETURN", SDTNone,
337 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;