1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
34 def AMDGPUFPPackOp : SDTypeProfile<1, 2,
35 [SDTCisFP<1>, SDTCisSameAs<1, 2>]
38 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
39 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
42 // float, float, float, vcc
43 def AMDGPUFmasOp : SDTypeProfile<1, 4,
44 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
47 def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
49 def AMDGPUIfOp : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
53 def AMDGPUElseOp : SDTypeProfile<1, 2,
54 [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, OtherVT>]
57 def AMDGPULoopOp : SDTypeProfile<0, 2,
58 [SDTCisVT<0, i64>, SDTCisVT<1, OtherVT>]
61 def AMDGPUBreakOp : SDTypeProfile<1, 1,
62 [SDTCisVT<0, i64>, SDTCisVT<1, i64>]
65 def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
66 [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, i64>]
69 def AMDGPUElseBreakOp : SDTypeProfile<1, 2,
70 [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, i64>]
73 //===----------------------------------------------------------------------===//
77 def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
78 def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
79 def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
81 def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
82 SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
83 [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
86 def AMDGPUconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
91 // This argument to this node is a dword address.
92 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
94 // Force dependencies for vector trunc stores
95 def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
97 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
98 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
100 // out = a - floor(a)
101 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
104 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
106 // out = 1.0 / sqrt(a)
107 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
109 // out = 1.0 / sqrt(a)
110 def AMDGPUrcp_legacy : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
111 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
113 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
114 def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
116 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
118 def AMDGPUpkrtz_f16_f32 : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
119 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
120 def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
123 def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
125 // out = max(a, b) a and b are floats, where a nan comparison fails.
126 // This is not commutative because this gives the second operand:
127 // x < nan ? x : nan -> nan
128 // nan < x ? nan : x -> x
129 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
133 def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
134 [SDNPCommutative, SDNPAssociative]
137 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPUnaryOp>;
139 // out = min(a, b) a and b are floats, where a nan comparison fails.
140 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
144 // FIXME: TableGen doesn't like commutative instructions with more
146 // out = max(a, b, c) a, b and c are floats
147 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
148 [/*SDNPCommutative, SDNPAssociative*/]
151 // out = max(a, b, c) a, b, and c are signed ints
152 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
153 [/*SDNPCommutative, SDNPAssociative*/]
156 // out = max(a, b, c) a, b and c are unsigned ints
157 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
158 [/*SDNPCommutative, SDNPAssociative*/]
161 // out = min(a, b, c) a, b and c are floats
162 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
163 [/*SDNPCommutative, SDNPAssociative*/]
166 // out = min(a, b, c) a, b and c are signed ints
167 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
168 [/*SDNPCommutative, SDNPAssociative*/]
171 // out = min(a, b) a and b are unsigned ints
172 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
173 [/*SDNPCommutative, SDNPAssociative*/]
176 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
177 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
179 // out = (src1 > src0) ? 1 : 0
180 def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
182 def AMDGPUSetCCOp : SDTypeProfile<1, 3, [ // setcc
183 SDTCisVT<0, i64>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
186 def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
188 def AMDGPUSetRegOp : SDTypeProfile<0, 2, [
189 SDTCisInt<0>, SDTCisInt<1>
192 def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
193 SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
195 def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
196 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
198 def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
199 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
201 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
203 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
205 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
207 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
211 // urecip - This operation is a helper for integer division, it returns the
212 // result of 1 / a as a fractional unsigned integer.
213 // out = (2^32 / a) + e
214 // e is rounding error
215 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
217 // Special case divide preop and flags.
218 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
220 // Special case divide FMA with scale and flags (src0 = Quotient,
221 // src1 = Denominator, src2 = Numerator).
222 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
224 // Single or double precision division fixup.
225 // Special case divide fixup and flags(src0 = Quotient, src1 =
226 // Denominator, src2 = Numerator).
227 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
229 def AMDGPUfmad_ftz : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
231 // Look Up 2.0 / pi src0 with segment select src1[4:0]
232 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
234 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
235 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
236 [SDNPHasChain, SDNPMayLoad]>;
238 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
239 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
240 [SDNPHasChain, SDNPMayStore]>;
242 // MSKOR instructions are atomic memory instructions used mainly for storing
243 // 8-bit and 16-bit values. The definition is:
245 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
247 // src0: vec4(src, 0, 0, mask)
248 // src1: dst - rat offset (aka pointer) in dwords
249 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
250 SDTypeProfile<0, 2, []>,
251 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
253 def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
254 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
255 [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
258 def AMDGPUround : SDNode<"ISD::FROUND",
259 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
261 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
262 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
263 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
264 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
266 def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
267 def AMDGPUffbh_i32 : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
269 // Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
270 // when performing the mulitply. The result is a 32-bit value.
271 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
272 [SDNPCommutative, SDNPAssociative]
274 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
275 [SDNPCommutative, SDNPAssociative]
278 def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
279 [SDNPCommutative, SDNPAssociative]
281 def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
282 [SDNPCommutative, SDNPAssociative]
285 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
288 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
292 def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
296 def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
300 def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
302 def AMDGPUinit_exec : SDNode<"AMDGPUISD::INIT_EXEC",
303 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
304 [SDNPHasChain, SDNPInGlue]>;
306 def AMDGPUinit_exec_from_input : SDNode<"AMDGPUISD::INIT_EXEC_FROM_INPUT",
308 [SDTCisInt<0>, SDTCisInt<1>]>,
309 [SDNPHasChain, SDNPInGlue]>;
311 def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
312 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
313 [SDNPHasChain, SDNPInGlue]>;
315 def AMDGPUsendmsghalt : SDNode<"AMDGPUISD::SENDMSGHALT",
316 SDTypeProfile<0, 1, [SDTCisInt<0>]>,
317 [SDNPHasChain, SDNPInGlue]>;
319 def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
320 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
323 def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
324 SDTypeProfile<1, 3, [SDTCisFP<0>]>,
325 [SDNPInGlue, SDNPOutGlue]>;
327 def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
328 SDTypeProfile<1, 4, [SDTCisFP<0>]>,
332 def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
333 [SDNPHasChain, SDNPSideEffect]>;
336 def AMDGPUExportOp : SDTypeProfile<0, 8, [
337 SDTCisInt<0>, // i8 tgt
338 SDTCisInt<1>, // i8 en
340 SDTCisSameAs<3, 2>, // f32 src1
341 SDTCisSameAs<4, 2>, // f32 src2
342 SDTCisSameAs<5, 2>, // f32 src3
343 SDTCisInt<6>, // i1 compr
345 SDTCisInt<1> // i1 vm
349 def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
350 [SDNPHasChain, SDNPMayStore]>;
352 def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
353 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
356 def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
358 def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
359 [SDNPHasChain, SDNPSideEffect]>;
361 //===----------------------------------------------------------------------===//
362 // Flow Control Profile Types
363 //===----------------------------------------------------------------------===//
364 // Branch instruction where second and third are basic blocks
365 def SDTIL_BRCond : SDTypeProfile<0, 2, [
369 //===----------------------------------------------------------------------===//
370 // Flow Control DAG Nodes
371 //===----------------------------------------------------------------------===//
372 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
374 //===----------------------------------------------------------------------===//
375 // Call/Return DAG Nodes
376 //===----------------------------------------------------------------------===//
377 def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
378 [SDNPHasChain, SDNPOptInGlue]>;
380 def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
381 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
383 def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
384 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]