1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the InstructionSelector class for
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #define GET_GLOBALISEL_PREDICATE_BITSET
25 #define AMDGPUSubtarget GCNSubtarget
26 #include "AMDGPUGenGlobalISel.inc"
27 #undef GET_GLOBALISEL_PREDICATE_BITSET
28 #undef AMDGPUSubtarget
33 class AMDGPUInstrInfo;
34 class AMDGPURegisterBankInfo;
38 class MachineRegisterInfo;
40 class SIMachineFunctionInfo;
43 class AMDGPUInstructionSelector : public InstructionSelector {
45 AMDGPUInstructionSelector(const GCNSubtarget &STI,
46 const AMDGPURegisterBankInfo &RBI,
47 const AMDGPUTargetMachine &TM);
49 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
50 static const char *getName();
54 const MachineInstr &GEP;
55 SmallVector<unsigned, 2> SgprParts;
56 SmallVector<unsigned, 2> VgprParts;
58 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
61 /// tblgen-erated 'select' implementation.
62 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
64 MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
65 bool selectCOPY(MachineInstr &I) const;
66 bool selectG_CONSTANT(MachineInstr &I) const;
67 bool selectG_ADD(MachineInstr &I) const;
68 bool selectG_GEP(MachineInstr &I) const;
69 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
70 bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
71 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
72 CodeGenCoverage &CoverageInfo) const;
73 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
74 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
75 SmallVectorImpl<GEPInfo> &AddrInfo) const;
76 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
77 bool selectG_LOAD(MachineInstr &I) const;
78 bool selectG_STORE(MachineInstr &I) const;
80 InstructionSelector::ComplexRendererFns
81 selectVCSRC(MachineOperand &Root) const;
83 InstructionSelector::ComplexRendererFns
84 selectVSRC0(MachineOperand &Root) const;
86 InstructionSelector::ComplexRendererFns
87 selectVOP3Mods0(MachineOperand &Root) const;
88 InstructionSelector::ComplexRendererFns
89 selectVOP3OMods(MachineOperand &Root) const;
90 InstructionSelector::ComplexRendererFns
91 selectVOP3Mods(MachineOperand &Root) const;
93 const SIInstrInfo &TII;
94 const SIRegisterInfo &TRI;
95 const AMDGPURegisterBankInfo &RBI;
96 const AMDGPUTargetMachine &TM;
97 const GCNSubtarget &STI;
98 bool EnableLateStructurizeCFG;
99 #define GET_GLOBALISEL_PREDICATES_DECL
100 #define AMDGPUSubtarget GCNSubtarget
101 #include "AMDGPUGenGlobalISel.inc"
102 #undef GET_GLOBALISEL_PREDICATES_DECL
103 #undef AMDGPUSubtarget
105 #define GET_GLOBALISEL_TEMPORARIES_DECL
106 #include "AMDGPUGenGlobalISel.inc"
107 #undef GET_GLOBALISEL_TEMPORARIES_DECL
110 } // End llvm namespace.